CY7C1355B CY7C1357B CY7C1357 CY7C1355 7C1355B-133 7C1357B-133 7C1355B-117 - Datasheet Archive

 

CY7C1357B PRELIMINARY 256Kx36/512Kx18 Flow-Through SRAM with NoBLTM Architecture Features · No Bus Latency (NoBL)

 

CY7C1355B CY7C1355B CY7C1357B CY7C1357B PRELIMINARY 256Kx36/512Kx18 Flow-Through SRAM with NoBLTM Architecture Features · No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles · Pin-for-pin compatible with ZBT Architecture · Fast access times: 6.5 ns, 7.5 ns, and 8.5 ns · Fast clock speed: 133, 117, and 100 MHz - 6.5 ns (for 133-MHz device) - 7.5 ns (for 117-MHz device) - 8.5 ns (for 100-MHz device) · Internally synchronized registered outputs eliminate the need to control OE · 3.3V ­5% and +5% power supply · 3.3V or 2.5V I/O supply · Single R/W (READ/WRITE) control pin · Positive clock-edge triggered, address, data, and control signal registers for fully pipelined applications · Interleaved or linear four-word burst capability · Individual byte write (BWa­BWd) control (may be tied LOW) · CEN pin to enable clock and suspend operations · Three chip enables for simple depth expansion · Automatic Power-down feature available using ZZ mode or CE deselect. · JTAG boundary scan for BGA and fBGA packages · Low profile 119-ball BGA, 165-ball fBGA, and 100-pin TQFP packages Functional Description The CY7C1355B CY7C1355B and CY7C1357B CY7C1357B SRAMs are flow-through synchronous SRAMs designed to eliminate dead cycles when transitions from READ to WRITE or vice versa. These SRAMs are optimized for 100 percent bus utilization with the No Bus Latency (NoBL) architecture. They integrate 262,144 x 36 and 524,288 x 18 SRAM cells, respectively, with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. These employ high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of Six transistors. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, depth-expansion Chip Enables (CE, CE2, and CE3), Cycle Start Input (ADV/LD), Clock Enable (CEN), Byte Write Enables (BWa, BWb, BWc, and BWd), and read-write control (R/W). BWc and BWd apply to CY7C1355B CY7C1355B only. There are three Chip Enable pins (CE, CE2, CE3) that allow the user to deselect the device when desired. If any one of these three are not active when ADV/LD is LOW, no new memory operation can be initiated and any burst cycle in progress is stopped. However, any pending data transfers (read or write) will be completed. The data bus will be in high-impedance state one cycle after chip is deselected or a write cycle is initiated. The CY7C1355B CY7C1355B and CY7C1357B CY7C1357B have an on-chip two-bit burst counter. In the burst mode, the CY7C1355B CY7C1355B and CY7C1357B CY7C1357B provide up to four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the MODE input pin. The MODE pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address (ADV/LD = LOW) or increment the internal burst counter (ADV/LD = HIGH). Logic Block Diagram CLK CE D Data-In REG. Q ADV/LD Ax CY7C1357 CY7C1357 CEN CE1 CE2 CE3 WE BWSx AX X = 17:0 X = 18:0 Mode DQX X = a, b, c, d X = a, b DQPX BWSX X = a, b, c, d X = a, b X = a, b, c, d X = a, b CY7C1355 CY7C1355 CONTROL and WRITE LOGIC 256K X 36/ 512K X 18 MEMORY ARRAY DQx DQPx OE Cypress Semiconductor Corporation Document #: 38-05117 Rev. *A · 3901 North First Street · San Jose · CA 95134 · 408-943-2600 Revised November 12, 2002 CY7C1355B CY7C1355B CY7C1357B CY7C1357B PRELIMINARY Selection Guide 7C1355B-133 7C1355B-133 7C1357B-133 7C1357B-133 7C1355B-117 7C1355B-117 7C1357B-117 7C1357B-117 7C1355B-100 7C1355B-100 7C1357B-100 7C1357B-100 Unit Maximum Access Time 6.5 7.5 8.5 ns Maximum Operating Current 250 220 180 mA Maximum CMOS Standby Current 30 30 30 mA Pin Configurations A A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 BWSd BWSc BWSb BWSa CE3 VDD VSS CLK WE CEN OE ADV/LD E(18) A 100-pin TQFP Package DQPc DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ CY7C1355B CY7C1355B (256K x 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQPa Document #: 38-05117 Rev. *A A A A A A A A E(36) E(72) VSS VDD E(288) E(144) MODE A A A A A1 A0 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQc DQc VSS/DNU VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Page 2 of 25 CY7C1355B CY7C1355B CY7C1357B CY7C1357B PRELIMINARY Pin Configurations (continued) A A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 NC NC BWSb BWSa CE3 VDD VSS CLK WE CEN OE ADV/LD E(18) A 100-pin TQFP Package NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb VSS/DNU VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ CY7C1357B CY7C1357B (512K x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC Document #: 38-05117 Rev. *A A A A A A A A E(36) E(72) VSS VDD E(288) E(144) MODE A A A A A1 A0 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Page 3 of 25 CY7C1355B CY7C1355B CY7C1357B CY7C1357B PRELIMINARY Pin Configurations (continued) 119-Ball BGA Pinout CY7C1355B CY7C1355B (256K x 36)­7 x 17 BGA 1 2 3 4 5 6 7 A VDDQ A A E(18) A A VDDQ B C D E F G H J K L M N P NC NC CE2 A A A ADV/LD VDD A A CE3 A NC NC DQc DQPc VSS NC VSS DQPb DQb R T U DQc DQc VSS CE1 VSS DQb DQb VDDQ DQc VSS OE VSS DQb VDDQ DQc DQc BWSc A BWSb DQb DQb DQc VDDQ DQc VDD VSS NC WE VDD VSS NC DQb VDD DQb VDDQ DQd DQd DQd DQd VSS BWSd CLK NC VSS BWSa DQa DQa DQa DQa VDDQ DQd VSS CEN VSS DQa VDDQ DQd DQd VSS A1 VSS DQa DQa DQd DQPd VSS A0 VSS DQPa DQa NC A MODE VDD NC A NC NC E(72) A A A E(36) ZZ VDDQ TMS TDI TCK TDO NC VDDQ CY7C1355B CY7C1355B (512K x 18)­7 x 17 BGA 1 A B C D E F G H J K L M N P R T U Document #: 38-05117 Rev. *A 2 3 4 5 6 7 VDDQ A A E(18) A A VDDQ NC CE2 A ADV/LD A CE3 NC NC A A VDD A A NC DQb NC VSS NC VSS DQPa NC NC DQb VSS CE1 VSS NC DQa VDDQ NC VSS OE VSS DQa VDDQ NC DQb VDDQ DQb NC VDD BWSb VSS NC A WE VDD VSS VSS NC NC DQa VDD DQa NC VDDQ DQa NC DQb VSS CLK VSS NC DQb NC VSS NC BWSa DQa NC VDDQ DQb VSS CEN VSS NC VDDQ DQb NC VSS A1 VSS DQa NC NC DQPb VSS A0 VSS NC DQa NC NC A MODE VDD NC A E(72) A A E(36) A A ZZ VDDQ TMS TDI TCK TDO NC VDDQ Page 4 of 25 PRELIMINARY CY7C1355B CY7C1355B CY7C1357B CY7C1357B Pin Definitions Pin Name I/O Type Pin Description A0 A1 A InputSynchronous Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK. BWSa BWSb BWSc BWSd InputSynchronous Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWSa controls DQa and DQPa, BWSb controls DQb and DQPb, BWSc controls DQc and DQPc, BWSd controls DQd and DQPd. WE InputSynchronous Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. ADV/LD InputSynchronous Advance/Load Input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. CE1 InputSynchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. CE2 InputSynchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE3 InputSynchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. OE InputAsynchronous Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. CEN InputSynchronous Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. DQa DQb DQc DQd I/OSynchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa­DQd are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DQPa DQPb DQPc DQPd I/OSynchronous Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During write sequences, DQPa is controlled by BWSa, DQPb is controlled by BWSb, DQPc is controlled by BWSc, and DQPd is controlled by BWSd. MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order. Power Supply Power supply inputs to the core of the device, 3.3V. VDD VDDQ VSS TDO I/O Power Supply Power supply for the 3.3V or 2.5V I/O circuitry. Ground Ground for the device. Should be connected to ground of the system. JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. Synchronous TDI JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. Synchronous TMS Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK. Synchronous Document #: 38-05117 Rev. *A Page 5 of 25 PRELIMINARY CY7C1355B CY7C1355B CY7C1357B CY7C1357B Pin Definitions Pin Name I/O Type Pin Description TCK JTAG-Clock NC ­ No connects. E(18,36,72, 144, 288) ­ These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M and 288M densities. InputAsynchronous ZZ "sleep" Input. This active HIGH input places the device in a non-time critical "sleep" condition with data integrity preserved. During normal operation, this pin can be connected to Vss or left floating. ZZ Clock input to the JTAG circuitry. Introduction Functional Overview The CY7C1355B/CY7C1357B CY7C1355B/CY7C1357B is a synchronous flow-through burst NoBL SRAM designed specifically to eliminate wait states during Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. Maximum access delay from the clock rise (tCDV) is 6.5 ns (133-MHz device). Accesses can be initiated by asserting Chip Enable(s) (CE1, CE2, CE3 on the TQFP, CE1 on the BGA) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a Read or Write operation, depending on the status of the Write Enable (WE). Byte Write Selects can be used to conduct byte write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry Synchronous Chip Enable (CE1, CE2, and CE3 on the TQFP, CE1 on the BGA) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and 4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers. The data is available within 6.5 ns (133-MHz device) provided OE is active LOW. After the first clock of the read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. On the subsequent clock, another operation (Read/Write/Deselect) can be initiated. When the SRAM is deselected at clock rise by one of the chip enable signals, its output will be three-stated immediately. Document #: 38-05117 Rev. *A Burst Read Accesses The CY7C1355B/CY7C1357B CY7C1355B/CY7C1357B has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) Chip Enable(s) asserted active, and (3) the write signal WE is asserted LOW. The address presented is loaded into the Address Register. The write signals are latched into the Control Logic block. The data lines are automatically three-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQ and DQP. On the next clock rise the data presented to DQ and DQP (or a subset for byte write operations, see Write Cycle Description table for details) inputs is latched into the device and the write is complete. Additional accesses (Read/Write/Deselect) can be initiated on this cycle. The data written during the Write operation is controlled by Byte Write Select signals. The CY7C1355B/ CY7C1355B/ CY7C1357B CY7C1357B provide byte write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations. Because the CY7C1355B/CY7C1357B CY7C1355B/CY7C1357B are common I/O devices, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQ and DQP inputs. Doing so will three-state the output drivers. As a safety precaution, DQ and DQP are automatically three-stated during the data portion of a write cycle, regardless of the state of OE. Page 6 of 25 CY7C1355B CY7C1355B CY7C1357B CY7C1357B PRELIMINARY Burst Write Accesses Sleep Mode The CY7C1355B/CY7C1357B CY7C1355B/CY7C1357B has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BWSa,b,c,d/BWSa,b inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. ZZ Mode Electrical Characteristics Parameter Description Test Conditions IDDZZ Snooze mode standby current tZZS Device operation to ZZ ZZ recovery time Unit mA 2tCYC ZZ < 0.2V Max. 35 ZZ > VDD - 0.2V tZZREC Min. ns ZZ > VDD - 0.2V 2tCYC ns Cycle Description Truth Table[1, 2, 3, 4, 5, 6] Address Used CE External 1 Suspend ­ Begin Read External Begin Write Operation Deselected CEN ADV/LD/ WE BWSx CLK 0 L X X 1 X X X L-H Clock ignored, all operations suspended. 0 0 0 1 X L-H Address latched. External 0 0 0 0 Valid Burst Read Operation Internal X 0 1 X X Burst Write Operation Internal X 0 1 X Valid Interleaved Burst Sequence X Comments L-H I/Os three-state following next recognized clock. L-H Address latched, data presented two valid clocks later. L-H Burst Read operation. Previous access was a Read operation. Addresses incremented internally in conjunction with the state of Mode. L-H Burst Write operation. Previous access was a Write operation. Addresses incremented internally in conjunction with the state of MODE. Bytes written are determined by BWS[d:a]. Linear Burst Sequence First Address Second Address Third Address Fourth Address First Address Second Address Third Address Fourth Address A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] 00 01 10 11 00 01 10 11 01 00 11 10 01 10 11 00 10 11 00 01 10 11 00 01 11 10 01 00 11 00 01 10 Notes: 1. X = "don't care," 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL Chip Enables active. BWSx = 0 signifies at least one Byte Write Select is active, BWSx = Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details. 2. Write is defined by WE and BWSx. See Write Cycle Description table for details. 3. The DQ and DQP pins are controlled by the current cycle and the OE signal. 4. CEN = 1 inserts wait states. 5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE. 6. OE assumed LOW. Document #: 38-05117 Rev. *A Page 7 of 25 CY7C1355B CY7C1355B CY7C1357B CY7C1357B PRELIMINARY Write Cycle Description[1, 2] Function (CY7C1355B CY7C1355B) WE BWSd BWSc BWSb BWSa Read 1 X X X X Write ­ No bytes written 0 1 1 1 1 Write Byte 0 ­ (DQa and DQPa) 0 1 1 1 0 Write Byte 1 ­ (DQb and DQPb) 0 1 1 0 1 Write Bytes 1, 0 0 1 1 0 0 Write Byte 2 ­ (DQc and DQPc) 0 1 0 1 1 Write Bytes 2, 0 0 1 0 1 0 Write Bytes 2, 1 0 1 0 0 1 Write Bytes 2, 1, 0 0 1 0 0 0 Write Byte 3 ­ (DQd and DQPd) 0 0 1 1 1 Write Bytes 3, 0 0 0 1 1 0 Write Bytes 3, 1 0 0 1 0 1 Write Bytes 3, 1, 0 0 0 1 0 0 Write Bytes 3, 2 0 0 0 1 1 Write Bytes 3, 2, 0 0 0 0 1 0 Write Bytes 3, 2, 1 0 0 0 0 1 Write All Bytes 0 0 0 0 0 WE BWSb BWSa Read 1 x x Write ­ No Bytes Written 0 1 1 Write Byte 0 ­ (DQa and DQPa) 0 1 0 Write Byte 1 ­ (DQb and DQPb) 0 0 1 Write Both Bytes 0 0 0 Function (CY7C1357B CY7C1357B) IEEE 1149.1 Serial Boundary Scan (JTAG) Test Access Port­Test Clock The CY7C1355B/CY7C1357B CY7C1355B/CY7C1357B incorporates a serial boundary scan Test Access Port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 3.3V or 2.5V I/O logic levels. The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Disabling the JTAG Feature The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register. It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) Test Data Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current Document #: 38-05117 Rev. *A Page 8 of 25 PRELIMINARY CY7C1355B CY7C1355B CY7C1357B CY7C1357B state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK. TDO is connected to the Least Significant Bit (LSB) of any register. into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. Performing a TAP Reset TAP Instruction Set A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. TAP Registers The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address, data, or control signals into the SRAM and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather it performs a capture of the Inputs and Output ring when these instructions are executed. Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in the TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The x36 configuration has a xx-bit-long register, and the x18 configuration has a yy-bit-long register. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired Document #: 38-05117 Rev. *A Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in the TAP controller, and therefore this device is not compliant to the 1149.1 standard. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1-compliant. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. Page 9 of 25 PRELIMINARY CY7C1355B CY7C1355B CY7C1357B CY7C1357B The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register. Bypass Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Document #: 38-05117 Rev. *A Page 10 of 25 CY7C1355B CY7C1355B CY7C1357B CY7C1357B PRELIMINARY TAP Controller State Diagram[7] 1 TEST-LOGIC RESET 0 TEST-LOGIC/ IDLE 1 1 1 SELECT DR-SCAN SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-DR 0 0 0 SHIFT-DR 0 SHIFT-IR 1 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR 0 0 PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR 1 0 UPDATE-IR 1 0 Note: 7. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05117 Rev. *A Page 11 of 25 CY7C1355B CY7C1355B CY7C1357B CY7C1357B PRELIMINARY TAP Controller Block Diagram 0 Bypass Register Selection Circuitry 2 TDI 1 0 1 0 1 Selection Circuitry 0 TDO Instruction Register 31 30 29 . . 2 Identification Register 68 . . . . 2 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range[8, 9] Parameter Description Test Conditions VOH1 Output HIGH Voltage VOH2 Output HIGH Voltage VOL1 Output LOW Voltage IOL = 2.0 mA VOL2 Output LOW Voltage IOL = 100 µA VIH Input HIGH Voltage VDDQ = 3.3V VIL Input LOW Voltage IX Input Load Current Min. Max. Unit IOH = ­2.0 mA, VDDQ = 3.3V 2.0 V IOH = ­2.0 mA, VDDQ = 2.5V 1.7 V IOH = ­100 µA, VDDQ = 3.3V 2.0 V IOH = ­100 µA, VDDQ = 2.5V 2.0 VDDQ = 2.5V V 0.7 0.2 2.0 V V VDD + 0.3 V 1.7 V ­0.3 GND VI VDDQ 0.7 V ­30 30 µA TAP AC Switching Characteristics Over the Operating Range[10, 11] Parameter Description Min. Max. Unit 10 MHz tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency 100 ns tTH TCK Clock HIGH 40 ns tTL TCK Clock LOW 40 ns Notes: 8. All voltage referenced to ground. 9. Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC/2; undershoot: VIL(AC) < 0.5V for t < tTCYC/2; power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms. 10. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 11. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns. Document #: 38-05117 Rev. *A Page 12 of 25 CY7C1355B CY7C1355B CY7C1357B CY7C1357B PRELIMINARY TAP AC Switching Characteristics Over the Operating Range[10, 11] Parameter Description Min. Max. Unit Set-up Times tTMSS TMS Set-up to TCK Clock Rise 10 ns tTDIS TDI Set-up to TCK Clock Rise 10 ns tCS Capture Set-up to TCK Rise 10 ns tTMSH TMS Hold after TCK Clock Rise 10 ns tTDIH TDI Hold after Clock Rise 10 ns tCH Capture Hold after clock rise 10 ns Hold Times Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 20 0 ns ns TAP Timing and Test Conditions 1.5/1.25V ALL INPUT PULSES 3.0/2.5V 50 1.5/1.25V 0V TDO Z0 = 50 CL = 20 pF (a) GND tTH tTL Test Clock TCK tTCYC tTMSS tTMSH Test Mode Select TMS tTDIS tTDIH Test Data-In TDI Test Data-Out TDO tTDOV Document #: 38-05117 Rev. *A tTDOX Page 13 of 25 CY7C1355B CY7C1355B CY7C1357B CY7C1357B PRELIMINARY Identification Register Definitions Instruction Field Value Description Revision Number (31:28) TBD Reserved for version number. Device Depth (27:23) TBD Defines depth of SRAM. Device Width (22:18) TBD Defines with of the SRAM. Cypress Device ID (17:12) TBD Reserved for future use. Cypress JEDEC ID (11:1) TBD Allows unique identification of SRAM vendor. ID Register Presence (0) TBD Indicate the presence of an ID register. Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 69 Identification Codes Instruction Code Description EXTEST 000 Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Boundary Scan Exit Order (×36) (continued) Boundary Scan Exit Order (×36) Bit # Signal Name 119-ball ID 165-ball ID Bit # Signal Name 119-ball ID 165-ball ID TBD TBD TBD 1 TBD TBD TBD 13 2 TBD TBD TBD 14 TBD TBD TBD TBD TBD TBD 3 TBD TBD TBD 15 4 TBD TBD TBD 16 TBD TBD TBD TBD TBD TBD 5 TBD TBD TBD 17 6 TBD TBD TBD 18 TBD TBD TBD TBD TBD TBD 7 TBD TBD TBD 19 8 TBD TBD TBD 20 TBD TBD TBD TBD TBD TBD 9 TBD TBD TBD 21 10 TBD TBD TBD 22 TBD TBD TBD TBD TBD TBD TBD TBD TBD 11 TBD TBD TBD 23 12 TBD TBD TBD 24 Document #: 38-05117 Rev. *A Page 14 of 25 CY7C1355B CY7C1355B CY7C1357B CY7C1357B PRELIMINARY Boundary Scan Exit Order (×36) (continued) Boundary Scan Exit Order (×36) (continued) Bit # Signal Name 119-ball ID 165-ball ID Bit # Signal Name 119-ball ID 165-ball ID 25 TBD TBD TBD 68 TBD TBD TBD 26 TBD TBD TBD 69 TBD TBD TBD 27 TBD TBD TBD 70 TBD TBD TBD 28 TBD TBD TBD 29 TBD TBD TBD 30 TBD TBD TBD 31 TBD TBD TBD Bit # Signal Name 119- ball ID 165- ball ID 32 TBD TBD TBD 1 TBD TBD TBD 33 TBD TBD TBD 2 TBD TBD TBD 34 TBD TBD TBD 3 TBD TBD TBD 35 TBD TBD TBD 4 TBD TBD TBD 36 TBD TBD TBD 5 TBD TBD TBD 37 TBD TBD TBD 6 TBD TBD TBD 38 TBD TBD TBD 7 TBD TBD TBD 39 TBD TBD TBD 8 TBD TBD TBD 40 TBD TBD TBD 9 TBD TBD TBD 41 TBD TBD TBD 10 TBD TBD TBD 42 TBD TBD TBD 11 TBD TBD TBD 43 TBD TBD TBD 12 TBD TBD TBD 44 TBD TBD TBD 13 TBD TBD TBD 45 TBD TBD TBD 14 TBD TBD TBD 46 TBD TBD TBD 15 TBD TBD TBD 47 TBD TBD TBD 16 TBD TBD TBD 48 TBD TBD TBD 17 TBD TBD TBD 49 TBD TBD TBD 18 TBD TBD TBD 50 TBD TBD TBD 19 TBD TBD TBD 51 TBD TBD TBD 20 TBD TBD TBD 52 TBD TBD TBD 21 TBD TBD TBD 53 TBD TBD TBD 22 TBD TBD TBD 54 TBD TBD TBD 23 TBD TBD TBD 55 TBD TBD TBD 24 TBD TBD TBD 56 TBD TBD TBD 25 TBD TBD TBD 57 TBD TBD TBD 26 TBD TBD TBD 58 TBD TBD TBD 27 TBD TBD TBD 59 TBD TBD TBD 28 TBD TBD TBD 60 TBD TBD TBD 29 TBD TBD TBD 61 TBD TBD TBD 30 TBD TBD TBD 62 TBD TBD TBD 31 TBD TBD TBD 63 TBD TBD TBD 32 TBD TBD TBD 64 TBD TBD TBD 33 TBD TBD TBD 65 TBD TBD TBD 34 TBD TBD TBD 66 TBD TBD TBD 35 TBD TBD TBD 67 TBD TBD TBD 36 TBD TBD TBD Document #: 38-05117 Rev. *A Boundary Scan Exit Order (×18) Page 15 of 25 PRELIMINARY CY7C1355B CY7C1355B CY7C1357B CY7C1357B Boundary Scan Exit Order (×18) Bit # Signal Name 119- ball ID 165- ball ID 37 TBD TBD TBD 38 TBD TBD TBD 39 TBD TBD TBD 40 TBD TBD TBD 41 TBD TBD TBD 42 TBD TBD TBD 43 TBD TBD TBD 44 TBD TBD TBD 45 TBD TBD TBD 46 TBD TBD TBD 47 TBD TBD TBD 48 TBD TBD TBD 49 TBD TBD TBD 50 TBD TBD TBD 51 TBD TBD TBD Document #: 38-05117 Rev. *A Page 16 of 25 CY7C1355B CY7C1355B CY7C1357B CY7C1357B PRELIMINARY Current into Outputs (LOW). 20 mA Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .­65°C to +150°C Static Discharge Voltage. > 2001V (per MIL-STD-883 MIL-STD-883, Method 3015) Latch-up Current. > 200 mA Operating Range Ambient Temperature with Power Applied. ­55°C to +125°C Supply Voltage on VDD Relative to GND . ­0.5V to +3.6V Range Ambient Temperature[12] DC to Outputs in High-Z State[13] . ­0.5V to VDDQ + 0.5V Com'l 0°C to +70°C DC Input Voltage[13] . ­0.5V to VDDQ + 0.5V VDD/VDDQ 3.135 ­ 3.6V / 3.135 ­ 3.6V or 2.375 ­ 2.9V Electrical Characteristics Over the Operating Range[1212] Parameter Description Test Conditions Unit 3.6 V 3.135 VDD V VDDQ = 2.5V I/O Supply Voltage Max. 2.375 2.9 V Power Supply Voltage VDDQ Min. 3.135 VDDQ = 3.3V VDD Output HIGH Voltage VDD = Min., IOH = -4.0 mA, VDDQ = 3.3V 2.4 V VDD = Min., IOH = -1.0 mA, VDDQ = 2.5V VOH 2.0 V VIH Output LOW Voltage 0.4 V 0.4 V Input LOW Voltage 2.0 VDDQ + 0.3V V 1.7 VDDQ = 3.3V ­0.3 0.8 V VDDQ = 2.5V [13] VDDQ = 3.3V VDDQ = 2.5V VIL Input HIGH Voltage VDD = Min., IOH = 8.0 mA, VDDQ = 3.3V VDD = Min., IOH = 1.0 mA, VDDQ = 2.5V VOL ­0.3 0.7 V ­5 5 µA GND VI VDDQ V IX Input Load Current except ZZ and MODE IOZ Output Leakage Current GND VI VDDQ, Output Disabled ­5 5 µA IZZ Input Current of MODE and ZZ pins ­0 30 µA IDD VDD Operating Supply Current 7.5-ns cycle, 133 MHz 250 mA 8.8-ns cycle, 117 MHz 220 mA 10-ns cycle, 100 MHz 180 mA ISB1 Automatic CS Power-down Current-TTL Inputs VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC Max. VDD, Device Deselected, VIN > VIH or VIN < VIL f = fMAX = 1/tCYC 7.5-ns cycle, 133 MHz TBD mA 8.8-ns cycle, 117 MHz TBD mA 10-ns cycle, 100 MHz TBD mA 30 mA ISB2 Automatic CS Max. VDD, Device Deselected, Power-down VIN < 0.3V or VIN > VDDQ ­ 0.3V, f Current-CMOS Inputs = 0 ISB3 Automatic CS Max. VDD, Device Deselected, or 7.5-ns cycle, 133 MHz Power-down VIN < 0.3V or VIN > VDDQ ­ 0.3V 8.8-ns cycle, 117 MHz Current-CMOS Inputs f = fMAX = 1/tCYC 10-ns cycle, 100 MHz TBD mA TBD mA TBD mA Automatic CS Power-down Current-TTL Inputs TBD mA ISB4 Max. VDD, Device Deselected, VIN > VIH or VIN < VIL, f = 0 Notes: 12. Minimum voltage equals -2.0V for pulse durations of less than 1 ns or -0.5V for 20 ns. 13. The load used for VOH and VOL testing is shown in figure (b) of the A/C test conditions. Document #: 38-05117 Rev. *A Page 17 of 25 CY7C1355B CY7C1355B CY7C1357B CY7C1357B PRELIMINARY Capacitance[14,16] Parameter Description CIN Input Capacitance CCLK Clock Input Capacitance CI/O Test Conditions Input/Output Capacitance Max. 4 pF 4 pF 4 TA = 25°C, f = 1 MHz, VDD = 3.3V VDDQ = 2.5V Unit pF Thermal Resistance Parameter Description Test Conditions QJA Thermal Resistance (Junction to Ambient) QJC Thermal Resistance (Junction to Case) BGA Typ fBGA Typ. TQFP Typ. Unit Notes 25 27 25 °C/W 16 6 6 9 °C/W 16 Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board 3.0V/2.5V OUTPUT R = 317/1667 ALL INPUT PULSES OUTPUT Z0 = 50 RL = 50 VL = 1.5V/2.5V (a) Switching Characteristics 3.0/2.5V 5 pF INCLUDING JIG AND SCOPE 90% 10% 3V/ns (c) (b) Over the Operating Range [17] Description 90% 10% 1.5/1.25V GND R = 351/1538 3V/ns -133 Parameter [15] Min. -117 Max. Min. -100 Max. Min. Max. Unit Clock tCYC Clock Cycle Time 7.5 8.5 FMAX Maximum Operating Frequency tCH Clock HIGH 3.0 3.2 4.0 ns tCL Clock LOW 3.0 3.2 4.0 ns 133 10 117 ns 100 MHz Output Times tCO Data Output Valid After CLK Rise 6.5 7.5 8.5 ns tEOV OE LOW to Output Valid[16, 18, 20] 3.5 3.5 3.5 ns tDOH Data Output Hold After CLK Rise tCHZ Clock to High-Z[16, 17, 18, 19, 20] 0 tCLZ Clock to Low-Z[16, 17, 18, 19, 20] 0 tEOHZ OE HIGH to Output High-Z[17, 18, 20] tEOLZ OE LOW to Output Low-Z[17, 18, 20] 2.0 2.0 3.5 0 2.0 3.5 0 3.5 0 ns 3.5 0 3.5 ns ns 3.5 ns 0 0 0 ns Set-up Times tAS Address Set-up Before CLK Rise 1.5 1.5 1.5 ns tDS Data Input Set-up Before CLK Rise 1.5 1.5 1.5 ns tCENS CEN Set-up Before CLK Rise 1.5 1.5 1.5 ns tWES WE, BWSx Set-up Before CLK Rise 1.5 1.5 1.5 ns Notes: 14. TA is the case temperature. 15. Input waveform should have a slew rate of > 1 V/ns. 16. Tested initially and after any design or process change that may affect these parameters. 17. Unless otherwise noted, test conditions assume signal transition time of 1 ns or less, timing reference levels of 1.5V or 1.25V, input pulse levels of 0 to 3.0V or 2.5V, and output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b) and (c) of AC test loads. 18. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with AC test conditions shown in (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 19. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 20. This parameter is sampled and not 100% tested. Document #: 38-05117 Rev. *A Page 18 of 25 CY7C1355B CY7C1355B CY7C1357B CY7C1357B PRELIMINARY Switching Characteristics Over the Operating Range (continued)[17] -133 Parameter Description Min. -117 Max. Min. -100 Max. Min. Max. Unit tALS ADV/LD Set-up Before CLK Rise 1.5 1.5 1.5 ns tCES Chip Select Set-up 1.5 1.5 1.5 ns tAH Address Hold After CLK Rise 0.5 0.5 0.5 ns tDH Data Input Hold After CLK Rise 0.5 0.5 0.5 ns tCENH CEN Hold After CLK Rise 0.5 0.5 0.5 ns tWEH WE, BWx Hold After CLK Rise 0.5 0.5 0.5 ns tALH ADV/LD Hold after CLK Rise 0.5 0.5 0.5 ns tCEH Chip Select Hold After CLK Rise 0.5 0.5 0.5 ns Hold Times DESELECT DESELECT Suspend Read Write Read DESELECT Read Read Write Read/Write/Deselect Sequence[21] Read Switching Waveforms CLK tCENH tCENS tCH tCL tCENH tCENS tCYC CEN tAS ADDRESS WA2 RA1 RA4 RA3 WA5 RA6 RA7 tAH WE tWES tCES tWEH tCEH CE tCLZ tCHZ tDOH Data In/Out Q1 Out tCHZ D2 In Q3 Out Q4 Out D5 In Device tCDV originally deselected Q6 Out Q7 Out tDOH = DON'T CARE = UNDEFINED Note: 21. WE is the combination of WE and BWSx(x = a, b, c, d) to define a write cycle (see Write Cycle Description table). CE is the combination of CE1, CE2, and CE3. All chip selects need to be active in order to select the device. Any chip select can deselect the device. RAx stands for Read Address X, WA stands for Write Address X, Dx stands for Data-in X, Qx stands for Data-out X. Document #: 38-05117 Rev. *A Page 19 of 25 CY7C1355B CY7C1355B CY7C1357B CY7C1357B PRELIMINARY Burst Read Burst Read Begin Read Burst Write Burst Write Burst Write Begin Write Burst Read Burst Sequences[22] Burst Read Burst Read Switching Waveforms (continued) CLK tALH tALS tCH tCL tCYC ADV/LD tAS tAH ADDRESS RA1 WA2 RA3 WE tWEH tWES tWS tWH BWSx tCES tCEH CE tCLZ Data In/Out tCHZ tDOH Q1 1a Out tCDV t DeviceCDV originally deselected Q1+1 Out Q1+2 Out tCLZ tDH Q1+3 Out D2 In D2+1 In D2+2 In D2+3 In Q3 Out Q3+1 Out tDS Notes: 22. The combination of WE and BWSx(x = a, b, c, d) define a write cycle (see Write Cycle Description table). CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select the device. Any chip enable can deselect the device. RAx stands for Read Address X, WA stands for Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWSx input signals. Burst order determined by the state of the MODE input. CEN held LOW. OE held LOW. Document #: 38-05117 Rev. *A Page 20 of 25 CY7C1355B CY7C1355B CY7C1357B CY7C1357B PRELIMINARY Switching Waveforms (continued) OE tEOV tEOHZ Three-State I/Os tEOLZ Ordering Information Speed (MHz) 133 Ordering Code CY7C1355B-133AC CY7C1355B-133AC CY7C1357B-133AC CY7C1357B-133AC Package Name A101 CY7C1355B-133BGC CY7C1355B-133BGC CY7C1357B-133BGC CY7C1357B-133BGC CY7C1355B-133BZC CY7C1355B-133BZC CY7C1357B-133BZC CY7C1357B-133BZC 117 BG119 BG119 BB165A BB165A CY7C1355B-117AC CY7C1355B-117AC CY7C1357B-117AC CY7C1357B-117AC A101 CY7C1355B-117BGC CY7C1355B-117BGC CY7C1357B-117BGC CY7C1357B-117BGC CY7C1355B-117BZC CY7C1355B-117BZC CY7C1357B-117BZC CY7C1357B-117BZC 100 BG119 BG119 BB165A BB165A CY7C1355B-100AC CY7C1355B-100AC CY7C1357B-100AC CY7C1357B-100AC A101 CY7C1355B-100BGC CY7C1355B-100BGC CY7C1357B-100BGC CY7C1357B-100BGC BG119 BG119 CY7C1355B-100BZC CY7C1355B-100BZC CY7C1357B-100BZC CY7C1357B-100BZC BB165A BB165A Document #: 38-05117 Rev. *A Package Type 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Operating Range Commercial 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 165-ball fine pitch Ball Grid Array (13 x 15 x 1.2 mm) 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 165-ball fine pitch Ball Grid Array (13 x 15 x 1.2 mm) 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 165-ball fine pitch Ball Grid Array (13 x 15 x 1.2 mm) Page 21 of 25 PRELIMINARY CY7C1355B CY7C1355B CY7C1357B CY7C1357B Package Diagram 100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-A Document #: 38-05117 Rev. *A Page 22 of 25 PRELIMINARY CY7C1355B CY7C1355B CY7C1357B CY7C1357B Package Diagram (continued) 119-Lead PBGA (14 x 22 x 2.4 mm) BG119 BG119 51-85115-*B Document #: 38-05117 Rev. *A Page 23 of 25 PRELIMINARY CY7C1355B CY7C1355B CY7C1357B CY7C1357B Package Diagram (continued) 165-Ball FBGA (13 x 15 x 1.2 mm) BB165A BB165A 51-85122-*C No Bus Latency and NoBL are trademarks of Cypress Semiconductor. ZBT is a registered trademark of Integrated Device Technology, Inc. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05117 Rev. *A Page 24 of 25 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1355B CY7C1355B CY7C1357B CY7C1357B PRELIMINARY Document History Page Document Title: CY7C1355B/CY7C1357B CY7C1355B/CY7C1357B 256Kx36/512Kx18 Flow-Through SRAM with NoBLTM Architecture Document Number: 38-05117 REV. Orig. of Change ECN No. Issue Date * 117908 08/28/02 RCS New Data Sheet *A 121067 11/13/02 DSG Updated package drawings 51-85115 (BG119 BG119) to *B and 51-85122 (BB165A BB165A) to *C Document #: 38-05117 Rev. *A Description of Change Page 25 of 25