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CY7C1316JV18 Cypress Semiconductor 18-Mbit DDR-II SRAM 2-Word Burst Architecture
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26 pages,
406.03 Kb

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Abstract: CY7C1316JV18, CY7C1916JV18 CY7C1916JV18 CY7C1318JV18 CY7C1318JV18, CY7C1320JV18 CY7C1320JV18 18-Mbit DDR-II SRAM 2-Word Burst , 1.5 cycle read latency when the DLL is enabled The CY7C1316JV18, CY7C1916JV18 CY7C1916JV18, CY7C1318JV18 CY7C1318JV18, and , two 8-bit words in the case of CY7C1316JV18 and two 9-bit words in the case of CY7C1916JV18 CY7C1916JV18 that , the case of CY7C1316JV18 and CY7C1916JV18 CY7C1916JV18. For CY7C1318JV18 CY7C1318JV18 and CY7C1320JV18 CY7C1320JV18, the burst counter , Configurations CY7C1316JV18 ­ 2M x 8 CY7C1916JV18 CY7C1916JV18 ­ 2M x 9 CY7C1318JV18 CY7C1318JV18 ­ 1M x 18 CY7C1320JV18 CY7C1320JV18 ­ 512K x 36 ... Original
datasheet

26 pages,
406.03 Kb

CY7C1916JV18 CY7C1320JV18 CY7C1318JV18 CY7C1316JV18 CY7C1316JV18 abstract
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