CY7C1031 CY7C1032 7C1031 7C1032 MIL-STD-883 12YMB - Datasheet Archive

 

CY7C1031 CY7C1032 PRELIMINARY 64K x 18 Synchronous Cache RAM Features Functional Description · Supports 66-MHz PentiumTM

 

1CY 7C10 32 CY7C1031 CY7C1031 CY7C1032 CY7C1032 PRELIMINARY 64K x 18 Synchronous Cache RAM Features Functional Description · Supports 66-MHz PentiumTM microprocessor cache systems with zero wait states · 64K by 18 common I/O · Fast clock-to-output times - 8.5 ns · Two-bit wraparound counter supporting Pentium microprocessor and 486 burst sequence (7C1031 7C1031) · Two-bit wraparound counter supporting linear burst sequence (7C1032 7C1032) · Separate processor and controller address strobes · Synchronous self-timed write · Direct interface with the processor and external cache controller · Asynchronous output enable · I/Os capable of 3.3V operation · JEDEC-standard pinout · 52-pin PLCC and PQFP packaging The CY7C1031 CY7C1031 and CY7C1032 CY7C1032 are 64K by 18 synchronous cache RAMs designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.5 ns. A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. The CY7C1031 CY7C1031 is designed for Intel Pentium and i486 CPU-based systems; its counter follows the burst sequence of the Pentium and the i486 processors. The CY7C1032 CY7C1032 is architected for processors with linear burst sequences. Burst accesses can be initiated with the processor address strobe (ADSP) or the cache controller address strobe (ADSC) inputs. Address advancement is controlled by the address advancement (ADV) input. A synchronous self-timed write mechanism is provided to simplify the write interface. A synchronous chip select input and an asynchronous output enable input provide easy control for bank selection and output three-state control. Logic Block Diagram Pin Configuration PLCC Top View 18 16 DATA IN REGISTER 14 A15 ­ A0 ADDR REG 9 9 DQ8 DQ9 VCCQ VSSQ DQ10 DQ11 DQ12 DQ13 VSSQ VCCQ DQ14 DQ15 DP1[1] 14 16 2 2 ADV ADV LOGIC WH CLK ADSP ADSC CS WH WL 64K X 9 64K X 9 RAM ARRAY RAM ARRAY TIMING CONTROL WL 9 9 8 9 10 11 12 13 14 15 16 17 18 19 20 7 6 5 4 3 2 1 52 51 50 49 48 47 46 45 44 43 42 41 7C1031 7C1031 7C1032 7C1032 40 39 38 37 36 35 34 2122 23 24 25 26 27 28 29 30 31 32 33 [1] DP0 DQ7 DQ6 VCCQ VSSQ DQ5 DQ4 DQ3 DQ2 VSSQ VCCQ DQ1 DQ0 18 1031­1 DQ15 ­ DQ0 DP1 ­ DP0 OE 1031­2 Selection Guide Maximum Access Time (ns) Maximum Operating Current (mA) Commercial Military 7C1031 7C1031­7 7C1032 7C1032­7 7 300 7C1031 7C1031­8 7C1032 7C1032­8 8.5 280 7C1031 7C1031­10 7C1032 7C1032­10 10 280 7C1031 7C1031­12 7C1032 7C1032­12 12 230 235 Shaded area contains advanced information. Pentium is a trademark of Intel Corporation. Note: 1. DP0 and DP1 are functionally equivalent to DQx. Cypress Semiconductor Corporation · 3901 North First Street · San Jose · CA 95134 · 408-943-2600 January 1993 ­ Revised March 1995 CY7C1031 CY7C1031 CY7C1032 CY7C1032 PRELIMINARY Functional Description (continued) is LOW, and (3) WH and WL are HIGH. The address at A0 through A 15 is stored into the address advancement logic and delivered to the RAM core. If the output enable (OE) signal is asserted (LOW), data will be available at the data outputs a maximum of 8.5 ns after clock rise. ADSP is ignored if CS is HIGH. Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CS is LOW and (2) ADSP is LOW. ADSP-triggered write cycles are completed in two clock periods. The address at A0 through A15 is loaded into the address register and address advancement logic and delivered to the RAM core. The write signal is ignored in this cycle because the cache tag or other external logic uses this clock period to perform address comparisons or protection checks. If the write is allowed to proceed, the write input to the CY7C1031 CY7C1031 and CY7C1032 CY7C1032 will be pulled LOW before the next clock rise. ADSP is ignored if CS is HIGH. Burst Sequences The CY7C1031 CY7C1031 provides a 2-bit wraparound counter, fed by pins A0 ­ A1, that implements the Intel 80486 and Pentium processor's address burst sequence (see Table 1). Note that the burst sequence depends on the first burst address. Table 1. Counter Implementation for the Intel Pentium/80486 Processor's Sequence If WH, WL, or both are LOW at the next clock rise, information presented at DQ0 ­ DQ15 and DP0 ­ DP1 will be written into the location specified by the address advancement logic. WL controls the writing of DQ0 ­ DQ7 and DP0 while WH controls the writing of DQ8 ­ DQ15 and DP1. Because the CY7C1031 CY7C1031 and CY7C1032 CY7C1032 are common-I/O devices, the output enable signal (OE) must be deasserted before data from the CPU is delivered to DQ0 ­ DQ15 and DP0 ­ DP1. As a safety precaution, the appropriate data lines are three-stated in the cycle where WH, WL, or both are sampled LOW, regardless of the state of the OE input. First Address AX + 1, Ax 00 01 10 11 Single Write Accesses Initiated by ADSC Second Address AX + 1, Ax 01 00 11 10 Third Address AX + 1, Ax 10 11 00 01 Fourth Address AX + 1, Ax 11 10 01 00 The CY7C1032 CY7C1032 provides a two-bit wraparound counter, fed by pins A0 ­ A1, that implements a linear address burst sequence (see Table 2). This write access is initiated when the following conditions are satisfied at rising edge of the clock: (1) CS is LOW, (2) ADSC is LOW, and (3) WH or WL are LOW. ADSC triggered accesses are completed in a single clock cycle. Table 2. Counter Implementation for a Linear Sequence The address at A0 through A15 is loaded into the address register and address advancement logic and delivered to the RAM core. Information presented at DQ0 ­ DQ15 and DP0 ­ DP1 will be written into the location specified by the address advancement logic. Since the CY7C1031 CY7C1031 and the CY7C1032 CY7C1032 are common-I/O devices, the output enable signal (OE) must be deasserted before data from the cache controller is delivered to the data and parity lines. As a safety precaution, the appropriate data and parity lines are three-stated in the cycle where WH and WL are sampled LOW regardless of the state of the OE input. First Address A X + 1, Ax 00 01 10 11 Second Address AX + 1, Ax 01 10 11 00 Third Address AX + 1, Ax 10 11 00 01 Fourth Address AX + 1, Ax 11 00 01 10 Application Example Figure 1 shows a 512-Kbyte secondary cache for the Pentium microprocessor using four CY7C1031 CY7C1031 cache RAMs. Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise: (1) CS is LOW, (2) ADSP or ADSC 2 CY7C1031 CY7C1031 CY7C1032 CY7C1032 PRELIMINARY 512 KB 66­MHz OSC CLK CLK ADR ADR DATA DATA ADS ADSP ADSC PENTIUM PROCESSOR 7C1031 7C1031 ADV WH, WL OE WH, WL WH, WL WH, WL 2 CLK ADR CD CACHE TAG DATA MATCH DIRTY VALID 2 2 2 WH1 , CLK ADSC ADV OE WH0 , WL1 WL0 ADR DATA ADSP CACHE CONTROLLER WH2 , WL2 WH3 , WL3 INTERFACE TO MAIN MEMORY MATCH DIRTY VALID Figure 1. Cache Using Four CY7C1031s Pin Definitions Signal Name VCC VCCQ GND VSSQ CLK A15 ­ A0 ADSP ADSC WH WL ADV OE CS DQ15­DQ0 DP1­DP0 Type Input Input Input Input Input Input Input Input Input Input Input Input Input Input/Output Input/Output # of Pins 1 4 1 4 1 16 1 1 1 1 1 1 1 16 2 3 Description +5V Power +5V or 3.3V (Outputs) Ground Ground (Outputs) Clock Address Address Strobe from Processor Address Strobe from Cache Controller Write Enable ­ High Byte Write Enable ­ Low Byte Advance Output Enable Chip Select Regular Data Parity Data CY7C1031 CY7C1031 CY7C1032 CY7C1032 PRELIMINARY Pin Descriptions Signal Name I/O Pin Descriptions (continued) Signal Name Description Input Signals I/O ADV CLK I A15­A 0 I Advance. This signal is sampled by the rising edge of CLK. When it is asserted, it automatically increments the 2-bit on-chip auto-address-increment counter. In the CY7C1032 CY7C1032, the address will be incremented linearly. In the CY7C1031 CY7C1031, the address will be incremented according to the Pentium/486 burst sequence. This signal is ignored if ADSP or ADSC is asserted concurrently with CS. Note that ADSP has no effect on ADV if CS is HIGH. CS I Chip select. This signal is sampled by the rising edge of CLK. If CS is HIGH and ADSC is LOW, the SRAM is deselected. If CS is LOW and ADSC or ADSP is LOW, a new address is captured by the address register. If CS is HIGH, ADSP is ignored. OE Sixteen address lines used to select one of 64K locations. They are captured in an on-chip register on the rising edge of CLK if ADSP or ADSC is LOW. The rising edge of the clock also loads the lower two address lines, A1 ­ A 0, into the on-chip auto-address-increment logic if ADSP or ADSC is LOW. I I Output enable. This signal is an asynchronous input that controls the direction of the data I/O pins. If OE is asserted (LOW), the data pins are outputs, and the SRAM can be read (as long as CS was asserted when it was sampled at the beginning of the cycle). If OE is deasserted (HIGH), the data I/O pins will be three-stated, functioning as inputs, and the SRAM can be written. Clock signal. It is used to capture the address, the data to be written, and the following control signals: ADSP, ADSC, CS, WH, WL, and ADV. It is also used to advance the on-chip auto-address-increment logic (when the appropriate control signals have been set). ADSP ADSC WH WL I I I I Description Address strobe from processor. This signal is sampled at the rising edge of CLK. When this input and/or ADSC is asserted, A0­A15 will be captured in the on-chip address register. It also allows the lower two address bits to be loaded into the on-chip auto-address-increment logic. If both ADSP and ADSC are asserted at the rising edge of CLK, only ADSP will be recognized. The ADSP input should be connected to the ADS output of the processor. ADSP is ignored when CS is HIGH. Bidirectional Signals Address strobe from cache controller. This signal is sampled at the rising edge of CLK. When this input and/or ADSP is asserted, A0­A 15 will be captured in the on-chip address register. It also allows the lower two address bits to be loaded into the on-chip auto-address-increment logic. The ADSC input should not be connected to the ADS output of the processor. DQ15 ­DQ0 I/O DP1­DP0 Write signal for the high-order half of the RAM array. This signal is sampled by the rising edge of CLK. If WH is sampled as LOW, i.e., asserted, the control logic will perform a self-timed write of DQ15 ­ DQ8 and DP1 from the on-chip data register into the selected RAM location. There is one exception to this. If ADSP, WH, and CS are asserted (LOW) at the rising edge of CLK, the write signal, WH, is ignored. Note that ADSP has no effect on WH if CS is HIGH. Write signal for the low-order half of the RAM array. This signal is sampled by the rising edge of CLK. If WL is sampled as LOW, i.e., asserted, the control logic will perform a self-timed write of DQ7 ­ DQ0 and DP0 from the on-chip data register into the selected RAM location. There is one exception to this. If ADSP, WL, and CS are asserted (LOW) at the rising edge of CLK, the write signal, WL, is ignored. Note that ADSP has no effect on WL if CS is HIGH. 4 Sixteen bidirectional data I/O lines. DQ15 ­ DQ8 are inputs to and outputs from the high-order half of the RAM array, while DQ7 ­ DQ0 are inputs to and outputs from the low-order half of the RAM array. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they carry the data read from the selected location in the RAM array. The direction of the data pins is controlled by OE: when OE is high, the data pins are three-stated and can be used as inputs; when OE is low, the data pins are driven by the output buffers and are outputs. DQ15 ­ DQ8 and DQ7 ­ DQ0 are also three-stated when WH and WL, respectively, is sampled LOW at clock rise. Two bidirectional data I/O lines. These operate in exactly the same manner as DQ15 ­ DQ0, but are named differently because their primary purpose is to store parity bits, while the DQs' primary purpose is to store ordinary data bits. DP1 is an input to and an output from the high-order half of the RAM array, while DP0 is an input to and an output from the lower-order half of the RAM array. I/O CY7C1031 CY7C1031 CY7C1032 CY7C1032 PRELIMINARY Maximum Ratings Static Discharge Voltage . >2001V (per MIL-STD-883 MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current . >200 mA Storage Temperature .­65°C to +150°C Operating Range Ambient Temperature with Power Applied.­55°C to +125°C Supply Voltage on VCC Relative to GND. ­0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[2] .­0.5V to VCC + 0.5V DC Input Ambient Temperature[3] VCC VCCQ 0°C to +70°C 5V ± 5% 3.0V to VCC ­55°C to +125°C 5V ± 5% 5V ± 5% Range Com'l Mil Voltage[2] .­0.5V to VCC + 0.5V Current into Outputs (LOW) . 20 mA Electrical Characteristics Over the Operating Range[4] 7C1031 7C1031­7 7C1032 7C1032­7 Parameter Description Test Conditions 7C1031 7C1031­8 7C1032 7C1032­8 7C1031 7C1031­10 7C1032 7C1032­10 7C1031 7C1031­12 7C1032 7C1032­12 Min. Max. Min. Max. Min. Max. Min. Max. Unit 2.4 VCCQ 2.4 VCCQ 2.4 VCCQ 2.4 VCCQ V 0.4 V VOH Output HIGH Voltage VCC = Min., IOH=­4.0 mA VOL Output LOW Voltage VIH Input HIGH Voltage 2.2 VCC + 0.3V 2.2 VCC + 0.3V 2.2 VCC + 0.3V 2.2 VCC + 0.3V V VIL Input LOW Voltage[2] ­0.3 0.8 ­0.3 0.8 ­0.3 0.8 ­0.3 0.8 V IX Input Load Current GND VI VCC ­1 1 ­1 1 ­1 1 ­1 1 µA IOZ Output Leakage Current GND VI VCC, Output Disabled ­5 5 ­5 5 ­5 5 ­5 5 µA IOS Output Short Circuit Current[5] VCC=Max., VOUT=GND ­300 ­300 ­300 ­300 mA ICC VCC Operating Supply Current VCC=Max., Com'l Iout=0mA, Mil f=fMAX =1/tCYC 300 280 280 230 mA Automatic CE Power-Down Current-TTL Inputs Max. VCC, CS Com'l VIH, VIN VIH Mil or VIN VIL, f=fMAX 90 Automatic CE Max. VCC, CS Com'l Power-Down Current VCC ­ 0.3V, Mil - CMOS Inputs VIN VCC ­0.3V or VIN 0.3V, f=0[6] 30 ISB1 ISB2 VCC = Min, IOL=8.0 mA 0.4 0.4 0.4 250 80 30 60 mA 70 30 80 mA 30 mA 50 Shaded area contains advanced information. Notes: 2. Minimum voltage equals ­2.0V for pulse durations of less than 20 ns. 3. TA is the "instant on" case temperature. 4. See the last page for Group A subgroup testing information. 5. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 6. Inputs are disabled, clock is allowed to run at speed. 5 CY7C1031 CY7C1031 CY7C1032 CY7C1032 PRELIMINARY Capacitance[7] Parameter CIN: Addresses Description Input Capacitance Test Conditions TA = 25°C, f = 1 MHz, Com'l VCC = 5.0V Mil Com'l Mil Com'l Mil CIN: Other Inputs COUT Output Capacitance Max. 4.5 6 5 8 8 10 Unit pF pF pF pF pF pF Shaded areas contain advanced information AC Test Loads and Waveforms R1 VCCQ OUTPUT Z0 = 50 ALL INPUT PULSES OUTPUT 3.0V RL = 50 5 pF VL =1.5V (a) INCLUDING JIGAND SCOPE 10% R2 GND 3 ns (b) [8] 90% 90% 10% 3 ns 1031­3 1031­4 Notes: 7. Tested initially and after any design or process changes that may affect these parameters. 8. Resistor values for VCCQ=5V are: R1=1179 and R2=868. Resistor values for VCCQ=3.3V are R1=317 and R2=348. 6 CY7C1031 CY7C1031 CY7C1032 CY7C1032 PRELIMINARY Switching Characteristics Over the Operating Range[9] 7C1031 7C1031­7 7C1032 7C1032­7 Parameter Description Min. Max. 7C1031 7C1031­8 7C1032 7C1032­8 Min. Max. 7C1031 7C1031­10 7C1032 7C1032­10 7C1031 7C1031­12 7C1032 7C1032­12 Min. Min. tCYC Clock Cycle Time tCH Clock HIGH tCL Clock LOW 5 5 tAS Address Set-Up Before CLK Rise 2.5 2.5 tAH Address Hold After CLK Rise 0.5 0.5 0.5 tCDV Data Output Valid After CLK Rise Max. Max. Unit 13.3 15 15 20 ns 5 5 6 8 ns 6 8 ns 2.5 2.5 ns 0.5 ns 7 8.5 10 12 ns tDOH Data Output Hold After CLK Rise 2 3 3 3 ns tADS ADSP, ADSC Set-Up Before CLK Rise 2.5 2.5 2.5 2.5 ns tADSH ADSP, ADSC Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tWES WH, WL Set-Up Before CLK Rise 2.5 2.5 2.5 2.5 ns tWEH WH, WL Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tADVS ADV Set-Up Before CLK Rise 2.5 2.5 2.5 2.5 ns tADVH ADV Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tDS Data Input Set-Up Before CLK Rise 2.5 2.5 2.5 2.5 ns tDH Data Input Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tCSS Chip Select Set-Up 2.5 2.5 2.5 2.5 ns tCSH Chip Select Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tCSOZ Chip Select Sampled to Output High tEOZ OE HIGH to Output High tEOV Z[10] 2 OE LOW to Output Valid tWEOZ tWEOV 2 6 2 6 2 7 ns 6 2 6 2 6 2 5 6 ns 5 6 7 ns 7 Valid[11] ns 5 5 Z[10, 11] 7 5 WH or WL Sampled LOW to Output High WH or WL Sampled HIGH to Output 6 2 Z[10] 8.5 10 12 ns Shaded areas contain advanced information Notes: 9. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) os AC test loads. 10. tCSOZ, tEOZ, and tWEOZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage. 11. At any given voltage and temperature, tWEOZ min. is less than tWEOV min. 7 CY7C1031 CY7C1031 CY7C1032 CY7C1032 PRELIMINARY Switching Waveforms Single Read[12] tCH tCL tCYC CLK tCSS tCSH CS tAS tAH ADDRESS tADS [13] tADSH or ADSP ADSC tWES tWEH [14] WH, WL tCDV tDOH DATA OUT 1031­6 Single Write Timing: Write Initiated by ADSP tCH tCL CLK tCSS tCSH CS tAS tAH tADS tADSH ADDRESS ADSP tWES tWEH [14] WH, WL tDS tDH DATA IN DATA OUT tEOZ OE 1031­5 Notes: 12. OE is LOW throughout this operation. 13. If ADSP is asserted while CS is HIGH, ADSP will be ignored. 14. ADSP has no effect on ADV, WL, and WH if CS is HIGH. 8 CY7C1031 CY7C1031 CY7C1032 CY7C1032 PRELIMINARY Switching Waveforms (continued) Single Write Timing: Write Initiated by ADSC tCH tCL CLK tCSS tCSH tAS tAH tADS tADSH CS ADDRESS ADSC tWES tWEH WH, WL tDS tDH DATA IN DATA OUT tEOZ OE 1031­7 Burst Read Sequence with Four Accesses CLK tCSS tCSH CS tAS tAH tADS tADSH ADDRESS ADSP [13] or ADSC tADVS ADV tADVH [14] WH,WL [14] tWES tWEH OE tCDV DATA OUT OE tDOH DATA0 DATA1 DATA2 DATA3 1031­8 9 CY7C1031 CY7C1031 CY7C1032 CY7C1032 PRELIMINARY Switching Waveforms (continued) Output (Controlled by OE) DATA OUT tEOV tEOZ OE 1031­9 Write Burst Timing: Write Initiated by ADSC CLK tCSS tCSH tWES tWEH tADS tADSH tADS tADSH tAS tAH CS WH, WL OE ADSP [13] ADSC ADDR tADVS tADVH ADV tDS DATA DATA0 tDH DATA1 DATA2 DATA3 1031­10 10 CY7C1031 CY7C1031 CY7C1032 CY7C1032 PRELIMINARY Switching Waveforms (continued) Write Burst Timing: Write Initiated by ADSP CLK tCSS tCSH tADS tADSH tAS tAH CS WH, WL [14] OE ADSC ADSP [13] ADDR tADVS tADVH ADV [14] tDS DATA tDH DATA0 DATA1 DATA2 DATA3 1031­11 11 CY7C1031 CY7C1031 CY7C1032 CY7C1032 PRELIMINARY Switching Waveforms (continued) Output Timing (Controlled by CS) CLK tADS tCSH tADSH tCSS ADSC tADSH tCSS tADS tCSH CS tCSOZ tCDV DATA OUT 1031­12 Output Timing (Controlled by WH/ WL) CLK tADS tADSH tWES tWEH tADS tADSH ADSC and ADSP WH, WL tWEOZ tWEOV DATA OUT 1031­13 Truth Table Input ADSC ADV L X H H CS H H ADSP X L WH or WL X H CLK LH LH H L H L H LH H L H H L LH H L H L L LH L L L X L H H H X L L H X X X L X H L L LH LH LH LH X H H L H LH X H H H L LH X H H H H LH 12 Address N/A Same address as previous cycle Incremented burst address Same address as previous cycle Incremented burst address External External External Incremented burst address Incremented burst address Same address as previous cycle Same address as previous cycle Operation Chip deselected Read cycle (ADSP ignored) Read cycle, in burst sequence (ADSP ignored) Write cycle (ADSP ignored) Write cycle, in burst sequence (ADSP ignored) Read cycle, begin burst Read cycle, begin burst Write cycle, begin burst Write cycle, in burst sequence Read cycle, in burst sequence Write cycle Read cycle CY7C1031 CY7C1031 CY7C1032 CY7C1032 PRELIMINARY Ordering Information Speed (ns) 7 Ordering Code Package Name Package Type CY7C1031 CY7C1031­7JC J69 CY7C1031 CY7C1031­7NC TBD 52-Lead Plastic Quad Flatpack CY7C1031 CY7C1031­8JC J69 52-Lead Plastic Leaded Chip Carrier CY7C1031 CY7C1031­8NC TBD 52-Lead Plastic Quad Flatpack 10 CY7C1031 CY7C1031­10JC J69 52-Lead Plastic Leaded Chip Carrier CY7C1031 CY7C1031­10NC TBD 52-Lead Plastic Quad Flatpack 12 CY7C1031 CY7C1031­12JC J69 52-Lead Plastic Leaded Chip Carrier CY7C1031 CY7C1031­12NC TBD 52-Lead Plastic Quad Flatpack CY7C1031 CY7C1031­12YMB 12YMB Y59 52-Pin Ceramic Leaded Chip Carrier 8 Speed (ns) 7 Ordering Code Package Name 52-Lead Plastic Leaded Chip Carrier Operating Range Package Type J69 52-Lead Plastic Leaded Chip Carrier CY7C1032 CY7C1032­7NC 8 CY7C1032 CY7C1032­7JC TBD CY7C1032 CY7C1032­8JC J69 52-Lead Plastic Leaded Chip Carrier TBD Commercial Commercial Military Operating Range CY7C1032 CY7C1032­10JC J69 52-Lead Plastic Leaded Chip Carrier TBD 52-Lead Plastic Quad Flatpack CY7C1032 CY7C1032­12JC J69 52-Lead Plastic Leaded Chip Carrier CY7C1032 CY7C1032­12NC TBD 52-Lead Plastic Quad Flatpack CY7C1032 CY7C1032­12YMB 12YMB Y59 52-Pin Ceramic Leaded Chip Carrier Commercial 52-Lead Plastic Quad Flatpack CY7C1032 CY7C1032­10NC 12 Commercial 52-Lead Plastic Quad Flatpack CY7C1032 CY7C1032­8NC 10 Commercial Shaded areas contain advanced information. Document #: 38­00219­B 13 Commercial Commercial Commercial Military PRELIMINARY CY7C1031 CY7C1031 CY7C1032 CY7C1032 Package Diagrams 52-Lead Plastic Leaded Chip Carrier J69 52-P in Ceramic Leaded Chip Carrier Y59 © Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.