CY7C09079V/89V/99V CY7C09179V/89V/99V 1CY7C025/0251 32K/64K/128K - Datasheet Archive

 

CY7C09179V/89V/99V 1CY7C025/0251 CY7C09079V/89V/99V CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM

 

CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V 1CY7C025/0251 1CY7C025/0251 CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V 3.3V 32K/64K/128K 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM Features · True Dual-Ported memory cells which allow simultaneous access of the same memory location · 6 Flow-Through/Pipelined devices - 32K x 8/9 organizations (CY7C09079V/179V CY7C09079V/179V) - 64K x 8/9 organizations (CY7C09089V/189V CY7C09089V/189V) - 128K x 8/9 organizations (CY7C09099V/199V CY7C09099V/199V) · 3 Modes - Flow-Through - Pipelined - Burst · Pipelined output mode on both ports allows fast 100-MHz operation · 0.35-micron CMOS for optimum speed/power · High-speed clock to data access 6.5[1]/7.5[1]/9/12 ns (max.) · 3.3V low operating power - Active= 115 mA (typical) - Standby= 10 µA (typical) · Fully synchronous interface for easier operation · Burst counters increment addresses internally - Shorten cycle times - Minimize bus noise · · · · - Supported in Flow-Through and Pipelined modes Dual Chip Enables for easy depth expansion Automatic power-down Commercial and Industrial temperature ranges Available in 100-pin TQFP v Logic Block Diagram R/WL R/WR OEL OER CE0L CE1L 1 0 0/1 0/1 FT/PipeL [2] CE0R CE1R 1 0 1 0/1 0 0 1 0/1 8/9 FT/PipeR [2] 8/9 I/O0L­I/O7/8L I/O0R­I/O7/8R I/O Control [3] A0­A14/15/16L A14/15/16L CLKL ADSL CNTENL CNTRSTL I/O Control 15/16/17 15/16/17 Counter/ Address Register Decode Counter/ Address Register Decode True Dual-Ported RAM Array [3] A0­A14/15/16R A14/15/16R CLKR ADSR CNTENR CNTRSTR Notes: 1. See page 6 for Load Conditions. 2. I/O0­I/O7 for x8 devices, I/O0­I/O8 for x9 devices. 3. A0­A14 for 32K, A0­A15 for 64K, and A0­A16 for 128K devices. For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation · 3901 North First Street · San Jose · CA 95134 · 408-943-2600 February 2, 2001 CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V Functional Description A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables allows easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE0 LOW and CE1 HIGH to reactivate the outputs. The CY7C09079V/89V/99V CY7C09079V/89V/99V and CY7C09179V/89V/99V CY7C09179V/89V/99V are high-speed synchronous CMOS 32K, 64K, and 128K x 8/9 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.[4] Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 6.5 ns[1] (pipelined). Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode data will be available tCD1 = 18 ns after the address is clocked into the device. Pipelined output or flow-through mode is selected via the FT/Pipe pin. Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port's burst counter is loaded with the port's Address Strobe (ADS). When the port's Count Enable (CNTEN) is asserted, the address counter will increment on each LOW-to-HIGH transition of that port's clock signal. This will read/write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter Reset (CNTRST) is used to reset the burst counter. Each port contains a burst counter on the input address register. The internal write pulse width is independent of the LOW-to-HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times. All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. NC NC A6R A5R A4R A3R A2R A1R A0R CLKR ADSR GND ADSL CLKL CNTENL A0L A1L A2L A3L A4L A5L A6L NC NC 100-Pin TQFP (Top View) CNTENR Pin Configurations 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC 75 NC NC 2 74 NC A7L 3 73 A7R A8L 4 72 A8R A9L 5 71 A9R A10L 6 70 A10R A11L 7 69 A11R A12L 8 68 A12R A13L 9 67 A13R A14L 10 66 A14R [5] A15L 11 65 A15R [5] [6] A16L 12 64 A16R [6] VCC 13 63 GND NC 14 62 NC NC 15 61 NC NC 16 60 NC NC 17 59 NC CE0L 18 58 CE0R CE1L 19 57 CE1R CNTRSTL 20 56 CNTRSTR R/WL 21 55 R/WR OEL 22 54 OER FT/PIPEL 23 53 FT/PIPER [7] NC 24 52 GND NC [7] 1 25 51 NC CY7C09099V CY7C09099V (128K x 8) CY7C09089V CY7C09089V (64K x 8) CY7C09079V CY7C09079V (32K x 8) Notes: 4. When writing simultaneously to the same location, the final value cannot be guaranteed. 5. This pin is NC for CY7C09079V CY7C09079V. 6. This pin is NC for CY7C09079V CY7C09079V and CY7C09089V CY7C09089V. 2 NC NC NC I/O7R I/O6R I/O5R I/O4R I/O3R VCC I/O2R I/01R I/01R I/O0R GND VCC I/O0L I/O1L GND I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L NC GND 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V 7. For CY7C09079V CY7C09079V and CY7C09089V CY7C09089V, pin #23 connected to VCC is pin compatible with an IDT 5V x8 pipelined device; connecting pin #23 and #53 to GND is pin compatible with an IDT 5V x16 flow-through device. Pin Configurations (continued) NC A6R A5R A4R A3R A2R A1R A0R CNTENR CLKR ADSR GND GND ADSL CLKL CNTENL A0L A1L A2L A3L A4L A5L A6L NC NC 100-Pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC NC 2 74 NC A7L 3 73 A7R A8L 4 72 A8R A9L 5 71 A9R A10L 6 70 A10R A11L 7 69 A11R A12L 8 68 A12R A13L 9 67 A13R A14L 10 66 A14R A15L 11 65 A15R [8] A16L 12 64 A16R [9] VCC 13 63 GND NC 14 NC 15 NC NC [9] 75 NC [8] 1 CY7C09199V CY7C09199V (128K x 9) CY7C09189V CY7C09189V (64K x 9) CY7C09179V CY7C09179V (32K x 9) 62 NC 61 NC 16 60 NC 17 59 NC CE0L 18 58 CE0R CE1L 19 57 CE1R CNTRSTL 20 56 CNTRSTR R/WL 21 55 R/WR OEL 22 54 OER FT/PIPEL 23 53 FT/PIPER NC 24 52 GND NC 25 51 NC NC NC I/O8R I/O7R I/O6R I/O5R I/O4R I/O3R VCC I/O2R I/01R I/01R I/O0R GND VCC I/O0L I/O1L GND I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L GND I/O8L 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Selection Guide CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V -6[1] -7[1] -9 -12 fMAX2 (MHz) (Pipelined) 100 83 67 50 Max. Access Time (ns) (Clock to Data, Pipelined) 6.5 7.5 9 12 Typical Operating Current ICC (mA) 175 155 135 115 Typical Standby Current for ISB1 (mA) (Both Ports TTL Level) 25 25 20 20 Typical Standby Current for ISB3 (µA) (Both Ports CMOS Level) 10 µA 10 µA 10 µA 10 µA Notes: 8. This pin is NC for CY7C09179V CY7C09179V. 9. This pin is NC for CY7C09179V CY7C09179V and CY7C09189V CY7C09189V. 3 CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V Pin Definitions Left Port Right Port Description A0L­A16L A0R­A16R Address Inputs (A0­A14 for 32K; A0­A15 for 64K; and A0­A16 for 128K devices). ADSL ADSR Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to access the part using an externally supplied address. Asserting this signal LOW also loads the burst counter with the address present on the address pins. CE0L,CE1L CE0R,CE1R Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 VIL and CE1 VIH). CLKL CLKR Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX. CNTENL CNTENR Counter Enable Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW. CNTRSTL CNTRSTR Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN. I/O0L­I/O8L I/O0R­I/O8R Data Bus Input/Output (I/O0­I/O7 for x8 devices; I/O0­I/O8 for x9 devices). OEL OER Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read operations. R/WL R/WR Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. FT/PIPEL FT/PIPER Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For pipelined mode operation, assert this pin HIGH. GND Ground Input. NC No Connect. VCC Power Input. Maximum Ratings Output Current into Outputs (LOW)20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage>2001V Latch-Up Current>200 mA Storage Temperature ­65°C to +150°C Ambient Temperature with Power Applied­55°C to +125°C Operating Range Supply Voltage to Ground Potential­0.5V to +4.6V Ambient Temperature VCC Commercial 0°C to +70°C 3.3V ± 300 mV Industrial[10] ­40°C to +85°C 3.3V ± 300 mV Range DC Voltage Applied to Outputs in High Z State­0.5V to VCC+0.5V DC Input Voltage­0.5V to VCC+0.5V Note: 10. Industrial parts are available in CY7C09099V CY7C09099V and CY7C09199V CY7C09199V only. 4 CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V Electrical Characteristics Over the Operating Range CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V 2.4 Output HIGH Voltage (VCC = Min. IOH = ­4.0 mA) VOL Output LOW Voltage (VCC = Min. IOH = +4.0 mA) VIH Input HIGH Voltage VIL Input LOW Voltage IOZ Output Leakage Current ICC Operating Current Com'l. (VCC = Max. IOUT = 0 mA) Ind.[10] Outputs Disabled 175 Standby Current (Both Ports TTL Level)[11] CEL & CER VIH, f = fMAX 25 ISB2 ISB3 ISB4 2.0 320 2.0 10 ­10 10 Standby Current (Both Com'l. Ports CMOS Level)[11] Ind.[10] CEL & CER VCC ­ 0.2V, f=0 10 Standby Current (One Com'l. Port CMOS Level)[11] Ind.[10] CEL | CER VIH, f = fMAX 105 250 135 135 225 390 185 25 85 20 65 120 35 165 95 150 210 105 250 10 250 250 10 125 85 115 170 95 115 µA 205 mA 250 95 10 ­10 V 160 10 Unit Max. V 75 105 V 0.8 295 125 175 275 10 115 155 165 Standby Current (One Com'l. Port TTL Level)[11] CEL | Ind.[10] CER VIH, f = fMAX Typ. 2.0 85 95 0.4 0.8 275 Ind.[10] V 0.4 0.8 ­10 Min. Max. Typ. Min. Max. Typ. Min. 2.0 10 2.4 0.4 0.8 ­10 -12 2.4 0.4 Com'l. -9 2.4 VOH ISB1 -7[1] Max. Description Typ. Parameter Min. -6[1] 125 mA 20 50 mA mA 85 140 mA mA 10 250 µA µA 75 100 mA mA Capacitance Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. Unit 10 pF 10 pF Note: 11. CEL and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 VIL and CE1 VIH). 5 CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V AC Test Loads 3.3V 3.3V R1 = 590 OUTPUT RTH = 250 OUTPUT R1 = 590 OUTPUT C = 30 pF C = 30 pF R2 = 435 C = 5 pF R2 = 435 VTH = 1.4V (a) Normal Load (Load 1) (c) Three-State Delay (Load 2) (Used for tCKLZ, tOLZ, & tOHZ including scope and jig) (b) Thévenin Equivalent (Load 1) AC Test Loads (Applicable to -6 and -7 only)[12] Z0 = 50 OUTPUT ALL INPUT PULSES R = 50 3.0V C GND 90% 10% 90% 10% 3 ns 3 ns VTH = 1.4V (a) Load 1 (-6 and -7 only) 0. 60 (ns) for all -7 access times 0. 50 0. 40 0. 30 0. 20 0. 1 0 0. 00 10 15 20 25 Capacitance (pF) (b) Load Derating Curve Note: 12. Test Conditions: C = 10 pF. 6 30 35 CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V Switching Characteristics Over the Operating Range CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V Unit Max. Min. Max. -12 Min. Max. Description -9 Min. Min. Parameter -7[1] Max. -6[1] fMAX1 fMax Flow-Through 53 45 40 33 MHz fMAX2 fMax Pipelined 100 83 67 50 MHz tCYC1 Clock Cycle Time - Flow-Through 19 22 25 30 ns tCYC2 Clock Cycle Time - Pipelined 10 12 15 20 ns tCH1 Clock HIGH Time - Flow-Through 6.5 7.5 12 12 ns tCL1 Clock LOW Time - Flow-Through 6.5 7.5 12 12 ns tCH2 Clock HIGH Time - Pipelined 4 5 6 8 ns tCL2 Clock LOW Time - Pipelined 4 5 6 8 ns tR Clock Rise Time 3 3 3 3 ns tF Clock Fall Time 3 3 3 3 ns tSA Address Set-Up Time tHA Address Hold Time tSC Chip Enable Set-Up Time tHC Chip Enable Hold Time tSW R/W Set-Up Time tHW R/W Hold Time tSD Input Data Set-Up Time tHD Input Data Hold Time tSAD ADS Set-Up Time tHAD ADS Hold Time tSCN CNTEN Set-Up Time tHCN CNTEN Hold Time tSRST CNTRST Set-Up Time tHRST CNTRST Hold Time 3.5 4 4 4 ns 0 0 1 1 ns 3.5 4 4 4 ns 0 0 1 1 ns 3.5 4 4 4 ns 0 0 1 1 ns 3.5 4 4 4 ns 0 0 1 1 ns 3.5 4 4 4 ns 0 0 1 1 ns 3.5 4.5 5 5 ns 0 0 1 1 ns 3.5 4 4 4 ns 0 0 1 1 ns tOE Output Enable to Data Valid tOLZ[13, 14] OE to Low Z 2 [13, 14] OE to High Z 1 tOHZ 8 tCD1 Clock to Data Valid - Pipelined tDC Data Output Hold After Clock HIGH 2 Clock HIGH to Output High Z 2 Clock HIGH to Output Low Z 7 Clock to Data Valid - Flow-Through tCD2 2 tCKHZ[13, 14] tCKLZ [13, 14] 9 2 1 15 7 1 18 6.5 2 7 2 1 2 ns 7 ns ns 12 2 9 2 ns 25 9 2 9 12 2 20 7.5 2 9 10 2 2 ns ns 9 2 ns ns Port to Port Delays tCWDD Write Port Clock HIGH to Read Data Delay 30 35 40 40 ns tCCS Clock to Clock Set-Up Time 9 10 15 15 ns Notes: 13. Test conditions used are Load 2. 14. This parameter is guaranteed by design, but it is not production tested. 7 CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) Read Cycle for Flow-Through Output (FT/PIPE = VIL)[15, 16, 17, 18] tCH1 tCYC1 tCL1 CLK CE0 tSC tHC tSW tSA tSC tHC tHW tHA CE1 R/W An ADDRESS An+1 An+2 An+3 tCKHZ tDC tCD1 DATAOUT Qn Qn+1 Qn+2 tDC tCKLZ tOHZ tOLZ OE tOE Read Cycle for Pipelined Operation (FT/PIPE = VIH)[15, 16, 17, 18] tCH2 tCYC2 tCL2 CLK CE0 tSC tHC tSW tSA tSC tHC tHW tHA CE1 R/W ADDRESS DATAOUT An An+1 1 Latency An+2 An+3 tDC tCD2 Qn Qn+1 tOHZ tCKLZ Qn+2 tOLZ OE tOE Notes: 15. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 16. ADS = VIL, CNTEN and CNTRST = VIH. 17. The output is disabled (high-impedance state) by CE0=VIH or CE1 = VIL following the next rising edge of the clock. 18. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. 8 CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) Bank Select Pipelined Read[19, 20] - tCH2 tCYC2 tCL2 CLKL tHA tSA ADDRESS(B1) A0 A1 A3 A2 A4 A5 tHC tSC CE0(B1) tCD2 tHC tSC tCD2 tHA tSA tDC A0 ADDRESS(B2) A1 tDC tCKLZ A3 A2 tCKHZ D3 D1 D0 DATAOUT(B1) tCD2 tCKHZ A4 A5 tHC tSC CE0(B2) tSC tCD2 tHC DATAOUT(B2) tCKHZ tCD2 D4 D2 tCKLZ tCKLZ Left Port Write to Flow-Through Right Port Read[21, 22, 23, 24] CLKL tSW tHW tSA tHA R/WL ADDRESSL NO MATCH MATCH tHD tSD DATAINL VALID tCCS CLKR R/WR ADDRESSR tCD1 tSW tSA tHW tHA NO MATCH MATCH tCWDD tCD1 DATAOUTR VALID tDC VALID tDC Notes: 19. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet. ADDRESS(B1) = ADDRESS(B2). 20. OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH. 21. The same waveforms apply for a right port write to flow-through left port read. 22. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 23. OE = VIL for the right port, which is being read from. OE = VIH for the left port, which is being written to. 24. It tCCS maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS>maximum specified, then data is not valid until tCCS + tCD1. tCWDD does not apply in this case. 9 CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) Pipelined Read-to-Write-to-Read (OE = VIL)[18, 25, 26, 27] tCH2 tCYC2 tCL2 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An ADDRESS An+1 tSA An+2 An+2 An+3 An+4 tSD tHD tHA DATAIN tCD2 tCKHZ Dn+2 tCD2 tCKLZ Qn DATAOUT READ Qn+3 NO OPERATION WRITE READ [18, 25, 26, 27] Pipelined Read-to-Write-to-Read (OE Controlled) tCH2 tCYC2 tCL2 CLK CE0 tSC tHC CE1 R/W tSW tHW tSW tHW An An+1 An+2 An+3 An+4 An+5 ADDRESS tSA tHA tSD tHD Dn+2 DATAIN Dn+3 tCD2 DATAOUT tCKLZ tCD2 Qn Qn+4 tOHZ OE READ WRITE READ Notes: 25. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 26. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 27. During "No Operation", data in memory at the selected address may be corrupted and should be re-written to ensure data integrity. 10 CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) Flow-Through Read-to-Write-to-Read (OE = VIL)[16, 18, 25, 26, 27] tCH1 tCYC1 tCL1 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An ADDRESS An+1 tSA DATAIN An+2 An+2 tSD tHA An+3 tHD Dn+2 tCD1 tCD1 DATAOUT An+4 tCD1 Qn Qn+1 tDC tCKHZ READ tCD1 Qn+3 tCKLZ NO OPERATION WRITE tDC READ Flow-Through Read-to-Write-to-Read (OE Controlled)[16, 19, 25, 26, 27] tCH1 tCYC1 tCL1 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An An+1 An+2 An+3 An+4 An+5 ADDRESS tSA DATAIN DATAOUT tSD tHA Dn+2 tDC tCD1 tHD Dn+3 tOE tCD1 Qn tCD1 Qn+4 tOHZ tCKLZ tDC OE READ WRITE 11 READ CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) Pipelined Read with Address Counter Advance[28] tCH2 tCYC2 tCL2 CLK tSA tHA ADDRESS An tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tSCN DATAOUT tHCN Qx-1 tCD2 Qx READ EXTERNAL ADDRESS Qn Qn+1 tDC READ WITH COUNTER Qn+2 COUNTER HOLD Qn+3 READ WITH COUNTER Flow-Through Read with Address Counter Advance[28] tCH1 tCYC1 tCL1 CLK tSA tHA An ADDRESS tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tSCN DATAOUT tHCN tCD1 Qx Qn tDC READ EXTERNAL ADDRESS Qn+3 Qn+2 Qn+1 READ WITH COUNTER COUNTER HOLD READ WITH COUNTER Note: 28. CE0 and OE = VIL; CE1, R/W and CNTRST = VIH. 12 CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) Write with Address Counter Advance (Flow-Through or Pipelined Outputs)[29, 30] tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL ADDRESS An tSAD An+2 An+3 An+4 tHAD tSCN An+1 tHCN ADS CNTEN Dn DATAIN tSD tHD WRITE EXTERNAL ADDRESS Dn+1 Dn+1 WRITE WITH COUNTER Dn+2 WRITE COUNTER HOLD Dn+3 WRITE WITH COUNTER Notes: 29. CE0 and R/W = VIL; CE1 and CNTRST = VIH. 30. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH. 13 Dn+4 CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) Counter Reset (Pipelined Outputs)[18, 25, 31, 32] tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL ADDRESS AX 0 tSW An An+1 tHW tSD 1 An+1 tHD R/W tSAD tHAD tSCN tHCN tSRST tHRST ADS CNTEN CNTRST DATAIN D0 DATAOUT Q0 COUNTER RESET WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 Notes: 31. CE0 = VIL; CE1 = VIH. 32. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. 14 Q1 READ ADDRESS n Qn CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V Read/Write and Enable Operation[33, 34, 35] Inputs OE CLK CE0 Outputs CE1 I/O0­I/O9 R/W Operation X H X X High-Z Deselected[36] X X L X High-Z Deselected[36] X L H L DIN Write L L H H DOUT Read[36] L H X High-Z Outputs Disabled H X Address Counter Control Operation[33, 37, 38, 39] Address Previous Address X CLK ADS CNTEN X X X An X L X An X An CNTRST I/O Mode L Dout(0) Reset Counter Reset to Address 0 X H Dout(n) Load Address Load into Counter H H H Dout(n) Hold External Address Blocked-Counter Disabled H L H Dout(n+1) Increment Counter Enabled-Internal Address Generation Notes: 33. "X" = "Don't Care", "H" = VIH, "L" = VIL. 34. ADS, CNTEN, CNTRST = "Don't Care." 35. OE is an asynchronous input signal. 36. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle. 37. CE0 and OE = VIL; CE1 and R/W = VIH. 38. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle. 39. Counter operation is independent of CE0 and CE1. 15 Operation CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V Ordering Information 32K x8 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type OperatingRange 6.5[1] CY7C09079V-6AC CY7C09079V-6AC A100 100-Pin Thin Quad Flat Pack Commercial 7.5[1] CY7C09079V-7AC CY7C09079V-7AC A100 100-Pin Thin Quad Flat Pack Commercial 7.5[1] CY7C09079V-7AI CY7C09079V-7AI A100 100-Pin Thin Quad Flat Pack Industrial 9 CY7C09079V-9AC CY7C09079V-9AC A100 100-Pin Thin Quad Flat Pack Commercial 12 CY7C09079V-12AC CY7C09079V-12AC A100 100-Pin Thin Quad Flat Pack Commercial 64K x8 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 6.5[1] CY7C09089V-6AC CY7C09089V-6AC A100 100-Pin Thin Quad Flat Pack 7.5[1] CY7C09089V-7AC CY7C09089V-7AC A100 100-Pin Thin Quad Flat Pack Commercial 9 CY7C09089V-9AC CY7C09089V-9AC A100 100-Pin Thin Quad Flat Pack Commercial 12 CY7C09089V-12AC CY7C09089V-12AC A100 100-Pin Thin Quad Flat Pack Commercial Commercial 128K x8 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 6.5[1] CY7C09099V-6AC CY7C09099V-6AC A100 100-Pin Thin Quad Flat Pack Commercial 7.5[1] CY7C09099V-7AC CY7C09099V-7AC A100 100-Pin Thin Quad Flat Pack Commercial 9 CY7C09099V-9AC CY7C09099V-9AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09099V-9AI CY7C09099V-9AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C09099V-12AC CY7C09099V-12AC A100 100-Pin Thin Quad Flat Pack Commercial 12 32K x9 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name 6.5[1] CY7C09179V-6AC CY7C09179V-6AC A100 7.5[1] Package Type 100-Pin Thin Quad Flat Pack Operating Range Commercial CY7C09179V-7AC CY7C09179V-7AC A100 100-Pin Thin Quad Flat Pack Commercial 9 CY7C09179V-9C CY7C09179V-9C A100 100-Pin Thin Quad Flat Pack Commercial 12 CY7C09179V-12AC CY7C09179V-12AC A100 100-Pin Thin Quad Flat Pack Commercial 64K x9 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 6.5[1] CY7C09189V-6AC CY7C09189V-6AC A100 100-Pin Thin Quad Flat Pack Commercial 7.5[1] CY7C09189V-7AC CY7C09189V-7AC A100 100-Pin Thin Quad Flat Pack Commercial 9 CY7C09189V-9AC CY7C09189V-9AC A100 100-Pin Thin Quad Flat Pack Commercial 12 CY7C09189V-12AC CY7C09189V-12AC A100 100-Pin Thin Quad Flat Pack Commercial 128K x9 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range [1] 6.5 CY7C09199V-6AC CY7C09199V-6AC A100 100-Pin Thin Quad Flat Pack Commercial 7.5[1] CY7C09199V-7AC CY7C09199V-7AC A100 100-Pin Thin Quad Flat Pack Commercial 9 CY7C09199V-9AC CY7C09199V-9AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09199V-9AI CY7C09199V-9AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C09199V-12AC CY7C09199V-12AC A100 100-Pin Thin Quad Flat Pack Commercial 12 Document #: 38-00667-*G 16 CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 51-85048-B 51-85048-B © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.