CY62256V 62256V25 62256V18 C62256V MIL-STD-883 CY62256V25 CY62256V18 - Datasheet Archive

 

PRELIMINARY CY62256V 32K x 8 Static RAM Features ers. These devices have an automatic power-down feature, reducing the power

 

fax id: 1069 PRELIMINARY CY62256V CY62256V 32K x 8 Static RAM Features ers. These devices have an automatic power-down feature, reducing the power consumption by over 99% when deselected. The CY62256V CY62256V family is available in the standard 450-mil-wide (300-mil body width) SOIC, TSOP, and reverse TSOP packages. · Low voltage range: - 2.7V - 3.6V (62256V) - 2.3V - 2.7V (62256V25 62256V25) · · · · · An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. - 1.6V - 2.0V (62256V18 62256V18) Low active power and standby power Easy memory expansion with CE and OE features TTL-compatible inputs and outputs Automatic power-down when deselected CMOS for optimum speed/power Functional Description The CY62256V CY62256V family is composed of three high-performance CMOS static RAM's organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and three-state driv- The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. Logic Block Diagram Pin Configurations SOIC Top View A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND I/O0 INPUTBUFFER I/O1 A10 A9 A8 A7 A6 A5 A4 A3 A2 I/O2 I/O3 512x512 ARRA Y I/O4 I/O5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 C62256V C62256V­2 CE WE COLUMN DECODER I/O6 POWER DOWN I/O7 OE C62256V C62256V­1 A11 A10 A9 A8 A7 A6 A5 VCC WE A4 A3 A2 A1 OE 7 6 8 9 5 4 3 2 10 11 12 13 14 15 16 17 18 1 28 27 26 25 24 23 22 TSOP I Reverse Pinout Top View (not to scale) 19 20 21 A12 A13 A14 I/O0 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 I/O7 CE A0 OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7 TSOP I Top View (not to scale) · 3901 North First Street A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A14 A13 A12 C62256V C62256V­3 C62256V C62256V­4 Cypress Semiconductor Corporation 20 19 18 17 16 15 14 13 12 11 10 9 8 · San Jose · CA 95134 · 408-943-2600 March 1996 ­ Revised April 1998 PRELIMINARY Maximum Ratings CY62256V CY62256V Output Current into Outputs (LOW). 20 mA Static Discharge Voltage . >2001V (per MIL-STD-883 MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature . -65°C to + 150°C Latch-Up Current. >200 mA Ambient Temperature with Power Applied . 0°C to + 70°C Operating Range Range Commercial Industrial Supply Voltage to Ground Potential (Pin 28 to Pin 14).-0.5V to + 4.6V DC Voltage Applied to Outputs in High Z State[1] . -0.5V to VCC + 0.5V Ambient Temperature 0°C to +70°C -40°C to +85°C VCC 1.6V to 3.6V 1.6V to 3.6V Note: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. DC Input Voltage . -0.5V to VCC + 0.5V [1] Product Portfolio Power Dissipation ( LL Devices) Product Vcc Range Speed Operating(Icc) Standby (ISB2) Min. Typ. Max. Typical Maximum Typical Maximum CY62256V CY62256V 2.7V 3.0 3.6V 70 ns 11 mA 30 mA 0.1 uA 5 uA CY62256V25 CY62256V25 2.3V 2.5V 2.7V 100 ns 9 mA 15 mA 0.1 uA 4 uA CY62256V18 CY62256V18 1.6V 1.8V 2.0V 200 ns 5 mA 10 mA 0.1 uA 3 uA Electrical Characteristics Over the Operating Range CY62256V-70 CY62256V-70 Parameter Description Test Conditions Min. VOH Output HIGH Voltage VCC = Min., IOH = -1.0 mA VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA VIH Input HIGH Voltage VIL Input LOW Voltage IIX Input Load Current GND < VI < VCC IOZ Output Leakage Current GND < VO < VCC, Output Disabled ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Com'l Std/L /LL ISB1 Automatic CE Power-Down Current- TTL Inputs Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Com'l ISB2 Automatic CE Power-Down Current- CMOS Inputs Max. VCC, CE > VCC - 0.3V VIN > VCC - 0.3V or VIN < 0.3V, f=0 Com'l Typ.[2] Max. 2.4 Unit V 0.4 VCC +0.3V V -0.5 0.8 V -1 +1 uA -1 +1 uA 11 30 mA Std/L /LL 100 300 uA Std/ L 0.1 50 uA LL Ind'l V 2.2 5 uA LL 10 uA Electrical Characteristics Over the Operating Range CY62256V25-100 CY62256V25-100 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = -0.1 mA VOL Output LOW Voltage VCC = Min., IOL = 0.1 mA VIH Input HIGH Voltage VIL Input LOW Voltage IIX Input Load Current Min. Typ.[2] Max. 2 Unit V V 0.7 V -1 2 V Vcc + 0.3V -0.3 GND < VI < VCC 0.4 1.7 +1 uA PRELIMINARY CY62256V CY62256V Electrical Characteristics Over the Operating Range (continued) CY62256V25-100 CY62256V25-100 Parameter Description Test Conditions Typ.[2] Min. Unit +1 -1 Max. uA IOZ Output Leakage Current GND < VO < VCC, Output Disabled ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Com'l Stnd/L /LL 14 23 mA ISB1 Automatic CE Power-Down Current- TTL Inputs Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Com'l Stnd/L /LL 75 225 uA ISB2 Automatic CE Power-Down Current - CMOS Inputs Max. VCC, CE > VCC - 0.3V VIN > VCC - 0.3V or VIN < 0.3V, f=0 Com'l Stnd/L 40 uA 4 uA 8 uA 0.1 LL Ind'l LL Electrical Characteristics Over the Operating Range CY62256V18-200 CY62256V18-200 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = -0.1 mA VOL Output LOW Voltage VCC = Min., IOL = 0.1 mA VIH Input HIGH Voltage VIL Input LOW Voltage IIX Input Load Current IOZ Typ.[2] Min. Max. 0.8*Vcc Unit V 0.2 V 0.7*Vcc VCC +0.3V V -0.5 0.2*Vcc V GND < VI < VCC -1 +1 uA Output Leakage Current GND < VO < VCC, Output Disabled -1 +1 uA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Com'l Stnd/L /LL 10 17 mA ISB1 Automatic CE Power-Down Current- TTL Inputs Max. VCC, CE > VIH, Com'l VIN > VIH or VIN < VIL, f = fMAX Stnd/L /LL 56 165 uA ISB2 Automatic CE Power-Down Current- CMOS Inputs Max. VCC, CE > VCC - 0.3V VIN > VCC - 0.3V or VIN < 0.3V, f=0 Stnd/L 30 uA 3 uA 6 uA Com'l 0.1 LL Ind'l LL Capacitance[3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.0V Max. Unit 6 pF 8 pF Notes: 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = Vcc Typ., TA = 25°C, and tAA=70ns. 3. Tested initially and after any design or process changes that may affect these parameters. 3 PRELIMINARY CY62256V CY62256V AC Test Loads and Waveforms R1 Vcc ALL INPUT PULSES OUTPUT Vcc R2 50 pF GND < 5 ns < 5 ns INCLUDING JIG AND SCOPE Equivalent to: 90% 10% 90% 10% C62256V C62256V­5 C62256V C62256V­6 THÉVENIN EQUIVALENT Rth OUTPUT V th AC Test Load Vcc 3.3 V 2.5V 1.8V R1 1103 16.6K 13.6K R2 1554 15.4K 11.4K RTH 645 8K 6.2K VTH 1.75V 1.2V 0.82V Data Retention Characteristics (Over the Operating Range) Parameter Conditions[4] Description VDR VCC for Data Retention ICCDR Data Retention Current Min. Coml Stnd/L Ind. LL VCC = 1.6 CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V Chip Deselect to Data Retention Time tR[3] Max. 1.4 LL tCDR[3] Typ.[2] Operation Recovery Time Unit V 30 uA 6 0.1 uA 3 uA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE VCC 1.8V VDR > 1.4V tCDR 1.8V tR CE C62256V C62256V­7 4 PRELIMINARY CY62256V CY62256V Switching Characteristics Over the Operating Range[5] CY62256V-70 CY62256V-70 Parameter Description Min. Max. CY62256V25-100 CY62256V25-100 CY62256V18-200 CY62256V18-200 Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z[6] tHZOE 70 OE HIGH to High Z tLZCE CE LOW to Low Z 10 10 CE LOW to Power-Up 10 ns 75 50 70 ns 10 0 CE HIGH to Power-Down ns 125 50 25 0 ns 10 10 ns 200 75 5 25 ns 200 100 35 5 [6, 7] CE HIGH to High Z 200 100 70 [6] tPU WRITE CYCLE 10 [6, 7] tHZCE tPD 100 70 ns 75 0 100 ns ns ns 200 ns [8,9] tWC Write Cycle Time 70 100 200 ns tSCE CE LOW to Write End 60 90 180 ns tAW Address Set-Up to Write End 60 90 180 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 ns tPWE WE Pulse Width 50 80 160 ns tSD Data Set-Up to Write End 30 60 100 ns tHD Data Hold from Write End 0 0 0 ns [6, 7] tHZWE WE LOW to High Z tLZWE WE HIGH to Low Z[6] 25 10 50 10 100 10 ns ns Notes: 4. No input may exceed VCC+0.3V. 5. Test conditions assume signal transition time of 5 ns or less timing reference levels of Vcc/2, input pulse levels of 0 to Vcc, and output loading of the specified IOL/IOH and 100-pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage. Switching Waveforms Read Cycle No. 1[10, 11] tRC ADDRESS [10, 11] tOHA DATA OUT tAA DATA VALID PREVIOUS DATA VALID C62256V C62256V­8 5 PRELIMINARY CY62256V CY62256V Switching Waveforms (continued) Read Cycle No. 2 [11, 12] t RC CE tACE OE t HZOE tHZCE tDOE DATA OUT t LZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT t PD t PU ICC 50% 50% ISB C62256V C62256V­9 Write Cycle No. 1 (WE Controlled) [8, 13, 14] tWC ADDRESS CE tAW tHA tSA WE t PWE OE tSD DATA I/O NOTE 15 tHD DATAINVALID t HZOE C62256V C62256V­10 Notes: 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 10. Device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW. 6 PRELIMINARY CY62256V CY62256V Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled) [8, 13, 14] tWC ADDRESS tSCE CE tSA tAW tHA WE tSD DATA I/O t HD DATAINVALID C62256V C62256V­11 [ 9, 14] Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS CE tAW t HA tSA WE tSD DATA I/O NOTE 15 t HD DATA INVALID tLZWE t HZWE C62256V C62256V­12 Notes: 13. Data I/O is high impedance if OE = VIH. 14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 15. During this period, the I/Os are in output state and input signals should not be applied. 7 PRELIMINARY CY62256V CY62256V Typical DC and AC Characteristics 1.8 STANDBY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 3.0 1.4 Vcc=3.0V 1.6 1.4 1.2 2.5 1.2 1.0 2.0 1.0 0.8 1.5 Vcc=2.5V 0.8 1.0 0.6 Vcc=1.8V TA =25°C 0.6 0.4 0.5 0.2 0.0 0.4 0.2 0.0 -55 25 125 -0.5 -55 SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 2.5 2.0 105 OUTPUT SINK CURRENT 14 vs. OUTPUT VOLTAGE 1.6 1.4 25 AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE ISB 12 Vcc=3.0V 10 Vcc=2.5V TA =25°C 1.0 6 1.0 Vcc=2.5 V Vcc=1.8V 4 0.8 0.5 0.0 1.65 8 1.2 1.5 2.1 2.6 3.1 3.6 TA =25°C 2 0.6 -55 25 125 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE -14 -12 -10 -8 Vcc=2.5V -6 TA =25°C -4 0 0.0 0.5 1.0 1.5 2 OUTPUT VOLTAGE (V) 8 1.0 2.0 OUTPUT VOLTAGE (V) AMBIENT TEMPERATURE (°C) SUPPLY VOLTAGE (V) 0 0.0 2.5 3.0 PRELIMINARY CY62256V CY62256V Typical DC and AC Characteristics (continued) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 1.5 TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING TA =25°C Vcc =3V 20.0 1.00 15.0 0.5 Vcc=3.0V Vcc=1.8V 25.0 1.0 NORMALIZED I CC vs.CYCLE TIME 1.25 30.0 0.75 10.0 TA =25°C VIN =0.5V 5.0 0.0 0.0 1.0 2.0 3.0 SUPPLY VOLTAGE (V) 4.0 0.0 0 200 400 600 800 1000 CAPACITANCE (pF) 9 0.50 1 10 20 30 CYCLE FREQUENCY (MHz) PRELIMINARY CY62256V CY62256V Truth Table CE WE OE H X X High Z Inputs/Outputs Deselect/Power-Down Mode Standby (ISB) Power L H L Data Out Read Active (ICC) L L X Data In Write Active (ICC) L H H High Z Deselect, Output Disabled Active (ICC) Ordering Information Speed (ns) 70 Ordering Code CY62256V CY62256V -70SNC -70SNC Package Name S22 Package Type 28-Lead 450-Mil (300-Mil Body Width) SOIC Operating Range Commercial CY62256V CY62256V L-70SNC L-70SNC CY62256V CY62256V LL-70SNC LL-70SNC CY62256V CY62256V -70ZRC -70ZRC ZR28 28-Lead Reverse Thin Small Outline Package CY62256V CY62256V L-70ZRC L-70ZRC CY62256V CY62256V LL-70ZRC LL-70ZRC CY62256V CY62256V -70ZC -70ZC Z28 28-Lead Thin Small Outline Package Z28 28-Lead Thin Small Outline Package S22 28-Lead 450-Mil (300-Mil Body Width) SOIC CY62256V CY62256V L-70ZC L-70ZC CY62256V CY62256V LL-70ZC LL-70ZC CY62256V CY62256V -70ZI -70ZI Industrial CY62256V CY62256V L-70ZI L-70ZI CY62256V CY62256V LL-70ZI LL-70ZI CY62256V CY62256V -70SNI -70SNI CY62256VL CY62256VL -70SNI -70SNI CY62256VLL CY62256VLL -70SNI -70SNI CY62256V CY62256V -70ZRI -70ZRI ZR28 28-Lead Reverse Thin Small Outline Package CY62256V CY62256V L-70ZRI L-70ZRI CY62256V CY62256V LL-70ZRI LL-70ZRI 100 CY62256V25-100SNC CY62256V25-100SNC S22 28-Lead 450-Mil (300-Mil Body Width) SOIC Commercial CY62256V25L-100SNC CY62256V25L-100SNC CY62256V25LL-100SNC CY62256V25LL-100SNC CY62256V25-100ZRC CY62256V25-100ZRC ZR28 28-Lead Reverse Thin Small Outline Package CY62256V25L-100ZRC CY62256V25L-100ZRC CY62256V25LL-100ZRC CY62256V25LL-100ZRC CY62256V25-100ZC CY62256V25-100ZC 100 Z28 28-Lead Thin Small Outline Package CY62256V25L-100ZC CY62256V25L-100ZC Z28 28-Lead Thin Small Outline Package Commercial S22 28-Lead 450-Mil (300-Mil Body Width) SOIC Commercial CY62256V25LL-100ZC CY62256V25LL-100ZC 200 CY62256V18-200SNC CY62256V18-200SNC CY62256V18L-200SNC CY62256V18L-200SNC CY62256V18LL-200SNC CY62256V18LL-200SNC CY62256V18-200ZRC CY62256V18-200ZRC ZR28 28-Lead Reverse Thin Small Outline Package CY62256V18L-200ZRC CY62256V18L-200ZRC CY62256V18LL-200ZRC CY62256V18LL-200ZRC CY62256V18-200ZC CY62256V18-200ZC Z28 28-Lead Thin Small Outline Package Z28 28-Lead Thin Small Outline Package CY62256V18LL-200ZC CY62256V18LL-200ZC 200 CY62256V18L-200ZC CY62256V18L-200ZC Shaded area contains advanced information. Document #: 38-00519-A 10 Commercial PRELIMINARY Package Diagrams 28-Lead 450-Mil (300-Mil Body Width) SOIC S22 28-Lead Reverse Thin Small Outline Package ZR28 11 CY62256V CY62256V PRELIMINARY CY62256V CY62256V Package Diagrams (continued) 28-Lead Thin Small Outline Package Z28 © Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.