CY62148B CY62148 62148B-2 62148B-1 CY62148BLL-70 MIL-STD-883 62148B-3 62148B-4 - Datasheet Archive
CY62148B 512K x 8 Static RAM Features an automatic power-down feature that reduces power consumption by more than 99% when
48B CY62148B CY62148B 512K x 8 Static RAM Features an automatic power-down feature that reduces power consumption by more than 99% when deselected. · 4.5V5.5V operation · CMOS for optimum speed/power · Low active power - 110 mW (max.) · Low standby power (L version) - 110 µW (max.) · Automatic power-down when deselected · TTL-compatible inputs and outputs · Easy memory expansion with CE and OE options Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH for read. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. Functional Description The CY62148 CY62148 is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. This device has The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY62148 CY62148 is available in a standard 32-pin 450-mil-wide body width SOIC and 32-pin TSOP II packages. Logic Block Diagram Pin Configuration Top View SOIC TSOP II A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND I/O0 INPUT BUFFER CE I/O1 I/O2 SENSE AMPS ROW DECODER A0 A1 A4 A5 A6 A7 A12 A14 A16 A17 512 x 256 x 8 ARRAY I/O3 I/O4 COLUMN DECODER VCC 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A15 A18 WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 62148B-2 62148B-2 I/O5 I/O6 POWER DOWN I/O7 A2 A3 A15 A18 A13 A8 A9 A11 A10 WE OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Cypress Semiconductor Corporation 62148B-1 62148B-1 · 3901 North First Street · San Jose · CA 95134 · 408-943-2600 January 9, 2001 CY62148B CY62148B Selection Guide CY62148BLL-70 CY62148BLL-70 Maximum Access Time (ns) 70 Maximum Operating Current (mA) LL 20 Commercial LL 20 µA Industrial Maximum CMOS Standby Current LL 20 µA Maximum Ratings Current into Outputs (LOW). 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage.2001V (per MIL-STD-883 MIL-STD-883, Method 3015) Storage Temperature . 65°C to +150°C Latch-Up Current . >200 mA Ambient Temperature with Power Applied . 55°C to +125°C Operating Range Supply Voltage on VCC to Relative GND. 0.5V to +7.0V Ambient Temperature DC Voltage Applied to Outputs in High Z State .0.5V to VCC +0.5V Commercial Industrial  DC Input Voltage .0.5V to VCC +0.5V VCC 0°C to +70°C Range 4.5V5.5V 40°C to +85°C Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. VOH Output HIGH Voltage VCC = Min., IOH = 1mA VOL Output LOW Voltage VCC = Min., IOL = 2.1mA VIH Input HIGH Voltage VIL Input LOW Voltage IIX Input Load Current GND VI V CC IOZ Output Leakage Current GND VI VCC, Output Disabled ICC VCC Operating Supply Current VCC = Max., IOUT + 0 mA, f = fMAX = 1/tRC ISB1 Automatic CE Power-Down Current - TTL Inputs Max. VCC, CE VIH VIN V IH or VIN V IL, f = fMAX ISB2 Automatic CE Power-Down Current - CMOS Inputs Max. VCC, CE VCC 0.3V, VIN V CC 0.3V, or VIN 0.3V, f=0 Typ. Max. 2.4 Unit V 0.4 V 2.2 VCC + 0.3 V 0.3 0.8 V 1 +1 µA 1 +1 µA 20 mA 1.5 mA LL Com'l LL 1.6 20 µA Ind'l LL 1.6 20 µA Notes: 1. VIL (min.) = 2.0V for pulse durations of less than 20 ns. 2. TA is the "instant on" case temperature. 3. Typical values are measured at VCC = 5V, TA = 25°C, and are included for reference only and are not tested or guaranteed. 2 CY62148B CY62148B Capacitance Parameter Description CIN Input Capacitance COUT Test Conditions Output Capacitance Max. 6 pF 8 TA = 25°C, f = 1 MHz, VCC = 5.0V Unit pF AC Test Loads and Waveforms R1 1838 R1 1838 ALL INPUT PULSES 5.0V 5V 5V 90% OUTPUT OUTPUT 5 pF R2 994 R2 994 5 pF INCLUDING INCLUDING JIG AND JIG AND SCOPE (b) 62148B-3 62148B-3 (a) SCOPE Equivalent to: THEVENIN EQUIVALENT 645 1.75V OUTPUT 62148B-4 62148B-4 3 GND 3 ns 10% 90% 10% 3 ns 62148B-5 62148B-5 CY62148B CY62148B Switching Characteristics Over the Operating Range 62148BLL 62148BLL70 Parameter Description Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z tHZOE 70 OE HIGH to High Z tLZCE CE LOW to Low Z 10 WRITE CYCLE ns ns 25 10 CE LOW to Power-Up tPD ns 35 [6, 7] CE HIGH to High Z ns 5  tPU ns 70 [6, 7] tHZCE ns 70 ns 25 0 CE HIGH to Power-Down ns ns ns 70 ns  tWC Write Cycle Time 70 ns tSCE CE LOW to Write End 60 ns tAW Address Set-Up to Write End 60 ns tHA Address Hold from Write End 0 ns tSA Address Set-Up to Write Start 0 ns tPWE WE Pulse Width 55 ns tSD Data Set-Up to Write End 30 ns tHD Data Hold from Write End 0 ns  tLZWE WE HIGH to Low Z tHZWE WE LOW to High Z[6, 7] 5 ns 25 ns Notes: 4. Tested initially and after any design or process changes that may affect these parameters. 5. Test conditions assume signal transition time of 5ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OL/IOH and 100-pF load capacitance. 6. t HZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. The internal write time of the memory is defined by the overlap of CE1 LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 4 CY62148B CY62148B Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current tCDR Chip Deselect to Data Retention Time tR Operation Recovery Time Min. Typ. Max. 2.0 Com'l LL Ind'l No input may exceed VCC + 0.3V VCC = VDR = 3.0V CE > VCC 0.3V VIN > VCC 0.3V or VIN < 0.3V LL Unit V 20 µA 20 µA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE 3.0V VCC 3.0V VDR > 2V tR tCDR CE 62148B-6 62148B-6 Switching Waveforms Read Cycle No.1 [9, 10] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID 62148B-7 62148B-7 Read Cycle No. 2 (OE Controlled)[10, 11] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tHZCE tLZOE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU 50% 50% ISB 62148B-8 62148B-8 Notes: 9. Device is continuously selected. OE, CE = VIL. 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE transition LOW. 5 CY62148B CY62148B Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled) tWC ADDRESS tSCE CE tSA tHA tAW tPWE WE tSD DATA I/O tHD DATA VALID 62148B-9 62148B-9 Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[12, 13] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 14 tHZOE 62148B-10 62148B-10 Notes: 12. Data I/O is high-impedance if OE = VIH. 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 14. During this period the I/Os are in the output state and input signals should not be applied. 6 CY62148B CY62148B Switching Waveforms (continued) Write Cycle No.3 (WE Controlled, OE LOW)[12, 13] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD NOTE 14 DATAI/O tHD DATA VALID tLZWE tHZWE 62148B-11 62148B-11 Truth Table CE OE WE I/O0 I/O7 Mode Power H X X High Z Power-Down Standby (ISB) L L H Data Out Read Standby (ICC) L X L Data In Write Active (ICC) L H H High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 70 Ordering Code Package Name CY62148BLL-70SC CY62148BLL-70SC S34 CY62148BLL-70ZC CY62148BLL-70ZC ZS32 CY62148BLL-70SI CY62148BLL-70SI S34 CY62148BLL-70ZI CY62148BLL-70ZI ZS32 Package Type 32-Lead (450-Mil) Molded SOIC Operating Range Commercial 32-Lead TSOP II 32-Lead (450-Mil) Molded SOIC 32-Lead TSOP II Document #: 38-01104-* 7 Industrial CY62148B CY62148B Package Diagrams 32-Lead (450 MIL) Molded SOIC S34 51-85081-A 8 CY62148B CY62148B Package Diagrams (continued) 32-Lead TSOP II ZS32 51-85095 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.