CY37384V CY37384 CY37256/37256V CY37512/37512V I/O0-I/O11 I/O12-I/O23

CY37384V UltraLogicTM 3.3V 384-Macrocell ISRTM CPLD Features - tPD = 15 ns - tS = 8 ns · 384 macrocells in 24 logic blocks

PRELIMINARY CY37384V CY37384V UltraLogicTM 3.3V 384-Macrocell ISRTM CPLD Features - tPD = 15 ns - tS = 8 ns · 384 macrocells in 24 logic blocks · 3.3V In-System ReprogrammableTM (ISRTM) - JTAG-compliant on-board programming · · · · · · · · · - Design changes don't cause pinout changes - Design changes don't cause timing changes · IEEE standard 3.3V operation - 3.3V ISR - 5V tolerant · Up to 192 I/Os - plus 5 dedicated inputs including 4 clock inputs · High speed - fMAX = 83 MHz - tCO = 8 ns Product-term clocking IEEE 1149.1 JTAG boundary scan Programmable slew rate control on individual I/Os Low power option on individual logic block basis User-Programmable Bus Hold capabilities on all I/Os Simple Timing Model PCI compliant[1] Available in 208-pin PQFP and 256-lead BGA packages Pinout compatible with the CY37384 CY37384, CY37256/37256V CY37256/37256V, CY37512/37512V CY37512/37512V Note: 1. Due to the 5V tolerant nature of the I/Os, the I/Os are not clamped to VCC. Clock/ Input Input Logic Block Diagram (256-pin BGA) 1 4 4 4 12 I/Os I/O0-I/O11 I/O0-I/O11 LOGIC BLOCK AA 12 I/Os LOGIC BLOCK AB I/O12-I/O23 I/O12-I/O23 12 I/Os I/O24-I/O35 I/O24-I/O35 LOGIC BLOCK AC LOGIC BLOCK AD 12 I/Os I/O36-I/O47 I/O36-I/O47 LOGIC BLOCK AE LOGIC BLOCK AF 12 I/Os I/O48-I/O59 I/O48-I/O59 LOGIC BLOCK AG 12 I/Os I/O60-I/O71 I/O60-I/O71 LOGIC BLOCK AH 12 I/Os LOGIC BLOCK AI I/O72-I/O83 I/O72-I/O83 LOGIC BLOCK AJ 12 I/Os I/O84-I/O95 I/O84-I/O95 LOGIC BLOCK AK LOGIC BLOCK AL TDI TCLK TMS JTAG Tap Controller 36 36 16 16 36 36 16 16 36 36 16 16 36 36 16 16 36 PIM 16 36 16 36 36 16 16 36 36 16 16 36 36 16 16 36 36 16 16 36 36 16 16 36 36 16 16 36 36 16 16 LOGIC BLOCK BL LOGIC BLOCK BK 12 I/Os I/O168-I/O191 I/O168-I/O191 LOGIC BLOCK BJ 12 I/Os I/O156-I/O179 I/O156-I/O179 LOGIC BLOCK BI 12 I/Os I/O144-I/O167 I/O144-I/O167 LOGIC BLOCK BH 12 I/Os I/O132-I/O155 I/O132-I/O155 LOGIC BLOCK BG LOGIC BLOCK BF LOGIC BLOCK BE 12 I/Os I/O120-I/O143 I/O120-I/O143 LOGIC BLOCK BD 12 I/Os I/O108-I/O131 I/O108-I/O131 LOGIC BLOCK BC 12 I/Os I/O96-I/O119 I/O96-I/O119 LOGIC BLOCK BB 12 I/Os I/O96-I/O107 I/O96-I/O107 LOGIC BLOCK BA TDO Cypress Semiconductor Corporation 37384V-1 96 · 3901 North First Street 96 · San Jose · CA95134 CA95134 · 408-943-2600 January 5, 1999 PRELIMINARY CY37384V CY37384V Selection Guide CY37384V-83 CY37384V-83 CY37384V-66 CY37384V-66 Maximum Propagation Delay, tPD (ns) 15 20 Minimum Set-Up, tS (ns) 8 10 Maximum Clock to Output, tCO (ns) 8 10 120 120 Typical Supply Current, ICC (mA) in Low Power Mode Output Slew Rate Control Functional Description Each output can be configured with either a fast edge rate (default) for high performance, or a slow edge rate for added noise reduction. In the fast edge rate mode, outputs switch at 3V/ns max. and in the slow edge rate mode, outputs switch at 1V/ns max. There is a nominal delay for I/Os using the slow edge rate mode. The CY37384V CY37384V is an In-System Reprogrammable (ISR) Complex Programmable Logic Device (CPLD) and is part of the Ultra37000TM family of high-density, high-speed CPLDs. Like all members of the Ultra37000 family, the CY37384V CY37384V is designed to bring the ease of use and high performance of the 22V10 22V10 to high-density PLDs. # of Pins # Buried Macrocells # I/O Macrocells 208 224 160 PQFP 256 192 192 In-System Reprogramming Package Types BGA The CY37384V CY37384V can be programmed in system using IEEE 1149.1 compliant JTAG programming protocol. The CY37384V CY37384V can also be programmed on a number of traditional parallel programmers including Cypress's Impulse3TM programmer and industry standard third-party programmers. For an overview of ISR programming, refer to the Ultra37000 Family data sheet and for UltraISR cable and software specifications, refer to InSRkit: ISR Programming data sheet (CY3600i). For a more detailed description of the architecture and features of the CY37384V CY37384V see the Ultra37000 family data sheet. Fully Routable with 100% Logic Utilization The CY37384V CY37384V is designed with a robust routing architecture which allows utilization of the entire device with a fixed pinout. This makes Ultra37000 optimal for implementing on-board design changes using ISR without changing pinouts. User-Programmable Bus Hold All outputs of the CY37384V CY37384V can either be configured into bus hold mode or left floating. When in bus hold mode, the undriven outputs retain their last value with a weak latch. This feature allows the designer the flexibility of either eliminating or including external pull-up/pull-down resistors. Enabling this feature affects all I/Os simultaneously. Simple Timing Model The CY37384V CY37384V features a very simple timing model with predictable delays. Unlike other high-density CPLD architectures, there are no hidden speed delays such as fanout effects, interconnect delays, or expander delays. The timing model allows for design changes with ISR without causing changes to system performance. Design Tools Development software for the CY37384V CY37384V is available from Cypress's Warp TM or third-party bolt-in software packages as well as a number of third-party development packages. Please refer to the Warp or third-party tool support data sheets for further information. Low Power Operation Each Logic Block of the CY37384V CY37384V can be configured as either High-Speed (default) or Low-Power. In the Low-Power mode, the logic block consumes approximately 50% less power and slows down by tLP. 2 PRELIMINARY CY37384V CY37384V Pin Configurations 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 GND I/O60 I/O60 I/O61 I/O61 I/O62 I/O62 I/O63 I/O63 I/O64 I/O64 TMS I/O65 I/O65 I/O66 I/O66 I/O67 I/O67 I/O68 I/O68 I/O69 I/O69 GND I/O70 I/O70 I/O71 I/O71 I/O72 I/O72 I/O73 I/O73 I/O74 I/O74 NC I/O75 I/O75 I/O76 I/O76 I/O77 I/O77 I/O78 I/O78 I/O79 I/O79 I2 VCC GND VCC I/O80 I/O80 I/O81 I/O81 I/O82 I/O82 I/O83 I/O83 I/O84 I/O84 I/O85 I/O85 I/O86 I/O86 I/O87 I/O87 I/O88 I/O88 I/O89 I/O89 GND I/O90 I/O90 I/O91 I/O91 I/O92 I/O92 I/O93 I/O93 I/O94 I/O94 GND TDO I/O95 I/O95 I/O96 I/O96 I/O97 I/O97 I/O98 I/O98 I/O99 I/O99 VCC GND I/O20 I/O20 I/O21 I/O21 I/O22 I/O22 I/O23 I/O23 I/O24 I/O24 TCLK I/O25 I/O25 I/O26 I/O26 I/O27 I/O27 I/O28 I/O28 I/O29 I/O29 GND I/O30 I/O30 I/O31 I/O31 I/O32 I/O32 I/O33 I/O33 I/O34 I/O34 NC I/O35 I/O35 I/O36 I/O36 I/O37 I/O37 I/O38 I/O38 I/O39 I/O39 CLK0/I0 VCC GND NC CLK1/I1 I/O40 I/O40 I/O41 I/O41 I/O42 I/O42 I/O43 I/O43 I/O44 I/O44 I/O45 I/O45 I/O46 I/O46 I/O47 I/O47 I/O48 I/O48 I/O49 I/O49 GND I/O50 I/O50 I/O51 I/O51 I/O52 I/O52 I/O53 I/O53 I/O54 I/O54 NC I/O55 I/O55 I/O56 I/O56 I/O57 I/O57 I/O58 I/O58 I/O59 I/O59 VCC 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 VCC VCC I/O19 I/O19 I/O18 I/O18 I/O17 I/O17 I/O16 I/O16 I/O15 I/O15 NC I/O14 I/O14 I/O13 I/O13 I/O12 I/O12 I/O11 I/O11 I/O10 I/O10 GND I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC GND VCC NC I/O159 I/O159 I/O158 I/O158 I/O157 I/O157 I/O156 I/O156 I/O155 I/O155 NC I/O154 I/O154 I/O153 I/O153 I/O152 I/O152 I/O151 I/O151 I/O150 I/O150 GND I/O149 I/O149 I/O148 I/O148 I/O147 I/O147 I/O146 I/O146 I/O145 I/O145 I/O144 I/O144 I/O143 I/O143 I/O142 I/O142 I/O141 I/O141 I/O140 I/O140 NC GND 208-pin PQFP Top View 3 VCC I/O139 I/O139 I/O138 I/O138 I/O137 I/O137 I/O136 I/O136 I/O135 I/O135 TDI I/O134 I/O134 I/O133 I/O133 I/O132 I/O132 I/O131 I/O131 I/O130 I/O130 GND I/O129 I/O129 I/O128 I/O128 I/O127 I/O127 I/O126 I/O126 I/O125 I/O125 I/O124 I/O124 I/O123 I/O123 I/O122 I/O122 I/O121 I/O121 I/O120 I/O120 CLK3/I4 VCC GND VCC GND CLK2/I3 I/O119 I/O119 I/O118 I/O118 I/O117 I/O117 I/O116 I/O116 I/O115 I/O115 NC I/O114 I/O114 I/O113 I/O113 I/O112 I/O112 I/O111 I/O111 I/O110 I/O110 GND I/O109 I/O109 I/O108 I/O108 I/O107 I/O107 I/O106 I/O106 I/O105 I/O105 I/O104 I/O104 I/O103 I/O103 I/O102 I/O102 I/O101 I/O101 I/O100 I/O100 GND 37384V-2 PRELIMINARY CY37384V CY37384V Pin Configurations (continued) 256-ball BGA Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A GND I/O21 I/O21 NC I/O16 I/O16 I/O12 I/O12 I/O9 I/O7 I/O4 I/O0 I/O190 I/O190 I/O189 I/O189 I/O186 I/O186 I/O182 I/O182 NC I/O178 I/O178 I/O175 I/O175 NC NC I/O169 I/O169 I/O168 I/O168 A B I/O23 I/O23 I/O20 I/O20 I/O19 I/O19 I/O18 I/O18 I/O15 I/O15 I/O11 I/O11 I/O8 I/O5 I/O1 I/O191 I/O191 I/O187 I/O187 I/O185 I/O185 I/O181 I/O181 NC NC I/O174 I/O174 I/O171 I/O171 I/O170 I/O170 NC I/O166 I/O166 B C NC NC I/O22 I/O22 NC I/O17 I/O17 I/O14 I/O14 I/O10 I/O10 I/O6 I/O2 NC I/O188 I/O188 I/O184 I/O184 I/O180 I/O180 I/O179 I/O179 I/O176 I/O176 I/O173 I/O173 I/O172 I/O172 I/O167 I/O167 I/O165 I/O165 I/O162 I/O162 C D I/O24 I/O24 NC NC GND NC VCCO I/O13 I/O13 GND I/O3 NC VCC I/O183 I/O183 GND I/O177 I/O177 VCCO NC GND I/O164 I/O164 TDI I/O160 I/O160 D E I/O27 I/O27 I/O26 I/O26 I/O25 I/O25 NC I/O163 I/O163 I/O161 I/O161 I/O159 I/O159 I/O156 I/O156 E F I/O30 I/O30 TCK I/O28 I/O28 VCCO VCCO I/O158 I/O158 NC I/O154 I/O154 F G I/O33 I/O33 I/O32 I/O32 I/O31 I/O31 I/O29 I/O29 I/O157 I/O157 I/O155 I/O155 I/O153 I/O153 I/O152 I/O152 G H I/O35 I/O35 NC I/O34 I/O34 GND GND GND GND GND GND GND GND I/O151 I/O151 I/O150 I/O150 I/O149 I/O149 H J I/O39 I/O39 I/O38 I/O38 I/O37 I/O37 I/O36 I/O36 GND GND GND GND GND GND I/O148 I/O148 I/O147 I/O147 I/O146 I/O146 I/O145 I/O145 J K I/O42 I/O42 I/O40 I/O40 I/O41 I/O41 VCC GND GND GND GND GND GND I/O144 I/O144 CLK3/I4 NC NC K L I/O43 I/O43 I/O44 I/O44 I/O45 I/O45 I/O46 I/O46 GND GND GND GND GND GND VCC NC L M I/O47 I/O47 I/O48 I/O48 GND GND GND GND GND GND I/O139 I/O139 I/O140 I/O140 I/O141 I/O141 I/O142 I/O142 M N I/O49 I/O49 I/O50 I/O50 I/O51 I/O51 GND GND GND GND GND GND GND GND I/O136 I/O136 I/O137 I/O137 I/O138 I/O138 N P I/O52 I/O52 I/O53 I/O53 I/O55 I/O55 I/O58 I/O58 I/O131 I/O131 I/O133 I/O133 I/O134 I/O134 I/O135 I/O135 P R I/O54 I/O54 I/O56 I/O56 I/O59 I/O59 VCCO VCCO I/O130 I/O130 NC I/O132 I/O132 R T I/O57 I/O57 I/O60 I/O60 I/O62 I/O62 I/O65 I/O65 I/O124 I/O124 I/O127 I/O127 I/O128 I/O128 I/O129 I/O129 T U I/O61 I/O61 I/O63 I/O63 I/O66 I/O66 GND I/O76 I/O76 VCCO I/O82 I/O82 GND I/O91 I/O91 VCC I/O98 I/O98 I/O102 I/O102 GND I/O112 I/O112 VCCO NC GND I/O123 I/O123 I/O122 I/O122 I/O126 I/O126 U V I/O64 I/O64 I/O67 I/O67 I/O69 I/O69 I/O75 I/O75 I/O78 I/O78 I/O81 I/O81 I/O85 I/O85 I/O88 I/O88 I/O92 I/O92 I2 I/O97 I/O97 I/O101 I/O101 I/O105 I/O105 I/O109 I/O109 I/O113 I/O113 TDO I/O114 I/O114 I/O117 I/O117 I/O121 I/O121 I/O125 I/O125 V W I/O68 I/O68 I/O70 I/O70 I/O72 I/O72 I/O74 I/O74 I/O79 I/O79 I/O83 I/O83 I/O86 I/O86 I/O89 I/O89 I/O93 I/O93 I/O95 I/O95 I/O96 I/O96 I/O100 I/O100 I/O104 I/O104 I/O107 I/O107 I/O110 I/O110 NC NC I/O115 I/O115 I/O118 I/O118 I/O120 I/O120 W Y I/O71 I/O71 I/O73 I/O73 I/O77 I/O77 TMS I/O80 I/O80 I/O84 I/O84 I/O87 I/O87 I/O90 I/O90 I/O94 I/O94 NC NC I/O99 I/O99 I/O103 I/O103 I/O106 I/O106 I/O108 I/O108 I/O111 I/O111 NC NC I/O116 I/O116 I/O119 I/O119 Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK0/I0 CLK1/I1 *NOTE: Center pins must be connected to GND to aid thermal dissipation. 4 CLK2/I3 I/O143 I/O143 PRELIMINARY CY37384V CY37384V Maximum Ratings DC Voltage Applied to Outputs in High Z State.0.5V to +4.6V (Above which the useful life may be impaired. For user guidelines, not tested.) DC Input Voltage .0.5V to +4.6V DC Program Voltage. 3.0 to 3.6V Storage Temperature . 65°C to +150°C Output Current into Outputs . 8 mA Ambient Temperature with Power Applied . 55°C to +125°C Static Discharge Voltage . >2001V (per MIL-STD-883 MIL-STD-883, Method 3015) Supply Voltage to Ground Potential . 0.5V to +4.6V Latch-Up Current. >200 mA Operating Range[2] Ambient Temperature[2] Industrial VCC 0°C to +90°C 3.3V ± 0.3V 40°C to +85°C Commercial Junction Temperature 0°C to +70°C Range -40°C to +125°C 3.3V ± 0.3V Electrical Characteristics Over the Operating Range Parameter VOH Description Output HIGH Voltage Test Conditions Min. [3] VCC = Min. IOH = 4 mA (Com'l) Max. [3] IOL = 8 mA (Com'l) Unit 2.4 V VOL Output LOW Voltage VCC = Min. 0.5 V VIH Input HIGH Voltage Guaranteed Input Logical HIGH voltage for all inputs[4] 2.0 VCCmax V VIL Input LOW Voltage Guaranteed Input Logical LOW voltage for all inputs[4] 0.5 0.8 V IIX Input Load Current VI = Internal GND, VI = VCC 10 10 µA IOZ Output Leakage Current VO = GND or VCC, Output Disabled 50 50 µA IOS Output Short Circuit Current[5, 6] 30 160 mA IBHL Input Bus Hold LOW Sustaining Current VCC = Max., VOUT = 0.5V VCC = Min., VIL = 0.8V +75 µA IBHH Input Bus Hold HIGH Sustaining Current VCC = Min., VIH = 2.0V 75 µA IBHLO Input Bus Hold LOW Overdrive Current VCC = Max. +500 µA IBHHO Input Bus Hold HIGH Overdrive Current VCC = Max. 500 µA Inductance[6] Parameter L Description Maximum Pin Inductance Test Conditions VIN = 3.3V at f = 1 MHz 208-lead PQFP Unit 11 nH Capacitance[6] Parameter CI/O Description Input/Output Capacitance Test Conditions Max. Unit VIN = 3.3V at f = 1 MHz at TA = 25°C 8 pF CCLK Clock Signal Capacitance VIN = 3.3V at f = 1 MHz at TA = 25°C 12 pF Notes: 2. Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the Ultra37000 family devices see the Ultra37000 family data sheet. 3. IOH = 2 mA, IOL = 2 mA for TDO. 4. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 5. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 6. Tested initially and after any design or process changes that may affect these parameters. 5 PRELIMINARY CY37384V CY37384V Endurance Characteristics[6] Parameter N Description Test Conditions Min. [2] Minimum Reprogramming Cycles Normal Programming Conditions Typ. Unit 1,000 10,000 Cycles AC Test Loads and Waveforms 238 (COM'L) 319 (MIL) 238 (COM'L) 319 (MIL) 5V 5V OUTPUT 170 (COM'L) 236 (MIL) 35 pF (a) 90% OUTPUT INCLUDING JIG AND SCOPE ALL INPUT PULSES 3.0V 170 (COM'L) GND 236 (MIL)