CY241V08A-12 XBUF/27 JESD22-A114-B ECX-5808-27 CY241V8ASXC-12 CY241V8ASXC-12T

Clock Generator with VCXO Features · · · · Benefits Integrated phase-locked loop (PLL) Low-jitter,

CY241V08A-12 CY241V08A-12 Clock Generator with VCXO Features · · · · Benefits Integrated phase-locked loop (PLL) Low-jitter, high-accuracy outputs VCXO with analog adjust 3.3V operation · Highest-performance PLL tailored for multimedia applications · Meets critical timing requirements in complex system designs · Application compatibility for a wide variety of designs Frequency Table Part Number Outputs CY241V08A-12 CY241V08A-12 2 Input Frequency Range Output Frequencies 27-MHz pullable crystal input per Cypress specification One copy of 27 MHz One copy of 74.25 MHz VCXO Control Curve linear Block Diagram PLL OUTPUT DIVIDER 74.25MHz 27 XIN XOUT XBUF/27MHz OSC VCXO VSS VDD Pin Configuration CY241V08A-12 CY241V08A-12 8-pin SOIC XIN 1 8 XOUT VDD VCXO 2 7 NC 3 6 74.25 MHz VSS 4 5 XBUF/27 XBUF/27 MHz Cypress Semiconductor Corporation Document #: 38-07676 Rev. * · 3901 North First Street · San Jose, CA 95134 · 408-943-2600 Revised June 02, 2004 [+] Feedback CY241V08A-12 CY241V08A-12 Pin Definitions Name Pin Number Description XIN 1 Reference crystal input. VDD 2 Voltage supply. VCXO 3 Input analog control for VCXO. VSS 4 Ground. XBUF/27 XBUF/27 MHz 5 27 MHz buffered crystal output. 74.25 MHz 6 74.25 MHz clock output. NC 7 No Connect. XOUT 8 Reference crystal output. Document #: 38-07676 Rev. * Page 2 of 6 [+] Feedback CY241V08A-12 CY241V08A-12 Absolute Maximum Conditions Data Retention @ Tj = 125°C.> 10 years Supply Voltage (VDD) .0.5 to +7.0V DC Input Voltage. 0.5V to VDD + 0.5 Storage Temperature (Non-condensing). 55°C to +125°C Junction Temperature . 40°C to +125°C Package Power Dissipation. 350 mW ESD (Human Body Model) JESD22-A114-B JESD22-A114-B . > 2000V (Above which the useful life may be impaired. For user guidelines, not tested.) Pullable Crystal Specifications[1] Parameter Description Comments Min. Typ. FNOM Nominal crystal frequency Parallel resonance, fundamental mode, AT cut CLNOM Nominal load capacitance R1 Equivalent series resistance (ESR) Fundamental mode R3/R1 Ratio of third overtone mode ESR to fundamental mode ESR Ratio used because typical R1 values are much less than the maximum spec Max. Unit MHz 27 14 pF 25 3 DL Crystal drive level No external series resistor assumed 150 µW F3SEPHI Third overtone separation from 3*FNOM High side 300 ppm F3SEPLO Third overtone separation from 3*FNOM Low side 150 ppm C0 Crystal shunt capacitance 7 pF C0/C1 Ratio of shunt to motional capacitance 180 250 C1 Crystal motional capacitance 14.4 18 21.6 fF Recommended Operating Conditions Parameter Description Min. V 70 °C Max. Load Capacitance tPU 3.465 Ambient Temperature CLOAD 3.3 0 Operating Voltage Max. 3.135 VDD TA Typ. Power-up time for all VDD pins to reach minimum specified voltage (power ramps must be monotonic) Unit 15 pF 0.05 500 ms DC Electrical Specifications Parameter Name Description Min. Typ. Max. Unit IOH Output HIGH Current VOH = VDD 0.5V, VDD = 3.3V 12 24 mA IOL Output LOW Current VOL = 0.5V, VDD = 3.3V 12 24 mA CIN Input Capacitance Except XIN, XOUT pins VVCXO VCXO Input Range fXO [2] 7 pF VDD V Low Side 115 ppm High Side IVDD VCXO Pullability Range 0 115 ppm 40 mA Supply Current AC Electrical Specifications (VDD = 3.3V) [3] Parameter[3] Min. Typ. Max. Unit DC Output Duty Cycle Name Duty Cycle is defined in Figure 1, 50% of VDD Description 45 50 55 % ER Rising Edge Rate Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 2. 0.8 1.4 V/ns EF Falling Edge Rate Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF. See Figure 2. 0.8 1.4 V/ns Notes: 1. Crystals that meet this specification includes: Ecliptek ECX-5808-27 ECX-5808-27.000M 2. 115/+115 ppm assumes 2.5 pF of additional board level load capacitance. This range will be shifted down with more board capacitance or shifted up with less board capacitance. 3. Not 100% tested. Document #: 38-07676 Rev. * Page 3 of 6 [+] Feedback CY241V08A-12 CY241V08A-12 AC Electrical Specifications (VDD = 3.3V) (continued)[3] Parameter[3] Min. Typ. Max. Unit t9 Clock Jitter 74.25 MHz Name Peak-to-peak period jitter Description 150 ps t9 Clock Jitter XBUF/27 XBUF/27 MHz Peak-to-peak period jitter 250 ps t9 Clock Jitter 74.25 MHz 1000-cycle long term jitter 430 ps t9 Clock Jitter XBUF/27 XBUF/27 MHz 1000-cycle long term jitter 270 ps t10 PLL Lock Time 3 ms Test and Measurement Set-up VDD Outputs 0.1 µF CLOAD DUT GND Voltage and Timing Definitions t1 t2 VDD 50% of VDD Clock Output 0V Figure 1. Duty Cycle Definition t3 t4 V DD 80% of V DD 20% of V DD Clock Output 0V Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 Ordering Information Ordering Code Package Name Package Type Operating Range Operating Voltage Features CY241V8ASXC-12 CY241V8ASXC-12 SZ08 8-pin SOIC Commercial 3.3V Linear VCXO control curve CY241V8ASXC-12T CY241V8ASXC-12T SZ08 8-pin SOIC Tape and Reel Commercial 3.3V Linear VCXO control curve Document #: 38-07676 Rev. * Page 4 of 6 [+] Feedback CY241V08A-12 CY241V08A-12 Package Drawing and Dimensions 8-lead (150-Mil) SOIC S8 8 Lead (150 Mil) SOIC - S08 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 SZ08.15 LEAD FREE PKG. 8 0.189[4.800] 0.196[4.978] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C All product or company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07676 Rev. * Page 5 of 6 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY241V08A-12 CY241V08A-12 Document History Page Document Title: CY241V08A-12 CY241V08A-12 Clock Generator with VCXO Document Number: 38-07676 REV. ECN NO. Issue Date Orig. of Change * 230997 See ECN RGL Document #: 38-07676 Rev. * Description of Change New Data Sheet Page 6 of 6 [+] Feedback