CY24154 CY24154SC - Datasheet Archive

 

PRELIMINARY MediaClockTM 54-MHz MPEG Clock Generator with Digital VCXO Features Benefits · Integrated phase-locked loop

 

CY24154 CY24154 PRELIMINARY MediaClockTM 54-MHz MPEG Clock Generator with Digital VCXO Features Benefits · Integrated phase-locked loop (PLL) Highest-performance PLL tailored to multimedia applications · Low-jitter, high-accuracy outputs Meets critical timing requirements in complex system designs · VCXO with digital adjust Large ±150 ppm range, better linearity · 3.3V Operation Enables application compatibility · Serial Programming Interface (SPI) Enables dynamic VCXO configuration Part Number Outputs CY24154 CY24154 1 Input Frequency Range Output Frequencies 13.5-MHz Pullable Crystal per Cypress Specification 1 copy of 54 MHz (3.3V) Pin Configurations Logic Block Diagram CY24154 CY24154 8-pin SOIC 13.5 XIN OSC Q OUTPUT DIVIDER XOUT VCO 54 MHz P XIN SCLK 8 XOUT 2 7 3 6 VSS SDAT 1 VDD SDAT PLL 4 5 N/C 54 MHz SCLK Serial Programming Interface VDD Cypress Semiconductor Corporation Document #: 38-07321 Rev. * · VSS 3901 North First Street · San Jose · CA 95134 · 408-943-2600 Revised March 22, 2002 PRELIMINARY CY24154 CY24154 Summary Name Pin Number Description XIN 1 Reference Crystal Input VDD 2 Output Voltage Supply SDAT 3 Serial Data Input VSS 4 Output Ground SCLK 5 Serial Clock Input 54 MHz 6 54-MHz Clock Output N/C 7 No Connect XOUT[1] 8 Reference Crystal Output Pullable Crystal Specifications Parameter Name Min. Typ. Max. Unit Crystal Load Capacitance 14 ESR Equivalent Series Resistance 35 To Operating Temperature 70 °C Crystal Accuracy Crystal Accuracy +20 ppm TTs Stability over temperature and aging +50 ppm CRload pF C0/C1 240 50 0 Absolute Maximum Conditions Parameter Description Min. Max. Unit VDD Supply Voltage ­0.5 7.0 V TS Storage Temperature[2] ­65 125 °C TJ Junction Temperature 125 °C Digital Inputs VSS ­ 0.3 VDD + 0.3 V Digital Outputs Referred to VDD VSS ­ 0.3 VDD + 0.3 Electrostatic Discharge V 2 kV Recommended Operating Conditions Parameter Description VDD Operating Voltage TA Ambient Temperature CLOAD Reference Frequency Typ. Max. Unit 3.3 3.465 V 70 °C 15 pF Max Load Capacitance fREF Min. 3.135 0 13.5 MHz Note: 1. Float XOUT if XIN is externally driven. 2. Rated for 10 years. Document #: 38-07321 Rev. * Page 2 of 6 PRELIMINARY CY24154 CY24154 DC Electrical Characteristics Parameter Min. Typ. IOH Output HIGH Current Name VOH = VDD ­ 0.5, VDD = 3.3 V 12 24 VOL = 0.5, VDD=3.3 V 12 24 IOL Output LOW Current CIN Input Leakage Current Max. fxo Supply Current mA 7 pF +150 ppm 30 mA µA 5 VCXO Pullability Range IDD Unit mA Input Capacitance IIZ Description ­150 Sum of Core and Output Current AC Electrical Characteristics (VDD = 3.3V) Parameter[3] DC Name Description Min. Typ. Max. 55 Output Duty Cycle Duty Cycle is Defined in Figure 1, 50% of VDD 45 50 t3 Rising Edge Slew Rate Output Clock Rise Time, 20%­80% of VDD 0.8 1.4 t4 Falling Edge Slew Rate Output Clock Fall Time, 80%­20% of VDD 0.8 1.4 t9 Clock Jitter Peak to Peak Period Jitter t10 PLL Lock Time Unit % V/ns V/ns 100 ps 3 ms Serial Programming Interface for the 24154 t1 t2 Introduction 50% The CY24154 CY24154 has a 2-wire serial interface that can be used for digital VCXO control. SCLK is the Serial Clock input line, and SDAT is the Serial Data input line. 54 MHz Figure 1. Duty Cycle Definition; DC = t2/t1 t3 t4 80% 54 MHz 20% Figure 2. Rise and Fall Time Definitions The SPI address for the 24154 is: A6 A5 A4 A3 A2 A1 A0 1 1 0 1 0 0 1 VCXO control is at address 13h [00010011], bits [7.0]. The MSB, bit 7, is shifted in first. The VCXO register data can be any value between 00H­FFH. As you increase the value, the capacitance on the Xin and the Xout pins will increase, thereby decreasing the xtal frequency. SDAT Write 1-bit Slave ACK 1-bit 1-bit Slave R/W = 0 ACK 7-bit Device Address 8-bit Register Address 8-bit Register Data Stop Signal Start Signal SDAT Read 1 Bit 1 Bit Slave ACK R/W = 0 7 Bit Device Address 1-bit Slave ACK 1 Bit Slave ACK 8 Bit Register Address 1 Bit Slave 1 Bit R/W = 1 ACK 7 Bit Device Address 1 Bit Master ACK 8 Bit Register Data Start Signal Stop Signal Repeated Start Signal Figure 3. Data Frame Architecture Note: 3. Not 100% tested. Document #: 38-07321 Rev. * Page 3 of 6 PRELIMINARY CY24154 CY24154 Data Valid SDAT Data Valid Transition to next Bit Data is valid when the clock is HIGH, and may only be transitioned when the clock is LOW, as illustrated in Figure 4. Data Frame Every new data frame is indicated by a start and stop sequence, as illustrated in Figure 5. tSU Start Sequence ­ Start Frame is indicated by SDAT going LOW when SCLK is HIGH. Every time a start signal is given, the next 8-bit data must be the device address (7 bits) and a R/W bit. CLKLOW Stop Sequence ­ Stop Frame is indicated by SDAT going HIGH when SCLK is HIGH. A Stop Frame frees the bus for writing to another part on the same bus or writing to another random register address. tDH SCLK CLKHIGH VIH VIL Figure 4. Data Valid and Data Transition Periods Programmable Interface Timing Acknowledge Pulse The CY24154 CY24154 utilizes a 2-serial-wire interface SDAT and SCLK that operates up to 400 kbits/sec in Read or Write mode. The basic Write serial format is as follows: During Write mode the CY24154 CY24154 will respond with an Acknowledge pulse after every 8 bits. This is accomplished by pulling the SDAT line LOW during the N*9th clock cycle as illustrated in Figure 6. (N = the number of 8 bit segments transmitted.) During Read Mode the acknowledge pulse after the data packet is sent is generated by the master. Start bit; 7-bit Device Address (DA); R/W Bit; Slave Clock Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in MA+2; ACK; etc. until STOP bit.The basic serial format is illustrated in Figure 3. SDAT SCLK Transition to next Bit START STOP Figure 5. Start and Stop Frame SDAT + START DA6 DA5 DA0 + R/W ACK RA7 ACK D6 D1 D0 ACK STOP + Figure 6. Frame Format (Device Address, R/W, Register Address, Register Data Parameter fSCLK RA0 + + SCLK RA6 RA1 + D7 Description Min. Start Mode Time from SDA LOW to SCL LOW Unit 400 Frequency of SCLK Max. kHz 0.6 µs CLKLOW SCLK LOW Period 1.3 µs CLKHIGH SCLK HIGH Period 0.6 ns tSU Data Transition to SCLK HIGH 100 ns tDH Data Hold (SCLK LOW to Data Transition) 0 ns Rise Time of SCLK and SDAT 300 ns Fall Time of SCLK and SDAT 300 ns Stop Mode Time from SCLK HIGH to SDAT HIGH 0.6 µs Stop Mode to Start Mode 1.3 µs Document #: 38-07321 Rev. * Page 4 of 6 PRELIMINARY CY24154 CY24154 Test Circuit VDD CLKOUT 0.1 µF CLOAD OUTPUTS GND Ordering Information Ordering Code Package Name Package Type Operating Range Operating Voltage CY24154SC CY24154SC S8 8-pin SOIC Commercial 3.3V Package Diagram 8-lead (150-mil) SOIC S8 51-85066-A All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07321 Rev. * Page 5 of 6 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CY24154 CY24154 Document Title: CY24154 CY24154 MediaClock 54-MHz MPEG Clock Generator with Digital VCXO Document Number: 38-07321 REV. ECN NO. Issue Date Orig. of Change * 111590 04/02/02 CKN Document #: 38-07321 Rev. * Description of Change New Data Sheet Page 6 of 6