CY22393 CY22394 CY22395 CY3672 CY22393FC CY22393FI CY22394FC CY22394FI - Datasheet Archive

 

CY22393, CY22394, CY22395 Three-PLL Serial Programmable FLASH Programmable Clock Generator Features Benefits Three integrated

 

5 CY22393 CY22393, CY22394 CY22394, CY22395 CY22395 Three-PLL Serial Programmable FLASH Programmable Clock Generator Features Benefits Three integrated phase-locked loops Generates up to 3 unique frequencies on up to 6 outputs from an external source. Ultra-Wide Divide Counters (8-bit Q, 11-bit P, and 7-bit Allows for 0 ppm Frequency Generation and Frequency ConverPost Divide) sion under the most demanding applications. Improved Linear Crystal Load Capacitors Improves frequency accuracy over temperature, age, process, and initial offset. Flash programmability Non-Volatile programming enables easy customization, ultrafast turnaround, performance tweaking, design timing margin testing, inventory control, lower part count, and more secure product supply. In addition, any part in the family can also be programmed multiple times, which reduces programming errors and provides an easy upgrade path for existing designs. Field programmable In-house programming of samples and prototype quantities are available using the CY3672 CY3672 FTG Development Kit. Production quantities are available through Cypress Semiconductor's value added Distribution partners or by using third party programmers from BP Microsystems, HiLo Systems, and others. Low-jitter, high-accuracy outputs Performance suitable for high-end multimedia, communications, industrial, A/D Converters, and consumer applications. Power-management options (Shutdown, OE, Suspend) Supports numerous low-power application schemes and reduces EMI by allowing unused outputs to be turned off. Configurable crystal drive strength Adjust Crystal Drive Strength for compatibility with virtually all crystals. Frequency Select via three external LVTTL inputs 3-Bit External Frequency Select Options for PLL1, CLKA, and CLKB. 3.3V operation Industry-standard supply voltage. 16-pin TSSOP Package Industry-standard packaging saves on board space. CyClocksRTTM Support Easy to use software support for design entry. Advanced Features Benefits Serial programmable Allows in-system programming into volatile configuration memory. All frequency settings can be changed providing literally millions of frequency options. Configurable output buffer Adjust Output Buffer strength to lower EMI or improve timing margin. Digital VCXO Fine tune crystal oscillator frequency by changing load capacitance. High-Frequency LV PECL output (CY22394 CY22394 only) Differential Output up to 400 MHz. 3.3/2.5V outputs (CY22395 CY22395 only) Provides interfacing option for low-voltage parts. CyClocksRT is a trademark of Cypress Semiconductor Corporation. Cypress Semiconductor Corporation Document #: 38-07186 Rev. * · 3901 North First Street · San Jose · CA 95134 · 408-943-2600 Revised December 3, 2001 CY22393 CY22393, CY22394 CY22394, CY22395 CY22395 Selector Guide Part Number Outputs Input Frequency Range Output Frequency Range Specifics CY22393FC CY22393FC 6 CMOS 8 MHz­30 MHz (external crystal) Up to 200 MHz 1 MHz­166 MHz (reference clock) Commercial Temperature CY22393FI CY22393FI 6 CMOS 8 MHz­30 MHz (external crystal) Up to 166 MHz 1 MHz­150 MHz (reference clock) Industrial Temperature CY22394FC CY22394FC 1 PECL / 4 CMOS 8 MHz­30 MHz (external crystal) 100 MHz­400 MHz (PECL) 1 MHz­166 MHz (reference clock) Up to 200 MHz (CMOS) Commercial Temperature CY22394FI CY22394FI 1 PECL / 4 CMOS 8 MHz­30 MHz (external crystal) 125 MHz­375 MHz (PECL) 1 MHz­150 MHz (reference clock) Up to 166 MHz (CMOS) Industrial Temperature CY22395FC CY22395FC 4 LVCMOS / 1 CMOS 8 MHz­30 MHz (external crystal) Up to 200 MHz (3.3V) 1 MHz­166 MHz (reference clock) Up to 133 MHz (2.5V) Commercial Temperature CY22395FI CY22395FI 4 LVCMOS / 1 CMOS 8 MHz­30 MHz (external crystal) Up to 166 MHz (3.3V) 1 MHz­150 MHz (reference clock) Up to 133 MHz (2.5V) Industrial Temperature Logic Block Diagram - CY22393 CY22393 XTALIN XTALOUT XBUF OSC. CONFIGURATION FLASH PLL1 Divider /2, /3, or /4 CLKE Divider 7-Bit CLKD Divider 7-Bit CLKC Divider 7-Bit CLKB Divider 7-Bit 11-Bit P 8-Bit Q CLKA SHUTDOWN/OE SCLK SDAT PLL2 11-Bit P 8-Bit Q S2/SUSPEND PLL3 4x4 Crosspoint Switch 11-Bit P 8-Bit Q Document #: 38-07186 Rev. * Page 2 of 15 CY22393 CY22393, CY22394 CY22394, CY22395 CY22395 Logic Block Diagram - CY22394 CY22394 XTALIN XTALOUT XBUF OSC. CONFIGURATION FLASH PLL1 11-Bit P 8-Bit Q 0º PECL OUTPUT 180º P+CLK P-CLK SHUTDOWN/OE SCLK PLL2 S2/SUSPEND Divider 7-Bit 4x4 Crosspoint Switch PLL3 CLKC CLKB CLKA Divider /2, /3, or /4 11-Bit P 8-Bit Q Divider 7-Bit Divider 7-Bit SDAT LCLKE 11-Bit P 8-Bit Q Logic Block Diagram - CY22395 CY22395 XTALIN XTALOUT OSC. CONFIGURATION FLASH PLL1 11-Bit P 8-Bit Q Divider 7-Bit LCLKD Divider 7-Bit CLKC Divider 7-Bit SHUTDOWN/OE LCLKB Divider 7-Bit LCLKA SCLK 4x4 Crosspoint Switch SDAT S2/SUSPEND PLL2 11-Bit P 8-Bit Q PLL3 11-Bit P 8-Bit Q LCLKA, LCLKB, LCLKD, LCLKE referenced to LVDD Document #: 38-07186 Rev. * Page 3 of 15 CY22393 CY22393, CY22394 CY22394, CY22395 CY22395 Pin Configurations CY22393 CY22393 16-pin TSSOP CY22395 CY22395 16-pin TSSOP CY22394 CY22394 16-pin TSSOP CLKC 1 16 SHUTDOWN/OE VDD 2 15 S2/SUSPEND CLKC 1 16 2 15 CLKC S2/SUSPEND 1 16 SHUTDOWN/OE VDD SHUTDOWN/OE VDD 2 15 S2/SUSPEND AGND 3 14 AVDD AGND 3 14 AVDD AGND 3 14 AV DD XTALIN 4 13 SCLK (S1) XTALIN 4 13 SCLK (S1) XTALIN 4 13 SCLK (S1) XTALOUT XBUF 5 12 12 11 XTALOUT LVDD 12 6 SDAT (S0) GND 5 11 XTALOUT XBUF 5 6 SDAT (S0) GND 6 11 SDAT (S0) GND/LGND CLKD 7 10 CLKA P­CLK 7 10 CLKA LCLKD 7 10 LCLKA CLKE 8 9 CLKB P+ CLK 8 9 CLKB LCLKE 8 9 LCLKB Pin Summary Name Pin Number CY22393 CY22393 Pin Number CY22394 CY22394 Pin Number CY22395 CY22395 Description CLKC 1 1 1 Configurable clock output C VDD 2 2 2 Power supply AGND 3 3 3 Analog Ground XTALIN 4 4 4 Reference crystal input or external reference clock input XTALOUT 5 5 5 Reference crystal feedback XBUF 6 6 N/A Buffered reference clock output LVDD N/A N/A 6 Low Voltage Clock Output Power Supply CLKD or LCLKD 7 N/A 7 Configurable clock output D; LCLKD referenced to LVDD P­CLK N/A 7 N/A LV PECL Output[1] CLKE or LCLKE 8 N/A 8 Configurable clock output E; LCLKE referenced to LVDD P+ CLK N/A 8 N/A LV PECL Output[1] CLKB or LCLKB 9 9 9 Configurable clock output B; LCLKB referenced to LVDD CLKA or LCLKA 10 10 10 Configurable clock output A; LCLKA referenced to LVDD GND/LGND 11 11 11 Ground SDAT (S0) 12 12 12 Two Wire Serial Port Data. S0 value latched during start-up SCLK (S1) 13 13 13 Two Wire Serial Port Clock. S1 value latched during start-up AVDD 14 14 14 Analog Power Supply S2/ SUSPEND 15 15 15 General Purpose Input for Frequency Control; bit 2. Optionally Suspend mode control input SHUTDOWN/ OE 16 16 16 Places outputs in three-state condition and shuts down chip when LOW. Optionally, only places outputs in three-state condition and does not shut down chip when LOW Note: 1. LV PECL outputs require an external termination network. Document #: 38-07186 Rev. * Page 4 of 15 CY22393 CY22393, CY22394 CY22394, CY22395 CY22395 Operation The CY22393 CY22393, CY22394 CY22394, and CY22395 CY22395 are a family of parts designed as upgrades to the existing CY22392 CY22392 device. These parts have similar performance to the CY22392 CY22392, but provide advanced features to meet more demanding applications. The clock family has three PLLs which, when combined with the reference, allow up to four independent frequencies to be output on up to six pins. These three PLLs are completely programmable. Configurable PLLs PLL1 generates a frequency that is equal to the reference divided by an 8-bit divider (Q) and multiplied by an 11-bit divider in the PLL feedback loop (P). The output of PLL1 is sent to two locations: the crosspoint switch and the PECL output (CY22394 CY22394). The output of PLL1 is also sent to a /2, /3, or /4 synchronous post-divider that is output through CLKE. The frequency of PLL1 can be changed via serial programming or by external CMOS inputs, S0, S1, S2. See the following section on General-Purpose Inputs for more detail. PLL2 generates a frequency that is equal to the reference divided by an 8-bit divider (Q) and multiplied by an 11-bit divider in the PLL feedback loop (P). The output of PLL2 is sent to the crosspoint switch. The frequency of PLL2 can be changed via serial programming. PLL3 generates a frequency that is equal to the reference divided by an 8-bit divider (Q) and multiplied by an 11-bit divider in the PLL feedback loop (P). The output of PLL3 is sent to the crosspoint switch. The frequency of PLL3 can be changed via serial programming. General-Purpose Inputs S2 is a general-purpose input that can be programmed to allow for two different frequency settings. Options that may be switched with this general-purpose input are as follows: the frequency of PLL1, the output divider of CLKB, and the output divider of CLKA. The two frequency settings are contained within an eight-row frequency table. The values of SCLK (S1) and SDAT (S0) pins are latched during start-up and used as the other two indexes into this array. CLKA and CLKB both have 7-bit dividers that point to one of two programmable settings (register 0 and register 1). Both clocks share a single register control, so both must be set to register 0, or both must be set to register 1. For example: the part may be programmed to use S0, S1, and S2 (0,0,0 to 1,1,1) to control eight different values of P and Q on PLL1. For each PLL1 P and Q setting, one of the two CLKA and CLKB divider registers can be chosen. Any divider change as a result of switching S0, S1, or S2 is guaranteed to be glitch free. Crystal Input The input crystal oscillator is an important feature of this family of parts because of its flexibility and performance features. The oscillator inverter has programmable drive strength. This allows for maximum compatibility with crystals from various manufacturers, process, performance, and quality. The input load capacitors are placed on-die to reduce external component cost. These capacitors are true parallel-plate caDocument #: 38-07186 Rev. * pacitors for ultra-linear performance. These were chosen to reduce the frequency shift that occurs when non-linear load capacitance interacts with load, bias, supply, and temperature changes. Non-linear (FET gate) crystal load capacitors should not be used for MPEG, POTS dial tone, communications, or other applications that are sensitive to absolute frequency requirements. The value of the load capacitors is determined by six bits in a programmable register. The load capacitance can be set with a resolution of 0.375 pF for a total crystal load range of 6 pF to 30 pF. For driven clock inputs the input load capacitors may be completely bypassed. This enables the clock chip to accept driven frequency inputs up to 166 MHz. If the application requires a driven input, then XTALOUT must be left floating. Digital VCXO The serial programming interface may be used to dynamically change the capacitor load value on the crystal. A change in crystal load capacitance corresponds with a change in the reference frequency. For special pullable crystals specified by Cypress, the capacitance pull range is +150 ppm to ­150 ppm from midrange. Be aware that adjusting the frequency of the reference will affect all frequencies on all PLLs in a similar manner since all frequencies are derived from the single reference. Output Configuration Under normal operation there are four internal frequency sources that may be routed via a programmable crosspoint switch to any of the four programmable 7-bit output dividers. The four sources are: reference, PLL1, PLL2, and PLL3. The following is a description of each output. CLKA's output originates from the crosspoint switch and goes through a programmable 7-bit post divider. The 7-bit post divider derives its value from one of two programmable registers. See the section on General-Purpose Inputs for more information. CLKB's output originates from the crosspoint switch and goes through a programmable 7-bit post divider. The 7-bit post divider derives its value from one of two programmable registers. See the section on General-Purpose Inputs for more information. CLKC's output originates from the crosspoint switch and goes through a programmable 7-bit post divider. The 7-bit post divider derives its value from one programmable register. CLKD's output originates from the crosspoint switch and goes through a programmable 7-bit post divider. The 7-bit post divider derives its value from one programmable register. For the CY22394 CY22394, CLKD is brought out as the complimentary version of a LV PECL Clock referenced to CLKE, bypassing both the crosspoint switch and 7-bit post divider. CLKE's output originates from PLL1 and goes through a post divider that may be programmed to /2, /3, or /4. For the CY22394 CY22394, CLKE is brought out as an LV PECL Clock, bypassing the post divider. XBUF is simply the buffered reference. The Clock outputs have been designed to drive a single point load with a total lumped load capacitance of 15 pF. While driv- Page 5 of 15 CY22393 CY22393, CY22394 CY22394, CY22395 CY22395 ing multiple loads is possible with the proper termination it is generally not recommended. Temperature and Package Power Dissipation maximum ratings. Power Saving Features Serial Interface Operation The SHUTDOWN/OE input three-states the outputs when pulled LOW. If system shutdown is enabled, a LOW on this pin also shuts off the PLLs, counters, the reference oscillator, and all other active components. The resulting current on the VDD pins will be less than 5 µA (typical). After leaving shutdown mode, the PLLs will have to relock. The S2/SUSPEND input can be configured to shut down a customizable set of outputs and/or PLLs, when LOW. All PLLs and any of the outputs can be shut off in nearly any combination. The only limitation is that if a PLL is shut off, all outputs derived from it must also be shut off. Suspending a PLL shuts off all associated logic, while suspending an output simply forces a three-state condition. The serial port uses industry-standard signaling in both standard and fast modes. This section describes the unique features of the serial interface in this family of devices. Default Startup Condition for the CY22393/94/95 CY22393/94/95 The default (programmed) condition of each device is generally set by the distributor, who will program the device using a customer-specified JEDC file produced by CyClocksRT, Cypress's proprietary development software. Parts shipped by the factory are blank and unprogrammed. In this condition, all bits are set to 0, all outputs are three-stated, and the crystal oscillator circuit is active. With the serial interface, each PLL and/or output can be individually disabled. This provides total control over the power savings. While users can develop their own subroutine to program any or all of the individual registers as described in the following pages, it may be easier to simply use CyClocksRT to produce the required register setting file. Improving Jitter Device Address Jitter Optimization Control is useful in mitigating problems related to similar clocks switching at the same moment, causing excess jitter. If one PLL is driving more than one output, the negative phase of the PLL can be selected for one of the outputs (CLKA­CLKD). This prevents the output edges from aligning, allowing superior jitter performance. The device address is a 7-bit value that is configured during Field Programming. By programming different device addresses, two or more parts can be connected to the serial interface and be independently controlled. The device address is combined with a read/write bit as the LSB and is sent after each start bit. Power Supply Sequencing The default serial interface address is 69H, but should there be a conflict with any other devices in your system, this can also be changed using CyClocksRT. For parts with multiple VDD pins, there are no power supply sequencing requirements. The part will not be fully operational until all VDD pins have been brought up to the voltages specified in the "Operating Conditions" table. All grounds should be connected to the same ground plane. CyClocksRTTM Software CyClocksRT is our second-generation application that allows users to configure this family of devices. The easy-to-use interface offers complete control of the many features of this family including input frequency, PLL and output frequencies, and different functional options. Data sheet frequency range limitations are checked and performance tuning is automatically applied. CyClocksRT also has a power estimation feature that allows you to see the power consumption of your specific configuration. You can download a copy of CyClocksRT for free on Cypress's web site at www.cypress.com. CyClocksRT is used to generate P, Q, and divider values used in serial programming. There are many internal frequency rules which are not documented in this data sheet, but are required for proper operation of the device. These rules can be checked by using the latest version of CyClocksRT. Junction Temperature Limitations It is possible to program this family such that the maximum Junction Temperature rating is exceeded. The package JA is 115 °C/W. Use the CyClocksRT power estimation feature to verify that the programmed configuration meets the Junction Document #: 38-07186 Rev. * Memory Address This family of devices supports 1-byte memory addressing. The memory address is always sent after each Device Address/Write bit combination. It describes the memory location within the device to be accessed. The memory address is incremented after each acknowledge, allowing sequential memory access. To read a memory location, a write operation must be performed with the memory address to be read, and zero data bytes. This is followed by a repeated start bit and the Device Address/Read byte, after which the desired memory location is available for reading. Valid memory locations are shown in the "Serial Programming Memory Bitmap" section. All registers are read and write capable. Some reserved registers are not shown. For proper device operation, do not write data outside of the addresses shown. Memory Data For writes, all of the bytes sent to the device between the Memory Address and a stop bit or repeated start bit are interpreted as data. Each data byte is written to the current memory address, which is incremented after each acknowledge. For reads, data is shifted out immediately after the Device Address/Read byte. Bytes are shifted out sequentially until a notacknowledge followed by a stop bit are received by the device. Page 6 of 15 CY22393 CY22393, CY22394 CY22394, CY22395 CY22395 Dynamic Updates Clk*_FS[2:0] Clock Source 000 Reference Clock The output divider registers are not synchronized with the output clocks. Changing the divider value of an active output will likely cause a glitch on that output. 001 PLL P and Q data is spread between three bytes. Each byte becomes active on the acknowledge for that byte, so changing P and Q data for an active PLL will likely cause the PLL try to lock on an out-of-bounds condition. For this reason, it is recommended that the PLL being programmed be turned off during the update. This can be done by setting the PLL*_En bit LOW. PLL1, CLKA, and CLKB each have multiple registers supplying data. Programming these resources can be accomplished safely by always programming an inactive register, and then transitioning to that register. This allows these resources to stay on during programming. The serial interface is active even with the SHUTDOWN/OE pin LOW as the serial interface logic uses static components and is completely self-timed. The part will not meet the IDDS current limit with transitioning inputs. Reserved 010 PLL1 0° Phase 011 PLL1 180° Phase 100 PLL2 0° Phase 101 PLL2 180° Phase 110 PLL3 0° Phase 111 PLL3 180° Phase Xbuf_OE This bit enables the XBUF output when HIGH. For the CY22395 CY22395, Xbuf_OE = 0. PdnEn Memory Bitmap Definitions This bit selects the function of the SHUTDOWN/OE pin. When this bit is HIGH, the pin is an active LOW shutdown control. When this bit is LOW, this pin is an active HIGH output enable control. Clk{A­D}_Div[6:0] Clk*_ACAdj[1:0] Each of the four main output clocks (CLKA­CLKD) features a 7-bit linear output divider. Any divider setting may be used between 1 and 127 by programming the value of the desired divider into this register. Odd divide values are automatically duty-cycle corrected. Setting a divide value of zero powers down the divider and forces the output to a three-state condition. These bits modify the output predrivers, changing the duty cycle through the pads. These are nominally set to 01, with a higher value shifting the duty cycle higher. The performance of the nominal setting is guaranteed. CLKA and CLKB have two divider registers, selected by the DivSel bit (which in turn is selected by S2, S1, and S0). This allows dynamic changing of the output divider value. For the CY22394 CY22394 device, ClkD_Div = 000001. Clk*_DCAdj[1:0] These bits modify the DC drive of the outputs. The performance of the nominal setting is guaranteed. Clk*_DCAdj[1:0] Output Drive Strength 00 ­30% of nominal 01 Nominal ClkE_Div[1:0] CLKE has a simpler divider. ClkE_Div = 01. 10 +15% of nominal 11 For the CY22394 CY22394, set +50% of nominal ClkE_Div[1:0] ClkE Output PLL*_Q[7:0] 00 Off PLL*_P[9:0] 01 PLL1 0° Phase/4 10 PLL1 0° Phase/2 11 PLL1 0° Phase/3 Clk*_FS[2:0] Each of the four main output clocks (CLKA­CLKD) has a three-bit code that determines the clock sources for the output divider. The available clock sources are: Reference, PLL1, PLL2, and PLL3. Each PLL provides both positive and negative phased outputs, for a total of seven clock sources. Note that the phase is a relative measure of the PLL output phases. No absolute phase relation exists at the outputs Document #: 38-07186 Rev. * PLL*_P0 These are the 8-bit Q value and 11-bit P values that determine the PLL frequency. The formula is: PT FPLL = F REF × - Q T P T = ( 2 × ( P + 3 ) ) + PO Qt = Q + 2 PLL*_LF[2:0] These bits adjust the loop filter to optimize the stability of the PLL. The following table can be used to guarantee stability. However, CyClocksRT uses a more complicated algorithm to set the loop filter for enhanced jitter performance. It is recommended to use the Print Preview function in CyClocksRT to determine the charge pump settings for optimal jitter performance. Page 7 of 15 CY22393 CY22393, CY22394 CY22394, CY22395 CY22395 PLL*_LF[2:0] PT Min PT Max 000 16 231 001 232 626 010 627 834 011 835 1043 100 1044 1600 PLL*_En OscDrv[1:0] These bits control the crystal oscillator gain setting. These should always be set according to the following table. The parameters are the Crystal Frequency, Internal Crystal Parasitic Resistance (available from the manufacturer), and the OscCap setting during crystal start-up (which occurs when power is applied, or after shutdown is released). If in doubt, use the next higher setting. OscCap This bit enables the PLL when HIGH. If PLL2 or PLL3 are not enabled, then any output selecting the disabled PLL must have a divider setting of zero (off). Since the PLL1_En bit is dynamic, internal logic automatically turns off dependent outputs when PLL1_En goes LOW. 00H­20H 20H­30H 30H­40H Crystal Freq\ R 30 60 30 60 30 60 8­15 MHz 00 01 01 10 01 10 DivSel This bit controls which register is used for the CLKA and CLKB dividers. OscCap[5:0] This controls the internal capacitive load of the oscillator. The approximate effective crystal load capacitance is: C LOAD = 6pF + ( OscCap × 0.375pF ) Set to zero for external reference clock. Document #: 38-07186 Rev. * 15­20 MHz 01 10 01 10 10 10 20­25 MHz 01 10 10 10 10 11 25­30 MHz 10 10 10 11 11 NA For external reference, the following table must be used. External Freq (MHz) 1­25 25­50 50­90 90­166 OscDrv[1:0] 00 01 10 11 Reserved These bits must be programmed LOW for proper operation of the device. Page 8 of 15 CY22393 CY22393, CY22394 CY22394, CY22395 CY22395 Serial Programming Bitmaps - Summary Tables Addr DivSel b7 b6 b5 b4 08H 0 ClkA_FS[0] ClkA_Div[6:0] 09H 1 ClkA_FS[0] ClkA_Div[6:0] 0AH 0 ClkB_FS[0] ClkB_Div[6:0] 0BH 1 ClkB_FS[0] ClkB_Div[6:0] 0CH - ClkC_FS[0] ClkC_Div[6:0] 0DH - ClkD_FS[0] ClkD_Div[6:0] 0EH - ClkD_FS[2:1] ClkC_FS[2:1] 0FH - Clk{C,X}_ACAdj[1:0] Clk{A,B,D,E}_ACAdj[1:0] 10H - ClkX_DCAdj[1] Clk{D,E}_DCAdj[1] 11H - 12H - 13H - b3 b2 ClkB_FS[2:1] PdnEn Xbuf_OE ClkC_DCAdj[1] b1 b0 ClkA_FS[2:1] ClkE_Div[1:0] Clk{A,B}_DCAdj[1] PLL2_Q[7:0] PLL2_P[7:0] Reserved PLL2_En PLL2_LF[2:0] PLL2_PO 14H - PLL3_Q[7:0] 15H - PLL3_P[7:0] 16H - 17H - Addr S2 (1,0) 40H 000 PLL2_P[9:8] Reserved PLL3_En b7 b6 DivSel PLL1_En 001 DivSel PLL1_En 010 DivSel PLL1_En 011 PLL1_LF[2:0] PLL1_PO PLL1_P[9:8] PLL1_LF[2:0] PLL1_PO PLL1_P[9:8] PLL1_LF[2:0] PLL1_PO PLL1_P[9:8] PLL1_PO PLL1_P[9:8] PLL1_PO PLL1_P[9:8] PLL1_PO PLL1_P[9:8] PLL1_PO PLL1_P[9:8] PLL1_PO PLL1_P[9:8] PLL1_P[7:0] 4BH DivSel PLL1_En 100 PLL1_LF[2:0] PLL1_Q[7:0] 4DH PLL1_P[7:0] 4EH DivSel PLL1_En 101 PLL1_LF[2:0] PLL1_Q[7:0] 50H PLL1_P[7:0] 51H DivSel PLL1_En 110 PLL1_LF[2:0] PLL1_Q[7:0] 53H PLL1_P[7:0] 54H DivSel PLL1_En 111 PLL1_LF[2:0] PLL1_Q[7:0] 56H 57H b0 PLL1_Q[7:0] 4AH 55H b1 PLL1_P[7:0] 48H 52H b2 PLL1_Q[7:0] 47H 4FH b3 PLL1_P[7:0] 45H 4CH b4 PLL1_Q[7:0] 44H 49H b5 PLL3_P[9:8] Osc_Drv[1:0] PLL1_P[7:0] 42H 46H PLL3_PO PLL1_Q[7:0] 41H 43H PLL3_LF[2:0] Osc_Cap[5:0] PLL1_P[7:0] DivSel Document #: 38-07186 Rev. * PLL1_En PLL1_LF[2:0] Page 9 of 15 CY22393 CY22393, CY22394 CY22394, CY22395 CY22395 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage . ­0.5V to +7.0V DC Input Voltage. ­0.5V to + (AVDD + 0.5V) Data Retention @ Tj=125°C.> 10 years Maximum Programming Cycles .100 Package Power Dissipation. 350 mW Static Discharge Voltage Storage Temperature . ­65°C to +125°C (per MIL-STD-883 MIL-STD-883, Method 3015) . > 2000V Junction Temperature . 125°C Latch up (per JEDEC 17) . > ±200 mA Operating Conditions[2] Parameter Description Part Numbers Min. Typ Max. Unit V VDD/AVDD/LVDD Supply Voltage All 3.135 3.3 3.465 LVDD 2.5V Output Supply Voltage 22395 2.375 2.5 TA Commercial Operating Temperature, Ambient All 2.625 V 0 +70 °C ­40 +85 °C 15 pF Industrial Operating Temperature, Ambient All CLOAD_OUT Max. Load Capacitance All fREF External Reference Crystal All 8 30 MHz External Reference Clock[3], Commercial All 1 166 MHz All 1 150 MHz Max. Unit [3] External Reference Clock , Industrial 3.3V Electrical Characteristics Parameter Description IOH IOL Conditions CXTAL_MIN Output Low Current Typ. 12 24 mA VOL = 0.5, (L)VDD = 3.3V [4] Min. VOH = (L)VDD ­ 0.5, (L)VDD = 3.3V Output High Current[4] 12 24 mA [4] Capload at minimum setting 6 pF [3] Crystal Load Capacitance CXTAL_MAX Crystal Load Capacitance Capload at maximum setting 30 pF CIN Input Pin Capacitance[4] Except crystal pins 7 pF VIH HIGH-Level Input Voltage CMOS levels,% of AVDD VIL LOW-Level Input Voltage CMOS levels,% of AVDD 70% AVD D 30% AVD D IIH Input HIGH Current VIN = AVDD ­ 0.3 V