CY2077 MIL-STD-883 VDD-10 CY2077SC-XXX CY2077ZC-XXX CY2077SI-XXX CY2077ZI-XXX - Datasheet Archive

 

High Accuracy EPROM Programmable Single-PLL Clock Generator Features Benefits · High accuracy PLL with 12-bit multiplier

 

CY2077 CY2077 High Accuracy EPROM Programmable Single-PLL Clock Generator Features Benefits · High accuracy PLL with 12-bit multiplier and 10-bit divider Enables synthesis of highly accurate and stable output clock frequencies with zero PPM · EPROM-programmability Enables quick turnaround of custom frequencies · 3.3V or 5V operation Supports industry standard design platforms · Operating frequency - 390 kHz­133 MHz at 5V - 390 kHz­100 MHz at 3.3V Services most PC, networking, and consumer applications · Reference input from either a 10-30 MHz fundamental toned crystal or a 1-75 MHz external clock Lowers cost of oscillator as PLL can be programmed to a high frequency using either a low-frequency, low-cost crystal, or an existing system clock · EPROM-selectable TTL or CMOS duty cycle levels Duty cycle centered at 1.5V or VDD/2 Provides flexibility to service most TTL or CMOS applications · Sixteen selectable post-divide options, using either PLL Provides flexibility in output configurations and testing or reference oscillator/external clock · Programmable PWR_DWN or OE pin, with asynchronous or synchronous modes Enables low-power operation or output enable function and flexibility for system applications, through selectable instantaneous or synchronous change in outputs · Low Jitter outputs typically - 80 ps at 3.3V/5V Suitable for most PC, consumer, and networking applications · Controlled rise and fall times and output slew rate Has lower EMI than oscillators · Available in both commercial and industrial temperature Suitable to fit most applications · Factory-programmable device options Easy customization and fast turnaround. either CY2077 CY2077 Logic Block Diagram Pin Configuration PWR_DWN XTALIN or external clock Q 10 bits Phase Detector XTALOUT [1] CRYSTAL OSCILLATOR or OE Charge Pump 8-Pin Top View CONFIGURATION EPROM VDD XTALOUT XTALIN PD/OE VCO 1 2 3 4 8 7 6 5 CLKOUT VSS VSS VSS P 12 bits HIGH ACCURACY PLL MUX Note 1. When using an external clock source leave XTALOUT floating Cypress Semiconductor Corporation CLKOUT / 1, 2, 4, 8, 16, 32, 64, 128 · 3901 North First Street · San Jose · CA 95134 · 408-943-2600 January 24, 2001 CY2077 CY2077 Functional Description PLL Output Frequency The CY2077 CY2077 is an EPROM-programmable, high-accuracy, general purpose, PLL-based design for use in applications such as modems, disk drives, CD-ROM drives, video CD players, DVD players, games, set-top boxes, and data/telecommunications. The CY2077 CY2077 contains a high resolution PLL with 12 bit multiplier and 10 bit divider.The output frequency of the PLL is determined by the following formula: 2 · (P + 5) FPLL = - · F REF (Q + 2) The CY2077 CY2077 can generate a clock output up to 133 MHz at 5V or 100 MHz at 3.3V. It has been designed to give the customer a very accurate and stable clock frequency with little to zero PPM error. The CY2077 CY2077 contains a 12-bit feedback counter divider and 10-bit reference counter divider to obtain a very high resolution to meet the needs of stringent design specifications. Further more, there are 8 output divide options of /1, /2, /4, /8, /16, /32, /64, and /128. The output divider can select between the PLL and crystal oscillator output/external clock, providing a total of 16 different options. To add more flexibility in designs. TTL or CMOS duty cycles can be selected. where P is the feedback counter value and Q is the reference counter value. P and Q are EPROM programmable values. The calculation of P and Q values for a given PLL output frequency is handled by the CyClocks software. Refer to the "Custom Configuration Request Procedure" section for details. Power Management Features PWR_DWN and OE options are configurable by EPROM programming for the CY2077 CY2077. In PWR_DWN mode, all active circuits are powered down when the control pin is set to LOW. When the control pin is set back to HIGH, both the PLL and oscillator circuit must re-lock. In the case of OE, the output is three-stated and weakly pulled down when the control pin is set to LOW. The oscillator and PLL are still active in this state, which leads to a quick clock output return when the control pin is set back to HIGH. Power management with the CY2077 CY2077 is also very flexible. The user may choose either a PWR_DWN or an OE feature with which both have integrated pull-up resistors. PWR_DWN and OE signals can be programmed to have asynchronous and synchronous timing with respect to the output siginal. There is a weak pull-down on the output that will pull CLKOUT low when either the PWR_DWN or OE siginal is active. This weak pull-down can easily be overridden by another clock signal in designs where multiple clock signals share a signal path. Additionally, PWR_DWN and OE can be configured to occur asynchronously or synchronously with respect to CLKOUT. In asynchronous mode, PWR_DWN or OE disables CLKOUT immediately (allowing for logic delays), without respect to the current state of CLKOUT. Synchronous mode will prevent output glitches by waiting for the next falling edge of CLKOUT after PWR_DWN or OE becomes asserted. In either asynchronous or synchronous setting, the output is always enabled synchronously by waiting for the next falling edge of CLKOUT. Multiple options for output selection, better power distribution layout, and controlled rise and fall times enable the CY2077 CY2077 to be used in applications which require low jitter and accurate reference frequencies. EPROM Configuration Block Table 1 summarizes the features which are configurable by EPROM . Table 1. EPROM Adjustable Features EPROM Adjustable Features Adjust Freq. Feedback counter value (P) Reference counter value (Q) Output divider selection Duty cycle levels (TTL or CMOS) Power management mode (OE or PWR_DWN) Power management timing (synchronous or asynchronous) Pin Summary Name Pin Description VDD 1 Voltage supply. VSS 5,6,7 Ground (all the pins have to be grounded). XD 2 Crystal output (leave this pin floating when external reference is used.). XG 3 Crystal input or external input reference. PWR_DWN / OE 4 EPROM programmable power down or output enable pin. Weak pull-up. CLKOUT Clock output. Weak pull-down. 8 2 CY2077 CY2077 Device Functionality: Output Frequencies Symbol Description Output frequency Condition Min. Max. Unit VDD = 4.5­5.5V 0.39 133 MHz VDD = 3.0­3.6V Fo 0.39 100 MHz Absolute Maximum Ratings Storage Temperature (Non-Condensing) . ­55°C to +150°C (Above which the useful life may be impaired. For user guidelines, not tested.) Junction Temperature . 150°C Static Discharge Voltage . >2000V (per MIL-STD-883 MIL-STD-883, Method 3015) Supply Voltage .­0.5 to +7.0V Input Voltage .­0.5V to VDD+0.5V Operating Conditions for Commercial Temperature Device Parameter Description VDD Supply Voltage TA Operating Temperature, Ambient CTTL Min. Max. Unit 3.0 5.5 V 0 +70 °C Max. Capacitive Load on outputs for TTL levels VDD = 4.5­5.5V, Output frequency = 1­40 MHz VDD = 4.5­5.5V, Output frequency = 40­125 MHz VDD = 4.5­5.5V, Output frequency = 125­133 MHz 50 25 15 pF pF pF CCMOS Max. Capacitive Load on outputs for CMOS levels VDD = 4.5­5.5V, Output frequency = 1­40 MHz VDD = 4.5­5.5V, Output frequency = 40­125 MHz VDD = 4.5­5.5V, Output frequency = 125­133 MHz VDD = 3.0­3.6V, Output frequency = 1­40 MHz VDD = 3.0­3.6V, Output frequency = 40­100 MHz 50 25 15 30 15 pF pF pF pF pF XREF Reference Frequency, input crystal with Cload = 10 pF 10 30 MHz Reference Frequency, external clock source 1 75 MHz Electrical Characteristics TA = 0°C to +70°C Parameter Description Test Conditions VIL Low-level Input Voltage VDD = 4.5­5.5V VDD = 3.0­3.6V Min. Typ. Max. Unit 0.8 0.2VDD V V VIH High-level Input Voltage VDD = 4.5­5.5V VDD = 3.0­3.6V VOL Low-level Output Voltage VDD = 4.5­5.5V, IOL= 16 mA VDD = 3.0­3.6V, IOL= 8 mA VOHCMOS High-level Output Voltage, CMOS levels VDD = 4.5­5.5V, IOH= ­16 mA VDD = 3.0­3.6V, IOH= ­8 mA VDD­0.4 VDD­0.4 V V VOHTTL High-level Output Voltage, TTL levels VDD = 4.5­5.5V, IOH= ­8 mA 2.4 V V V 2.0 0.7VDD 0.4 0.4 V V IIL Input Low Current VIN = 0V 10 µA IIH Input High Current VIN = VDD 5 µA IDD Power Supply Current, Unloaded VDD = 4.5­5.5V, Output frequency