CY2039 7C80320 MIL-STD-883 VDD-10 CY2039WAF - Datasheet Archive
High Accuracy EPROM Programmable Crystal Oscillator Features Benefits · EPROM-programmable capacitor tuning array with
CY2039 CY2039 High Accuracy EPROM Programmable Crystal Oscillator Features Benefits · EPROM-programmable capacitor tuning array with Shadow register Enables fine-tuning of output clock frequency by adjusting CLoad of the crystal · Twice programmable die EPROM redundancy allows 2 programming opportunities to correct errors, and control excess inventory · Simple 4-pin programming interface Enables programming of output frequency after packaging · On-chip oscillator runs from 1030 fundamental toned MHz crystal Lowers cost of oscillator as PPM manufacturing error can be tweaked in package · EPROM-selectable TTL or CMOS duty cycle levels Duty cycle centered at 1.4V or VDD/2 Provides flexibility to service most TTL or CMOS applications · Four selectable post-divide options, using reference os- Provides flexibility in output configurations and testing cillator output · Programmable PWR_DWN or OE pin Enables low-power operation or output enable function · Programmable asynchronous or synchronous OE and PWR_DWN modes Provides flexibility for system applications, through selectable instantaneous or synchronous change in outputs · 3.3V or 5V operation Lowers inventory cost as same die services both applications · Small Die Enables encapsulation in small-size, surface mount packages · Controlled rise and fall times and output slew rate Has lower EMI than oscillators CY2039 CY2039 Logic Block Diagram Die Configuration PWR_DWN Top View or OE VDD VDD CONFIGURATION EPROM 1 2  11 CLKOUT 10 N/C XD XD 5 XG OSCILLATOR 4 N/C CRYSTAL 3 6 9 VSS PWR_DWN or OE XG N/C / Xx 7 8 VSS 7C80320 7C80320 CLKOUT / 1, 2, 4, 8 Note: 1. For Customers not bonding XD or XG pad to external pins, an alternative bonding option would be shorting the Xx pad to the XD pad. Cypress Semiconductor Corporation · 3901 North First Street · San Jose · CA 95134 · 408-943-2600 May 21, 2001 CY2039 CY2039 Functional Description EPROM Adjustable Features The CY2039 CY2039 is a high-accuracy IC designed for the crystal oscillator market. The die attaches directly to a low-cost 1030 MHz crystal and can be packaged into 4-pin through-hole or surface mount packages. The oscillator devices can be stocked as blank parts and PPM error programmed in-package at the last stage before shipping. This enables fast-turn manufacture of custom and standard crystal oscillators without the need for dedicated, expensive crystals. Output divider selection Oscillator tuning (load capacitance values) Duty cycle levels (TTL or CMOS) Power management mode (OE or PWR_DWN) Power management timing (synchronous or asynchronous) The CY2039 CY2039 contains an on-chip oscillator and an unique oscillator tuning circuit for fine-tuning of the output frequency. The crystal Cload can be selectively adjusted by programming a set of seven EPROM bits. This feature can be used to compensate for crystal variations or to obtain a more accurate frequency. Power Management Features The CY2039 CY2039 contains EPROM programmable PWR_DWN and OE functions. If Powerdown is selected, all active circuitry on the chip is shut down when the control pin goes LOW. The oscillator must restart when the part leaves Powerdown Mode. If Output Enable mode is selected, the output is three-stated and weakly pulled LOW when the Control pin goes LOW. In this mode the oscillator circuit continues to operate, allowing a rapid return to normal operation when the Control input is deasserted. The CY2039 CY2039 uses EPROM programming with a simple two-wire, four-pin interface that includes VSS and VDD. The entire configuration can be reprogrammed one time allowing programmed inventory to be altered or reused. The CY2039 CY2039 also contains flexible power management control. The part includes both PWR_DWN and OE features with integrated pull-up resistors. The PWR_DWN and OE modes have an additional setting to determine timing (asynchronous or synchronous) with respect to the output signal. When PWR_DWN or OE modes are enables, CLKOUT is pulled LOW by a weak pull-down. The weak pull-down is easily overdriven by another active CLKOUT for applications that require multiple CLKOUTs on a single signal path. In addition, the PWR_DWN and OE modes can be programmed to occur synchronously or asynchronously with respect to the output signal. When the asynchronous setting is used, the powerdown or output three-state occurs immediately (allowing for logic delays) irrespective of position in the clock cycle. However, when the synchronous setting is used, the part waits for a falling edge at the output before Powerdown or Output Enable is initiated, thus preventing output glitches. Controlled rise and fall times, unique output driver circuits, and innovative circuit layout techniques enable the CY2039 CY2039 to have low jitter and accurate outputs making it suitable for most PC, networking and consumer applications Crystal Oscillator Tuning Circuit The CY2039 CY2039 contains an unique tuning circuit to fine-tune the output frequency of the device. The tuning circuit consists of an array of eleven load capacitors on both sides of the oscillator drive inverter. The capacitor load values are EPROM programmable and can be increased in small increments. As the capacitor load is increased the circuit is fine-tuned to a lower frequency. The tuning increments are shown in the table on page 3. Please refer to the "7C80320 7C80320 Programming Specification" for further details. EPROM Configuration Block The following table summarizes the features which are configurable by EPROM. Please refer to the "7C80320 7C80320 Programming Specification" for further details. The specification can be obtained from your local Cypress representative. Die Pad Summary Name Die Pad Description VDD 1,2 Voltage supply. VSS 8,9 Ground. XD 4 Crystal connection XX 3 No Connect. (For customers not bonding XD or XG pad to external pins, an alternative bonding option would be shorting this pad to XD pad.) XG 6 Crystal connection PWR_DWN / OE 7 EPROM programmable power down or output enable pad. Weak pull up. CLKOUT 11 Clock output. Weak pull down. NC 5,10 No Connect. (Do not bond to these pads) 2 CY2039 CY2039 Device Functionality: Output Frequencies Symbol Condition Max. Unit VDD = 4.55.5V Output frequency Min. 1.25 30 MHz VDD = 3.03.6V Fo Description 1.25 30 MHz Crystal Oscillator Tuning Circuit Rf External Crystal C6 C5 C4 C3 C2 C1 C0 Cgo Cdo C7 C8 C9 C10 C = LOAD CAPACITOR Symbol Rf Description Min. 0.5 1.0 Feedback resistor, VDD = 4.55.5V Feedback resistor, VDD = 3.03.6V Typ. 2 4 Max. 3.5 9.0 Unit M M Capacitors have ± 20% Tolerance Cg Gate capacitor 13 pF Cd Drain Capacitor 9 pF C0 Series Cap 0.27 pF C1 Series Cap 0.52 pF C2 Series Cap 1.00 pF C3 Series Cap 0.7 pF C4 Series Cap 1.4 pF C5 Series Cap 2.6 pF C6 Series Cap 5.0 pF C7 Series Cap 0.45 pF C8 Series Cap 0.85 pF C9 Series Cap 1.7 pF C10 Series Cap 3.3 pF 3 CY2039 CY2039 Absolute Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature (Non-Condensing) . 55°C to +150°C Supply Voltage .0.5 to +7.0V Static Discharge Voltage . >2000V (per MIL-STD-883 MIL-STD-883, Method 3015) Junction Temperature . 40°C to +100°C Input Voltage .0.5V to VDD+0.5V Operating Conditions Parameter Description Min. Max. Unit V V VDD Supply Voltage (3.3V) Supply Voltage (5.0V) 3.0 4.5 3.6 5.5 TAJ  Operating Temperature, Junction 40 +100 °C CTTL Max. Capacitive Load on outputs for TTL levels 25 pF CCMOS Max. Capacitive Load on outputs for CMOS levels XREF Reference Frequency, input crystal 25 pF 30 10 MHz Electrical Characteristics Over the Operating Range (Part was characterized in a 20-pin SOIC package with external crystal, Electrical Characteristics may change with other package types) Parameter Description Test Conditions VIL Low-level Input Voltage VDD = 4.55.5V VDD = 3.03.6V Min. Typ. Max. VIH High-level Input Voltage VDD = 4.55.5V VDD = 3.03.6V VOL Low-level Output Voltage VDD = 4.55.5V, IOL= 16 mA VDD = 3.03.6V, IOL= 8 mA VOHCMOS High-level Output Voltage, CMOS levels VDD = 4.55.5V, IOH= 16 mA VDD = 3.03.6V, IOH= 8 mA VDD0.4 VDD0.4 V V VOHTTL High-level Output Voltage, TTL levels VDD = 4.55.5V, IOH= 8 mA 2.4 V 0.8 0.2VDD Unit V V V V 2.0 0.7VDD 0.4 0.4 V V IIL Input Low Current VIN = 0V 10 µA IIH Input High Current VIN = VDD 5 µA IDD Power Supply Current, Unloaded VDD = 4.55.5V VDD = 3.03.6V 45 25 mA mA IDDS Stand-by current VDD = 3.03.6V 10 50 µA RUP Input Pull-Up Resistor VDD = 4.55.5V, VIN = 0V VDD = 4.55.5V, VIN = 0.7VDD 3.0 100 8.0 200 M k IOE_CLKOUT CLKOUT Pulldown current VDD = 5.0 1.1 50 20 Note: 2. This product is sold in die form so operating conditions are specified for the die, or junction temperature 4 µA CY2039 CY2039 Output Clock Switching Characteristics Over the Operating Range Para meter Description Test Conditions Min. Typ. Max. Unit t1w Output Duty Cycle at 1.4V, VDD = 4.55.5V t1w = t1A ÷ t1B 130 MHz, CL < 25 pF (TTL output) 45 55 % t1x Output Duty Cycle at VDD/2, VDD = 4.55.5V t1x = t1A ÷ t1B 130 MHz, CL < 25 pF (CMOS output) 45 55 % t1y Output Duty Cycle at VDD/2, VDD = 3.03.6V t1y = t1A ÷ t1B 130 MHz, CL < 25 pF (CMOS output) 45 55 % t2t Output Clock Rise time Between 0.8 2.0V, VDD = 4.5V5.5V 2.0 ns t2c Output Clock Rise time Between 0.2VDD0.8VDD, VDD = 4.5V5.5V Between 0.2VDD0.8VDD, VDD = 3.0V3.6V 4.0 4.0 ns ns t3t Output Clock Fall time Between 2.0V0.8V, VDD = 4.5V5.5V 2.0 ns t3c Output Clock Fall time Between 0.8VDD0.2VDD, VDD = 4.5V5.5V Between 0.8VDD0.2VDD, VDD = 3.0V3.6V 4.0 4.0 ns ns t4 Start-Up Time Out of Power-Down PWR_DWN pin LOW to output HIGH 5 10 ms t5a Power Down Delay Time From PWR_DWN pin at or below VIL to output LOW (synchronous setting) (T = period of output clk) T/2 T+10 ns t5b Power Down Delay Time From PWR_DWN pin at or below VIL to output LOW (asynchronous setting) 10 15 ns t6 Power Up Time From power on at or above VDD-10 VDD-10% to within frequency specification. 5 10 ms t7a Output Disable Time (synchronous setting) From OE pin at or below VIL to output Hi-Z (T = period of output clk) T/2 T + 10 ns t7b Output Disable Time (asynchronous setting) From OE pin at or below VIL to output Hi-Z 10 15 ns t8 Output Enable Time OE pin LOW to HIGH (T = period of output clk) 1.5T + 25 ns t9 RMS Period Jitter Over 6000 cycles 25 ps t10 Cycle to Cycle Jitter Over 6000 cycles 100 ps Switching Waveforms Duty Cycle Timing (t1w, t1x, t1y, t1z) OUTPUT t1A t1B Note: 3. Oscillator start time cannot be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70. 5 CY2039 CY2039 Switching Waveforms (continued) Output Rise/Fall Time VDD OUTPUT 0V t2 t3 Power Down Timing (synchronous and asynchronous modes) POWER DOWN VDD VIH VIL 0V t4 CLKOUT (synchronous) T t5a 1/f CLKOUT (asynchronous) t5b 1/f Power Up Timing VDD POWER UP 0V VDD10% t6 min. 2 ns CLKOUT 1/f Output Enable Timing (synchronous and asynchronous modes) VDD OUTPUT ENABLE VIH VIL 0V T CLKOUT (synchronous) High Impedance t8 t7a CLKOUT (asynchronous) High Impedance t7b t8 Notes: 4. In synchronous mode the powerdown or output 3-state is not initiated until the next falling edge of the output clock. 5. In asynchronous mode the powerdown or output 3-state occurs within 25ns irrespective of position in the ouput clock cycle. 6 CY2039 CY2039 Ordering Information Ordering Code Type Operating Range CY2039WAF CY2039WAF Wafer Industrial Die Size Dimensions x by y 1497x1105 microns Wafer Thickness 14 ±0.5 mils Document #: 38-01135-* © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.