NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Type | Ordering |
| CY14B101K | Cypress Semiconductor | 1 Mbit (128K x 8) nvSRAM With Real Time Clock |
24 pages, |
Original |  |
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| CY14B101K | Cypress Semiconductor | 1 Mbit (128K x 8) nvSRAM With Real Time Clock |
24 pages, |
Original | |
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| CY14B101K | Cypress Semiconductor | 1 Mbit (128K x 8) nvSRAM With Real-Time Clock |
24 pages, |
Original | |
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| CY14B101K-SP25XC | Cypress Semiconductor | 1 Mbit (128K x 8) nvSRAM With Real Time Clock |
24 pages, |
Original | |
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| CY14B101K-SP25XC | Cypress Semiconductor | 1 Mbit (128K x 8) nvSRAM With Real Time Clock |
28 pages, |
Original | |
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| CY14B101K-SP25XCT | Cypress Semiconductor | 1 Mbit (128K x 8) nvSRAM With Real Time Clock |
24 pages, |
Original | |
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| CY14B101K-SP25XCT | Cypress Semiconductor | 1 Mbit (128K x 8) nvSRAM With Real-Time Clock |
24 pages, |
Original | |
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| CY14B101K-SP25XCT | Cypress Semiconductor | 1 Mbit (128K x 8) nvSRAM With Real Time Clock |
28 pages, |
Original | |
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| CY14B101K-SP25XI | Cypress Semiconductor | 1 Mbit (128K x 8) nvSRAM With Real Time Clock |
28 pages, |
Original | |
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| CY14B101K-SP25XIT | Cypress Semiconductor | 1 Mbit (128K x 8) nvSRAM With Real Time Clock |
28 pages, |
Original | |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: CY14B101Q1 CY14B101Q2 CY14B101Q3 1 Mbit (128K x 8) Serial SPI nvSRAM Features 1 , Functional Overview The Cypress < > combines a 1 Mbit nonvolatile static RAM , Instruction Software Block Protection for 1/4,1/2, or entire Array CY14B101Q1 CY14B101Q2 CY14B101Q3 , 408-943-2600 Revised April 12, 2010 [+] Feedback CY14B101Q1 CY14B101Q2 CY14B101Q3 Contents Features , ] Feedback CY14B101Q1 CY14B101Q2 CY14B101Q3 Pinouts Figure 1. Pin Diagram - 8-Pin DFN[1, 2, 3 ... | Original |
24 pages, |
MOSI 0x00000 Serial NVSRAM CY14B101Q2 OF SPI protocol CY14B101Q1 CY14B101Q3 CY14B101Q1 abstract |
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| Abstract: ) Operating Voltage Range CY14B101L-SZ25XCT 51-85127 2.7V to 3.6V 32-pin SOIC CY14B101L-SZ25XC , CY14B101L-SP25XIT 51-85061 3.0V to 3.6V 48-pin SSOP CY14B101L-SP25XI 51-85061 3.0V to 3.6V , CY14B101L-SP35XCT 51-85061 2.7V to 3.6V 48-pin SSOP CY14B101L-SP35XC 51-85061 2.7V to 3.6V 48-pin SSOP CY14B101L-SZ35XIT 51-85127 2.7V to 3.6V 32-pin SOIC CY14B101L-SZ35XI , CY14B101L-SP45XCT 51-85061 2.7V to 3.6V 48-pin SSOP CY14B101L-SP45XC 51-85061 2.7V to 3.6V ... | Original |
21 pages, |
STK14CA8 CY14B101LL-SP25XC CY14B101L-SZ25XIT CY14B101L-SZ25XC CY14B101L CY14B101L abstract |
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| Abstract: operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B101K. During , primary power is removed. However, the battery is not recharged at any time by the CY14B101K. The , CY14B101K 1 Mbit (128K x 8) nvSRAM With Real Time Clock Features 25 ns[1], 35 ns , compliant) ig ns Functional Description es The Cypress CY14B101K combines a 1 Mbit , [+] Feedback CY14B101K Contents fo r N ew D es ig ns Interrupts ... | Original |
29 pages, |
STK17TA8 CY14B101K CY14B101K abstract |
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| Abstract: Sequence (WRITE) Table 6 summarizes all the protection features provided in the CY14B101P. The write , CY14B101P 1 Mbit (128K x 8) Serial SPI nvSRAM with Real Time Clock Features 1 , Cypress CY14B101P combines a 1 Mbit nonvolatile static RAM with full featured real time clock in a , Revised March 15, 2010 [+] Feedback CY14B101P Contents , . 34 Page 2 of 34 [+] Feedback CY14B101P Pinouts Figure 1. Pin Diagram - 16-Pin SOIC ... | Original |
34 pages, |
CY14B101P 16-SOIC 101P CY14B101P-SFXI CY14B101P abstract |
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| Abstract: CY14B101LA-SP25XI 51-85061 48-pin SSOP CY14B101LA-SZ25XIT 51-85127 32-pin SOIC CY14B101LA-SZ25XI 51-85127 32-pin SOIC CY14B101NA-ZS25XIT 51-85087 44-pin TSOP II CY14B101NA-ZS25XI , CY14B101LA-SP45XI 51-85061 48-pin SSOP CY14B101LA-SZ45XIT 51-85127 32-pin SOIC CY14B101LA-SZ45XI , Diagram CY14B101LA-ZS20XIT 51-85087 44-pin TSOP II CY14B101LA-ZS20XI 20 Ordering Code 51-85087 44-pin TSOP II Package Type CY14B101NA-ZS20XIT 44-pin TSOP II CY14B101LA-ZS25XIT ... | Original |
25 pages, |
CY14B101NA_ZS45XI CY14B101NA-ZS25XI CY14B101LA-ZS45XIT CY14B101LA CY14B101NA 8/64K CY14B101LA abstract |
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| Abstract: latch is not set, HSB is not driven LOW by the CY14B101KA/CY14B101MA. But any SRAM read and write , CY14B101KA/CY14B101MA 1 Mbit (128K x 8/64K 8/64K x 16) nvSRAM with Real Time Clock Features , 95134-1709 ยท 408-943-2600 Revised April 12, 2010 [+] Feedback CY14B101KA/CY14B101MA Contents , .32 Page 2 of 32 [+] Feedback CY14B101KA/CY14B101MA Pinouts Figure 1. Pin Diagram - , Rev. *F Page 3 of 32 [+] Feedback CY14B101KA/CY14B101MA Pin Definitions (continued) Pin ... | Original |
32 pages, |
CY14B101KA/CY14B101MA 8/64K CY14B101KA CY14B101MA CY14B101KA/CY14B101MA abstract |
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| Abstract: Table 6 summarizes all the protection features provided in the CY14B101P. Table 6. Write Protection , Hi-Z SO AutoStore Disable (ASDISB) AutoStore is enabled by default in CY14B101P. The AutoStore Disable instruction disables the AutoStore on CY14B101P. This setting is not nonvolatile and needs to be , AutoStore on CY14B101P. This setting is not nonvolatile and needs to be followed by a STORE sequence if , PRELIMINARY CY14B101P 1 Mbit (128K x 8) Serial SPI nvSRAM with Real Time Clock Features ... | Original |
32 pages, |
CY14B101P 16-SOIC 101P CY14B101P-SFXI CY14B101P abstract |
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| Abstract: CY14B101NA-BA20XCT 51-85128 48-ball FBGA CY14B101NA-BA20XC 51-85128 48-ball FBGA CY14B101LA-ZS20XIT , CY14B101LA-SP25XCT 51-85061 48-pin SSOP CY14B101LA-SP25XC 51-85061 48-pin SSOP CY14B101LA-SZ25XCT , CY14B101LA-SP25XI 51-85061 48-pin SSOP CY14B101LA-SZ25XIT 51-85127 32-pin SOIC CY14B101LA-SZ25XI , CY14B101LA-SP45XC 51-85061 48-pin SSOP CY14B101LA-SZ45XCT 51-85127 32-pin SOIC CY14B101LA-SZ45XC , CY14B101LA-ZS20XCT 51-85087 44-pin TSOP II CY14B101LA-ZS20XC 51-85087 Operating Range 44-pin TSOP ... | Original |
25 pages, |
CY14B101LA-BA25XC CY14B101LA CY14B101NA 8/64K CY14B101LA abstract |
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| Abstract: CY14B101L-SZ25XCT 51-85127 32-pin SOIC CY14B101L-SZ25XC 51-85127 32-pin SOIC CY14B101L-SP25XCT 51-85061 48-pin SSOP CY14B101L-SP25XC 51-85061 48-pin SSOP CY14B101L-SZ25XIT 51-85127 32-pin SOIC CY14B101L-SZ25XI 51-85127 51-85061 48-pin SSOP CY14B101L-SP25XI 51-85061 Commercial 32-pin SOIC CY14B101L-SP25XIT 35 Operating Range 48-pin SSOP CY14B101L-SZ35XCT , CY14B101L-SP45XC 51-85061 48-pin SSOP CY14B101L-SZ45XIT 51-85127 32-pin SOIC CY14B101L-SZ45XI ... | Original |
18 pages, |
STK14CA8 CY14B101L-SZ25XCT CY14B101L-SZ25XC CY14B101L-SP25XCT CY14B101L CY14B101L abstract |
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| Abstract: feature of QuantumTrap technology and is enabled by default on the CY14B101KA/CY14B101MA. The , PRELIMINARY CY14B101KA/CY14B101MA 1 Mbit (128K x 8/64K 8/64K x 16) nvSRAM with Real Time Clock , (CY14B101KA) or 64K x 16 (CY14B101MA) Hands off automatic STORE on power down with only a small capacitor , The Cypress CY14B101KA/CY14B101MA combines a 1-Mbit nonvolatile static RAM with a full featured real , [+] Feedback CY14B101KA/CY14B101MA PRELIMINARY Pinouts Figure 1. Pin Diagram - 44-Pin ... | Original |
29 pages, |
CY14B101KA/CY14B101MA 8/64K CY14B101KA/CY14B101MA abstract |
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