CXP845P60 CXP84548 E96825-PS SPC700 CXP845F60 00FEH 74HC04 00F9H 00MTZ CSA12 - Datasheet Archive

 

CMOS 8-bit Single Chip Microcomputer Description The CXP845P60 is a CMOS 8-bit microcomputer integrating on a single chip an A/D

 

CXP845P60 CXP845P60 CMOS 8-bit Single Chip Microcomputer Description The CXP845P60 CXP845P60 is a CMOS 8-bit microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time base timer, capture timer/counter, PWM output and the like besides the basic configurations of 8-bit CPU, PROM, RAM and I/O port. The CXP845P60 CXP845P60 also provides a sleep/stop functions that enable to execute the power-on reset function or lower the power consumption. The CXP845P60 CXP845P60 is the PROM-incorporated version of the CXP84548 CXP84548 with built-in mask ROM. This provides the additional feature of being able to write directly into the program. Thus, it is most suitable for evaluation use during system development and for small-quantity production. 80 pin QFP (Plastic) Features · A wide instruction set (213 instructions) which covers various types of data - 16-bit arithmetic/multiplication and division/Boolean bit operation instructions · Minimum instruction cycle 143ns at 28MHz operation (4.5 to 5.5V) 200ns at 20kHz operation (3.0 to 5.5V) · Incorporated PROM capacity 60K bytes · Incorporated RAM capacity 1472 bytes · Peripheral functions - A/D converter 8 bits, 8 channels, successive approximation method (Conversion time of 1.93µs at 28MHz, 2.7µs at 20MHz) - Serial interface Incorporated 8-bit, 8-stage FIFO (Auto transfer for 1 to 8 bytes, latch output function, MSB/LSB first selectable), 1 channel 8-bit clock sync type, 1 channel - Timer 8-bit timer 8-bit timer/counter 19-bit time base timer 16-bit capture time/counter - PWM output 8 bits, 2 channels · Interruption 14 factors, 14 vectors, multi-interruption possible · Standby mode Sleep/stop · Package 80-pin plastic QFP Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. ­1­ E96825-PS E96825-PS ­2­ TO CINT EC1 16 BIT CAPTURE TIMER/COUNTER 2 8 BIT TIMER 1 8 BIT TIMER/COUNTER 0 EC0 FIFO SERIAL INTERFACE UNIT 1 SERIAL INTERFACE UNIT 0 SI1 SO1 SCK1 CS0 SI0 SO0 SCK0 LAT0 8 BIT PWM GENERATOR 1 PWM1 A/D CONVERTER AVss 8 BIT PWM GENERATOR 0 8 AVREF PWM0 AN0 to AN7 2 2 INT0 INT1 INT2 INT3 INTERRUPT CONTROLLER Block Diagram PRESCALER/ TIME BASE TIMER PROM 60K BYTES SPC700 SPC700 CPU CORE EXTAL XTAL RST VDD Vss RAM 1472 BYTES CLOCK GENERATOR/ SYSTEM CONTROL PE0 to PE3 PD0 to PD7 PC0 to PC7 PB0 to PB7 PA0 to PA7 8 8 8 PI0 to PI7 PH0 to PH7 PG0 to PG7 PF0 to PF7 4 8 PE4 to PE7 4 8 8 8 8 CXP845P60 CXP845P60 PORT I PORT H PORT G PORT F PORT E PORT D PORT C PORT B PORT A NMI CXP845P60 CXP845P60 PI5 PI7 PI6 PG0 PG1 PG3 PG2 VDD Vpp PG5 PG4 PG6 PF0 PG7 PF1 PF2 Pin Assignment (Top View) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PF3 1 64 PI4 PF4 2 63 PI3/INT3 PF5 3 62 PI2/INT2 PF6 4 61 PI1/INT1 PF7 5 60 PI0/INT0 PD0 6 59 PE5/TO/PWM1 PD1 7 58 PE4/PWM0 PD2 8 57 PE3/NMI PD3 9 56 PE2/CINT PD4 10 55 PE1/EC1 PD5 11 54 PE0/EC0 PD6 12 53 PB7/SO1 PD7 13 52 PB6/SI1 PC0 14 51 PB5/SCK1 PC1 15 50 PB4/SO0 PC2 16 49 PB3/SI0 PC3 17 48 PB2/SCK0 PC4 18 47 PB1/CS0 PC5 19 46 PB0/LAT0 PC6 20 45 PA7/AN7 PC7 21 44 PA6/AN6 PH0 22 43 PA5/AN5 PH1 23 42 PA4/AN4 PH2 24 41 PA3/AN3 PA2/AN2 PA0/AN0 PA1/AN1 AVREF AVSS PE6 PE7 VSS XTAL RST EXTAL PH7 PH6 PH4 PH5 PH3 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Note) Vpp (Pin 73) is left open. (Internally connected to VDD.) However, this pin is used for the Flash EEPROM-incorporated version (CXP845F60 CXP845F60). ­3­ CXP845P60 CXP845P60 Pin Description Symbol I/O PA0/AN0 to PA7/AN7 I/O/Analog input PB0/LAT0 I/O/Input PB2/SCK0 I/O/I/O PB3/SI0 I/O/Input PB4/SO0 I/O/Output PB5/SCK1 I/O/I/O PB6/SI1 I/O/Input PB7/SO1 (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of the pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) I/O/Output PB1/CS0 Description I/O/Output Analog inputs to A/D converter. (8 pins) Latch output for serial interface (CH0). (Port B) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1). I/O (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Can drive 12mA sync current. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) PD0 to PD7 I/O (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) PE0/EC0 Input/Input PE1/EC1 Input/Input PE2/CINT Input/Input PE3/NMI Input/Input PE4/PWM0 Output/Output PE5/TO/ PWM1 Output/Output/ Output PE6 Output PE7 Output PC0 to PC7 PF0 to PF7 I/O External event inputs for timer/counter. (2 pins) (Port E) 8-bit port. Lower 4 bits are for inputs; upper 4 bits are for outputs. (8 pins) Capture trigger input. Non-maskable interruption request input. 8-bit PWM0 output. Rectangular wave output for 16-bit timer/ counter and 8-bit PWM1 output. (Port F) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) ­4­ CXP845P60 CXP845P60 Symbol PG0 to PG7 PH0 to PH7 I/O I/O (Port G) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) I/O (Port H) 8-bit I/O port. I/O and standby release input function can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) PI0/INT0 to PI3/INT3 I/O/Input PI4 to PI7 I/O EXTAL Input XTAL Output RST I/O (Port I) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) External interruption request inputs. (4 pins) Connects a crystal for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. System reset for active at Low level. This pin is I/O pin, and outputs Low level at the power on with the power-on reset function executed. Positive power supply for incorporated PROM writing. Leave this pin open (internally connected to VDD). This is used for the Flash EEPROM-incorporated version (CXP845F60 CXP845F60). Vpp AVREF Description Input Reference voltage input for A/D converter. AVss A/D converter GND. VDD Positive power supply. Vss GND ­5­ CXP845P60 CXP845P60 Input/Output Circuit Formats for Pins Pin When reset Circuit format Port A Pull-up resistor "0" when reset Port A data PA0/AN0 to PA7/AN7 Port A direction IP "0" when direction Input protection circuit Hi-Z Data bus RD (Port A) Port A function selection Input multiplexer "0" when reset A/D converter 8 pins Pull-up transistor Approx. 100k (VDD = 4.5 to 5.5V) Approx. 300k (VDD = 3.0 to 3.6V) Port B Pull-up resistor "0" when reset LAT0 Latch output enable Port B data PB0/LAT0 IP Hi-Z Port B direction "0" when reset Data bus RD (Port B) Pull-up transistor Approx. 100k (VDD = 4.5 to 5.5V) Approx. 300k (VDD = 3.0 to 3.6V) 1 pin Port B Pull-up resistor "0" when reset Port B data PB1/CS0 PB3/SI0 PB6/SI1 Port B direction IP "0" when reset Schmitt input Data bus RD (Port B) 3 pins CS0 SI0 SI1 Pull-up transistor Approx. 100k (VDD = 4.5 to 5.5V) Approx. 300k (VDD = 3.0 to 3.6V) ­6­ Hi-Z CXP845P60 CXP845P60 Pin When reset Circuit format Port B Pull-up resistor "0" when reset SCK OUT Serial clock output enable Port B function selection "0" when reset PB2/SCK0 PB5/SCK1 IP Port B data Hi-Z Port B direction "0" when reset Schmitt input Data bus RD (Port B) SCK0, SCK1 in 2 pins Pull-up transistor Approx. 100k (VDD = 4.5 to 5.5V) Approx. 300k (VDD = 3.0 to 3.6V) Port B Pull-up resistor SO Serial data output enable Port B function selection "0" when reset PB4/SO0 PB7/SO1 IP Port B data Hi-Z Port B direction "0" when reset Data bus RD (Port B) Pull-up transistor Approx. 100k (VDD = 4.5 to 5.5V) Approx. 300k (VDD = 3.0 to 3.6V) 2 pins Port C 2 Pull-up resistor "0" when reset Port C data PC0 to PC7 1 Port C direction IP "0" when reset Data bus RD (Port C) 1 Large current drive (12mA: VDD = 4.5 to 5.5V) ( 5mA: VDD = 3.0 to 3.6V) 2 Pull-up transistor Approx. 100k (VDD = 4.5 to 5.5V) Approx. 300k (VDD = 3.0 to 3.6V) 8 pins ­7­ Hi-Z CXP845P60 CXP845P60 Pin When reset Circuit format Port E PE0/EC0 PE1/EC1 PE2/CINT PE3/NMI Schmitt input EC0, EC1 CINT, NMI IP Hi-Z Data bus RD (Port E) 4 pins Port E PWM0 Port E function selection "0" when reset PE4/PWM0 High level Port E data "1" when reset Data bus 1 pin RD (Port E) Port E Internal reset signal Port E data PE5/TO/ PWM1 00 "1" when reset TO PWM1 01 1x MPX ( Port E function selection (upper) Port E function selection (lower) High level with resistor of pull-up transistor ON for reset Pull-up transistor Approx. 150k (VDD = 4.5 to 5.5V) Approx. 400k (VDD = 3.0 to 3.6V) "00" when reset TO output enable 1 pin Port E Port E data PE6, PE7 "0" when reset Low level Data bus 2 pins RD (Port E) ­8­ ) CXP845P60 CXP845P60 Pin When reset Circuit format Port D Port F Port G PD0 to PD7 PF0 to PF7 PG0 to PG7 PI4 to PI7 Pull-up resistor "0" when reset Ports D, F, G, I data Port I Ports D, F, G, I direction IP Hi-Z "0" when reset Data bus RD Pull-up transistor Approx. 100k (VDD = 4.5 to 5.5V) Approx. 300k (VDD = 3.0 to 3.6V) 28 pins Port H Pull-up resistor "0" when reset Port H data PH0 to PH7 Port H direction IP Hi-Z "0" when reset Data bus RD (Port H) Edge detection Standby release Pull-up transistor Approx. 100k (VDD = 4.5 to 5.5V) Approx. 300k (VDD = 3.0 to 3.6V) 8 pins Port I Pull-up resistor "0" when reset Port I data PI0/INT0 to PI3/INT3 Port I direction IP "0" when reset Schmitt input Data bus RD INT0 INT1 INT2 INT3 Pull-up transistor Approx. 100k (VDD = 4.5 to 5.5V) Approx. 300k (VDD = 3.0 to 3.6V) 4 pins ­9­ Hi-Z CXP845P60 CXP845P60 Pin EXTAL XTAL 2 pins When reset Circuit format · Diagram shows the circuit composition during oscillation. EXTAL IP IP · Feedback resistor is removed during stop mode and XTAL becomes High level. Oscillation XTAL Pull-up resistor RST Schmitt input Low level IP From power-on reset circuit 1 pin ­ 10 ­ CXP845P60 CXP845P60 Absolute Maximum Ratings (Vss = 0V reference) Item Symbol Unit VDD ­0.3 to +7.0 V AVSS Supply voltage Ratings Remarks V Input voltage VIN ­0.3 to +0.3 ­0.3 to +7.01 Output voltage VOUT ­0.3 to +7.01 V High level output current IOH ­5 mA Output (value per pin) High level total output current IOH ­50 mA Total for all output pins IOL 15 mA IOLC 20 mA All pins excluding large current outputs (value per pin) Large current outputs (value per pin2) Low level total output current IOL 100 mA Total for all output pins Operating temperature Topr ­20 to +75 °C Storage temperature Tstg ­55 to +150 °C Allowable power dissipation PD 600 mW Low level output current V 1 VIN and VOUT must not exceed VDD + 0.3V. 2 The large current drive transistor is the N-ch transistor of Port C (PC). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. Recommended Operating Conditions Item 5.5 5.5 0.7VDD VDD V VIHS 0.8VDD VDD V 0.9VDD VDD + 0.3 V Hysteresis input3 EXTAL4 VIL 0 0.3VDD V 2 VILS 0 0.2VDD V VILEX 1 2 3 4 3.5 (2.7) VIHEX Operating temperature 5.5 VIH Low level input voltage Max. 2.0 High level input voltage Min. 4.5 (3.0) Supply voltage1 Symbol (Vss = 0V reference) ­0.3 0.1VDD V Topr ­20 +75 °C VDD Unit Remarks Guaranteed operation range for 1/2 and 1/4 frequency dividing modes V Guaranteed operation range for 1/16 frequency dividing and sleep modes Guaranteed data hold range during stop mode 2 Hysteresis input3 EXTAL4 Specifies values in parenthesis for 1 to 20MHz system clock operation. Normal input ports (PA, PB0, PB4, PB7, PC, PE0 to PE3, PD, PF to PH, PI4 to PI7) RST, CINT, CS0, SCK0, SCK1, EC0, EC1, SI0, SI1, NMI, INT0, INT1, INT2, INT3 Specifies only during external clock input. ­ 11 ­ CXP845P60 CXP845P60 Electrical Characteristics DC Characteristics (VDD 4.5 to 5.5V) Item High level output voltage Low level output voltage Symbol Pins PA to PD, PE4 to PE7, PF to PI, RST (only VOL) Typ. Max. Unit IILR RST IIL PA to PD1 PF to PI1 IIZ PA to PD1 PF to PI1 PE0 to PE3 V VDD = 4.5V, IOH = ­1.2mA 3.5 V VDD = 4.5V, IOL = 1.8mA 0.4 V 0.6 V VDD = 4.5V, IOL = 12.0mA 1.5 V 0.1 25 µA VDD = 5.5V, VIL = 0.4V ­0.1 ­25 µA ­1.5 ­400 µA ­50 µA VDD = 5.5V, VIL = 4.0V VDD = 4.5V, VIL = 4.0V ­2.78 µA VDD = 5.5V, VI = 0, 5.5V ±10 µA 35 64 mA 2.5 10 mA 30 µA 20 pF For 1/2 frequency dividing mode IDD1 VDD = 5.5V, 28MHz crystal oscillation (C1 = C2 = 1pF) IDD2 Sleep mode IDDS1 IDDS2 4.0 VDD = 5.5V, VIH = 5.5V EXTAL IILE Supply current 2 Min. VDD = 4.5V, IOL = 3.6mA VOL IIHE I/O leakage current Conditions VDD = 4.5V, IOH = ­0.5mA VOH PC Input current (Ta = ­20 to +75°C, Vss = 0V reference) VDD VDD = 5.5V, 28MHz crystal oscillation (C1 = C2 = 1pF) Stop mode IDDS3 Input capacity CIN VDD = 5.5V, termination of 28MHz crystal oscillation PA to PD, PE0 to PE3, PF to PI, EXTAL, RST Clock 1MHz 0V for all pins excluding measured pins 10 1 For PA to PD and PF to PI pins, specifies the input current when pull-up resistance is selected; leakage current when no resistance is selected. 2 When all pins are open. ­ 12 ­ CXP845P60 CXP845P60 DC Characteristics (VDD = 3.0 to 3.6V) Item High level output voltage Low level output voltage Symbol VOH VOL Pins IIHE Input current IILR RST PA to PD1 PF to PI1 IIZ PA to PD1 PF to PI1 PE0 to PE3 Unit 2.7 V 2.3 V 0.3 V 0.5 V 1.0 VDD = 3.0V, IOL = 5mA V 0.05 15 µA VDD = 3.6V, VIL = 0.3V ­0.05 ­15 µA ­0.7 ­200 µA ­30 µA VDD = 3.6V, VIL = 0.3V VDD = 3.0V, VIL = 2.7V ­1.0 µA VDD = 3.6V, VI = 0, 3.6V VDD = 3.6V, 20MHz crystal oscillation (C1 = C2 = 10pF) IDD2 ±5 µA 14.5 30 mA 0.85 4.0 mA 5 µA Sleep mode IDDS1 VDD IDDS2 Typ. Max. For 1/2 frequency dividing mode IDD1 Supply current2 Min. VDD = 3.6V, VIH = 3.6V EXTAL IIL I/O leakage current Conditions VDD = 3.0V, IOH = ­0.15mA PA to PD, VDD = 3.0V, IOH = ­0.5mA PE4 to PE7, PF to PI, VDD = 3.0V, IOL = 1.2mA RST (only VOL) VDD = 3.0V, IOL = 1.6mA PC IILE (Ta = ­20 to +75°C, VSS = 0V reference) VDD = 3.6V, 20MHz crystal oscillation (C1 = C2 = 10pF) Stop mode IDDS3 VDD = 3.6V, termination of 20MHz crystal oscillation 1 For PA to PD and PF to PI pins, specifies the input current when pull-up resistance is selected; leakage current when no resistance is selected. 2 When all pins are open. ­ 13 ­ CXP845P60 CXP845P60 AC Characteristics (Ta = ­20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference) (1) Clock timing Item Symbol Pin Conditions Min. System clock frequency fC System clock input pulse width tXL, tXH EXTAL Fig. 3 EC0 EC1 20 Fig. 1, Fig. 2 External clock drive EC0 EC1 28 1 Fig. 1, Fig. 2 VDD = 4.5 to 5.5V External clock drive EXTAL 1 VDD = 4.5 to 5.5V XTAL Fig. 1, Fig. 2 EXTAL Typ. Max. Unit Fig. 3 tCR, tCF tEH, tEL tER, tEF System clock input rise time, fall time Event count input clock pulse width Event count input clock rise time, fall time MHz 15.6 ns 23 100 tsys + 501 ns ns 20 ns 1 tsys indicates the three values according to the contents of the clock control register (CLC: 00FEH 00FEH) upper 2 bits (CPU clock selection). tsys (ns) = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Fig. 1. Clock timing 1/fc VDD ­ 0.4V EXTAL 0.4V tXH tCF tXL tCR Fig. 2. Clock applied conditions Crystal oscillation Ceramic oscillation EXTAL External clock EXTAL XTAL C1 C2 XTAL 74HC04 74HC04 Fig. 3. Event count clock timing 0.8VDD EC0 EC1 0.2VDD tEH tTH tEF tTF ­ 14 ­ tEL tTL tER tTR CXP845P60 CXP845P60 (Ta = ­20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) (2) Serial transfer (CH0) Item Symbol Pin Condition Min. Max. Unit CS0 SCK0 delay time tDCSK SCK0 Chip select transfer mode (SCK0 = output mode) 1.5tsys + 100 ns CS0 SCK0 float delay time tDCSKF SCK0 Chip select transfer mode (SCK0 = output mode) 1.5tsys + 100 ns CS0 SO0 delay time tDCSO SO0 Chip select transfer mode 1.5tsys + 100 ns CS0 SO0 float delay time tDCSOF SO0 Chip select transfer mode 1.5tsys + 100 ns CS0 High level width tWHCS CS0 Chip select transfer mode SCK0 cycle time tKCY SCK0 SCK0 High, Low level width tKH tKL SCK0 SI0 input setup time (for SCK0 ) tSIK SI0 SI0 input hold time (for SCK0 ) tKSI SI0 SCK0 SO0 delay time tKSO SO0 SCK0 LAT0 output delay time tLADLY LAT0 Latch output mode (SCK0 = output mode) LAT0 data pulse width tLAPLS LAT0 Latch output mode (SCK0 = output mode) tsys + 150 2tsys + 200 ns 8000/fc ns tsys + 90 ns 4000/fc ­ 25 ns SCK0 input mode 50 ns SCK0 output mode 100 ns tsys + 100 ns 50 ns Input mode Output mode Input mode Output mode SCK0 input mode SCK0 output mode ns tsys + 100 ns 50 ns tKCY tKCY + 50 ns tKCY ­ 10 tKCY + 50 ns SCK0 input mode SCK0 output mode Note 1) tsys indicates the three values according to the contents of the clock control register (CLC: 00FEH 00FEH) upper 2 bits (CPU clock selection). tsys (ns) = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL. ­ 15 ­ CXP845P60 CXP845P60 Serial transfer (CH0) Item (Ta = ­20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference) Symbol Pin Condition CS0 SCK0 delay time tDCSK SCK0 CS0 SCK0 float delay time Min. Max. Unit Chip select transfer mode (SCK0 = output mode) 1.5tsys + 200 ns tDCSKF SCK0 Chip select transfer mode (SCK0 = output mode) 1.5tsys + 200 ns CS0 SO0 delay time tDCSO SO0 Chip select transfer mode 1.5tsys + 200 ns CS0 SO0 float delay time tDCSOF SO0 Chip select transfer mode 1.5tsys + 200 ns CS0 High level width tWHCS CS0 Chip select transfer mode SCK0 cycle time tKCY SCK0 SCK0 High, Low level width tKH tKL SCK0 SI0 input setup time (for SCK0 ) tSIK SI0 SI0 input hold time (for SCK0 ) tKSI SI0 SCK0 SO0 delay time tKSO SO0 SCK0 LAT0 output delay time tLADLY LAT0 Latch output mode (SCK0 = output mode) LAT0 data pulse width tLAPLS LAT0 Latch output mode (SCK0 = output mode) ns tsys + 200 2tsys + 200 ns 8000/fc ns tsys + 80 ns 4000/fc ­ 50 ns SCK0 input mode 80 ns SCK0 output mode 150 ns tsys + 120 ns 70 ns Input mode Output mode Input mode Output mode SCK0 input mode SCK0 output mode tsys + 200 ns 80 ns tKCY tKCY + 100 ns tKCY ­ 10 tKCY + 100 ns SCK0 input mode SCK0 output mode Note 1) tsys indicates the three values according to the contents of the clock control register (CLC: 00FEH 00FEH) upper 2 bits (CPU clock selection). tsys (ns) = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF. ­ 16 ­ CXP845P60 CXP845P60 Fig. 4. Serial transfer CH0 timing tWHCS 0.8VDD CS0 0.2VDD tKCY tDCSK tKL tDCSKF tKH 0.8VDD 0.8VDD 0.8VDD SCK0 0.2VDD tSIK tKSI 0.8VDD Input data SI0 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 Output data 0.2VDD tLADLY 0.8VDD LAT0 ­ 17 ­ tLAPLS 0.8VDD CXP845P60 CXP845P60 (3) Serial transfer (CH1) Item (Ta = ­20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference) Symbol Pin tKCY SCK1 SCK1 High, Low level width tKH tKL SCK1 SI1 input setup time (for SCK1 ) tSIK SI1 SI1 input hold time (for SCK1 ) tKSI SI1 SCK1 SO1 delay time tKSO SO1 SCK1 cycle time Condition Min. Max. Unit 500 ns 8000/fc ns 200 ns 4000/fc ­ 25 ns SCK1 input mode 50 ns SCK1 output mode 100 ns SCK1 input mode 100 ns SCK1 output mode 50 ns Input mode Output mode Input mode Output mode SCK1 input mode 100 ns SCK1 output mode 50 ns Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL. (Ta = ­20 to +75°C, VDD = 3.0 to 3.6V, VSS = 0V reference) Item SCK1 cycle time Symbol tKCY Pin SCK1 SCK1 High, Low level width tKH tKL SCK1 SI1 input setup time (for SCK1 ) tSIK SI1 SI1 input hold time (for SCK1 ) tKSI SCK1 SO1 delay time tKSO SI1 SO1 Condition Min. Max. Unit 700 ns 8000/fc ns 300 ns 4000/fc ­ 50 ns SCK1 input mode 70 ns SCK1 output mode 150 ns SCK1 input mode 150 ns SCK1 output mode 70 ns Input mode Output mode Input mode Output mode SCK1 input mode 150 ns SCK1 output mode 80 ns Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF. ­ 18 ­ CXP845P60 CXP845P60 Fig. 5. Serial transfer CH1 timing tKCY tKL tKH 0.8VDD SCK1 0.2VDD tSIK tKSI 0.8VDD Input data SI1 0.2VDD tKSO 0.8VDD SO1 Output data 0.2VDD ­ 19 ­ CXP845P60 CXP845P60 (4) A/D converter characteristics (Ta = ­20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to VDD, Vss = AVSS = 0V reference) Item Symbol Pin Condition Min. Typ. Zero transition voltage Full-scale transition voltage VFT2 Conversion time Ta = 25°C VDD = AVREF = 5.0V VSS = AVSS = 0V VZT1 tCONV tSAMP Sampling time 10 70 mV 4970 5030 mV µs µs VDD ­ 0.5 Analog input voltage VDD V 0 AN0 to AN7 AVREF V 1.0 mA 10 µA 0.6 Operation mode IREF IREFS ­10 27/fADC3 6/fADC3 AVREF AVREF current LSB 4910 Reference input voltage VREF VIAN Bits ±4 Linearity error Unit 8 Resolution Max. AVREF Sleep mode Stop mode (Ta = ­20 to +75°C, VDD = 3.0 to 3.6V, AVREF = 2.7 to VDD, Vss = AVSS = 0V reference) Item Symbol Pin Condition Min. Typ. Zero transition voltage Full-scale transition voltage VFT2 Conversion time Ta = 25°C VDD = AVREF = 3.3V VSS = AVSS = 0V VZT1 tCONV tSAMP Sampling time 6.5 70 mV 3280.5 3345 mV Operation mode AVREF µs Sleep mode Stop mode VDD V 0 AN0 to AN7 IREF µs VDD ­ 0.3 Analog input voltage IREFS ­10 27/fADC3 6/fADC3 AVREF AVREF current LSB 3216 Reference input voltage VREF VIAN Bits ±5 Linearity error Unit 8 Resolution Max. AVREF V 0.7 mA 5 µA 0.4 Fig. 6. Definition of A/D converter terms 1 VZT: Value at which the digital conversion value changes from 00H to 01H and vice versa. 2 VFT: Value at which the digital conversion value changes from FEH to FFH and vice versa. 3 fADC indicates the values below due to the contents of bit 6 (CKS) of the A/D control register (ADC: 00F9H 00F9H). fADC = fc (CKS = "0"), fc/2 (CKS = "1") However, the selection for fADC = fc (CKS = "0") is limited in the clock range of fc = 1 to 14MHz (VDD 4.5 to 5.5V) and fc = 1 to 10MHz (VDD = 3.0 to 4.5V). Digital conversion value FFH FEH Linearity error 01H 00H VFT VZT Analog input ­ 20 ­ CXP845P60 CXP845P60 (4) Interruption, reset input (Ta = ­20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference) Item Symbol Pin External interruption High, Low level width tIH tIL INT0 INT1 INT2 INT3 NMI Reset input Low level width tRSL Condition RST Min. Max. Unit 1 µs 32/fc µs Fig 7. Interruption input timing tIH tIL 0.8VDD INT0 INT1 INT2 INT3 NMI (Specifies NMI only for the falling edge.) 0.2VDD tIL tIH 0.8VDD 0.2VDD Fig. 8. RST input timing tRSL RST 0.2VDD (Ta = ­20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference) (5) Power-on reset Item Symbol tR tOFF Power supply rise time Power supply cut-off time Pin VDD Condition Min. Fig. 9. Power-on reset 4.5V VDD 0.2V tR tOFF Turn the power on smoothly. ­ 21 ­ 50 ms 1 Repetitive power-on reset 0.2V Unit 0.05 Power-on reset Max. ms CXP845P60 CXP845P60 Appendix Fig. 10. SPC700 SPC700 Series recommended oscillation circuit (i) Main clock EXTAL (ii) Main clock EXTAL XTAL XTAL Rd Rd C1 C2 C 1 C2 Model Manufacturer fc (MHz) CSA8.00MTZ 00MTZ MURATA MFG CO., LTD. 12.00 Rd () Circuit example 10.00 CSA12 CSA12.00MTZ 00MTZ CST8.00MTW 00MTW C2 (pF) 8.00 CSA10 CSA10.0MTZ C1 (pF) (i) 30 30 0 8.00 CST10 CST10.0MT 10.00 CST12 CST12.0MTW 12.00 (ii) CSA16 CSA16.00MXZ040 00MXZ040 CST16 CST16.00MXZ0C1 00MXZ0C1 16.00 5 5 0 (i) 16.00 5 5 0 (ii) CSA20 CSA20.00MXZ040 00MXZ040 20.00 OPEN OPEN 0 CSA24 CSA24.00MXZ040 00MXZ040 24.00 3 3 0 CSA28 CSA28.00MXZ040 00MXZ040 CCR20 CCR20.0MC6 28.00 3 3 0 20.00 16 16 0 24.00 16 16 0 HC49/U-S HC49/U-S 28.00 1 1 220 CX-11F CX-11F 28.00 1 1 220 TDK CORPORATION. CCR24 CCR24.0MC6 KINSEKI LTD. (i) (ii) (i) Models with an asterisk () have the built-in ground capacitance (C1, C2). Selection Guide Mask Option item Product name Package ROM capacitance Reset pin pull-up resistor Power-on reset function1 CXP84540 CXP84540 OTP CXP84548 CXP84548 80-pin plastic QFP 40K bytes 48K bytes CXP845P60Q-180-pin plastic QFP PROM 60K bytes Existent/Non-existent Existent Existent/Non-existent Existent 1 When the OTP product with the power-on reset function is used outside the range of VDD = 4.5 to 5.5V, be sure to keep the external reset (setting the RST pin to Low) for the oscillation stable time or more. ­ 22 ­ CXP845P60 CXP845P60 Characteristics Curves IDD vs. VDD (fc = 28MHz, Ta = 25°C, Typical) IDD vs. fc (VDD = 5V, Ta = 25°C, Typical) 1/2 dividing mode 1/2 dividing mode 1/4 dividing mode 20.0 30 10.0 1/16 dividing mode Sleep mode 20 1.0 0.5 0.1 (100µA) 0.05 (50µA) Stop mode IDD ­ Supply current [mA] IDD ­ Supply current [mA] 5.0 0.01 (10µA) 1/4 dividing mode 15 10 1/16 dividing mode 5 2 3 4 5 6 7 Sleep mode VDD ­ Supply voltage [V] 0 20 10 fc ­ System clock [MHz] 30 IDD vs. fc (VDD = 3.3V, Ta = 25°C, Typical) IDD vs. VDD (fc = 20MHz, Ta = 25°C, Typical) 1/2 dividing mode 20.0 1/4 dividing mode 10.0 Sleep mode 1.0 0.5 0.1 (100µA) 0.05 (50µA) IDD ­ Supply current [mA] IDD ­ Supply current [mA] 20 1/16 dividing mode 5.0 15 1/2 dividing mode 10 1/4 dividing mode 5 0.01 (10µA) 1/16 dividing mode Sleep mode 2 3 4 5 6 7 0 VDD ­ Supply voltage [V] ­ 23 ­ 10 20 fc ­ System clock [MHz] 30 CXP845P60 CXP845P60 Package Outline Unit: mm 80PIN 80PIN QFP (PLASTIC) 23.9 ± 0.4 + 0.1 0.15 ­ 0.05 + 0.4 20.0 ­ 0.1 64 0.15 41 65 16.3 17.9 ± 0.4 + 0.4 14.0 ­ 0.1 40 A + 0.2 0.1 ­ 0.05 25 1 24 0.8 0.12 M + 0.15 0.35 ­ 0.1 + 0.35 2.75 ­ 0.15 0° to 10° DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE QFP-80P-L01 QFP-80P-L01 EIAJ CODE QFP080-P-1420-A QFP080-P-1420-A JEDEC CODE EPOXY RESIN LEAD TREATMENT SOLDER PLATING LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 1.6g ­ 24 ­ 0.8 ± 0.2 80