CXD2588Q/R CXD2588Q CXD2588R E97519-PS 2588R 2588Q 12VDD 26VDD AM51A 3400XX - Datasheet Archive

 

CD Digital Signal Processor with Built-in Digital Servo and DAC Description The CXD2588Q/R is a digital signal processor LSI for

 

CXD2588Q/R CXD2588Q/R CD Digital Signal Processor with Built-in Digital Servo and DAC Description The CXD2588Q/R CXD2588Q/R is a digital signal processor LSI for CD players. This LSI incorporates a digital servo, digital filter, zero detection circuit, 1-bit DAC and analog low-pass filter on a single chip. Features Digital Signal Processor (DSP) Block · Playback mode which supports CAV (Constant Angular Velocity) · Frame jitter free · 0.5× to 4× continuous playback possible · Allows relative rotational velocity readout · Supports spindle external control · Wide capture range playback mode · Spindle rotational velocity following method · Supports normal-speed, 4× speed playback · 16K RAM · EFM data demodulation · Enhanced EFM frame sync signal protection · SEC strategy-based error correction · Subcode demodulation and Sub Q data error detection · Digital spindle servo · 16-bit traverse counter · Asymmetry compensation circuit · CPU interface on serial bus · Error correction monitor signal, etc. output from a new CPU interface · Servo auto sequencer · Digital audio interface outputs · Digital level meter, peak meter · CD TEXT data demodulation CXD2588Q CXD2588Q 100 pin QFP (Plastic) Applications CD players Structure Silicon gate CMOS IC Absolute Maximum Ratings ­0.3 to +7.0 V · Supply voltage VDD · Input voltage VI ­0.3 to +7.0 V (VSS ­ 0.3V to VDD + 0.3) · Output voltage VO ­0.3 to +7.0 V · Storage temperature Tstg ­40 to +125 °C · Supply voltage difference VSS ­ AVSS ­0.3 to +0.3 V VDD ­ AVDD ­0.3 to +0.3 V Recommended Operating Conditions · Supply voltage VDDNote) +2.7 to +5.5 V · Operating temperature Topr ­20 to +75 °C Note) The VDD for the CXD2588Q/R CXD2588Q/R varies according to the playback speed selection. VDD [V] Playback speed CD-DSP block 4× 4.75 to 5.25 1× 3.0 to 5.5 4.5 to 5.5 1× Digital Servo (DSSP) Block · Microcomputer software-based flexible servo control · Offset cancel function for servo error signal · Auto gain control function for servo loop · E:F balance, focus bias adjustment functions · Surf jump function supporting micro two-axis Digital Filter, DAC and Analog Low-Pass Filter Blocks · DBB (digital bass boost) function · Double-speed playback supported · Digital de-emphasis · Digital attenuation · Zero detection function · 8Fs oversampling digital filter · S/N: 100dB or more (master clock: 384Fs, typ.) · Logical value: 109dB · THD + N: 0.007% or less (master clock: 384Fs, typ.) · Rejection band attenuation: ­60dB or less CXD2588R CXD2588R 100 pin LQFP (Plastic) 2.7 to 5.5 2.7 to 5.5 I/O Capacitance · Input pin · Output pin · I/O pin CI CO CI/O DAC block 11 (Max.) 11 (Max.) 11 (Max.) pF pF pF Note) Measurement conditions VDD = VI = 0V fM = 1MHz Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. ­1­ E97519-PS E97519-PS CXD2588Q/R CXD2588Q/R SYSM BCKI PCMDI LRCKI EMPHI BCK PCMD LRCK WDCK C2PO WFCK EMPH GFS VCTL XUGF V16M VCKI XTSL VPCO Block Diagram DAC Block FSTO C4M Error Corrector EFM demodurator XRST D/A Interface RMUT Serial-In Interface LMUT ASYI BIAS Asymmetry Corrector Over Sampling Digital Filter 16K RAM XPCK FILO FILI TES1 TEST Clock OSC Generator RFAC ASYO TES2 XTAI XTAO 3rd-Order Noise Shaper Sub Code Processor Digital PLL Timing Logic Digital OUT PWM PWM PCO CLTV MDP PWMI Digital CLV LOCK SENS DATA AOUT1 XLAT CLOK AIN1 CPU Interface Servo Auto Sequencer SPOA SPOB LOUT1 AOUT2 AIN2 XLON LOUT2 SCOR DOUT SBSO SCLK EXCK COUT SQSO SERVO Interface SQCK FSTI SSTP Signal Processor Block ATSK Servo Block MIRR MIRR DFCT FOK RFDC DFCT FOK CE SERVO DSP TE SE OPAmp Analog SW PWM GENERATOR VC TRACKING PWM GENERATOR TFDR SLED SERVO FE FOCUS PWM GENERATOR FFDR FOCUS SERVO TRACKING SERVO A/D Converter SLED PWM GENERATOR SFDR ADIO IGEN ­2­ FRDR TRDR SRDR CXD2588Q/R CXD2588Q/R SE NC TE CE RFDC ADIO AVSS0 AVDD0 IGEN ASYO ASYI BIAS RFAC AVSS3 CLTV FILO FILI PCO AVDD3 VCTL VCKI V16M VPCO VSS TES2 VDD DOUT LRCK LRCKI PCMD Pin Configuration (CXD2588Q CXD2588Q) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PCMDI 81 50 FE BCK 82 49 VC BCKI 83 48 XTSL EMPH 84 47 TES1 EMPHI 85 46 TEST XVDD 86 45 VSS XTAI 87 44 VSS XTAO 88 43 FRDR XVSS 89 42 AVDD1 90 FFDR 41 TRDR AOUT1 91 40 TFDR AIN1 92 39 SRDR LOUT1 93 38 SFDR AVSS1 94 37 FSTI AVSS2 95 36 FSTO LOUT2 96 35 SSTP 34 MDP AIN2 97 AOUT2 98 33 LOCK MIRR COUT C4M WDCK SCOR GFS C2PO DATA XPCK SYSM XUGF XRST WFCK EXCK XLON SBSO SPOB SQCK ­3­ SPOA 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 ATSK 8 VDD 7 VDD 6 PWMI 5 SCLK 4 SENS 3 CLOK 2 XLAT 1 SQSO 31 DFCT NC 32 FOK RMUT 100 LMUT AVDD2 99 CXD2588Q/R CXD2588Q/R TE CE RFDC ADIO AVSS0 IGEN AVDD0 ASYO ASYI BIAS RFAC AVSS3 CLTV FILO FILI PCO AVDD3 VCTL VCKI V16M VPCO VSS TES2 VDD DOUT Pin Configuration (CXD2588R CXD2588R) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 LRCK 76 50 NC LRCKI 77 49 SE PCMD 78 48 FE PCMDI 79 47 VC BCK 80 46 XTSL BCKI 81 45 TES1 EMPH 82 44 TEST EMPHI 83 43 VSS XVDD 84 42 VSS XTAI 85 41 FRDR XTAO 86 40 FFDR XVSS 87 39 TRDR AVDD1 88 38 TFDR AOUT1 89 37 SRDR AIN1 90 36 SFDR LOUT1 91 35 FSTI AVSS1 92 34 FSTO AVSS2 93 33 SSTP LOUT2 94 32 MDP 31 LOCK AIN2 95 26 WDCK ­4­ C4M SCOR GFS C2PO XPCK XUGF XLON WFCK 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SPOB 8 SPOA 7 VDD 6 ATSK 5 VDD 4 PWMI 3 SCLK 2 SENS 1 XLAT COUT NC 100 CLOK LMUT 99 DATA MIRR 27 SYSM 28 XRST DFCT RMUT 98 EXCK AVDD2 97 SBSO FOK 29 SQCK 30 SQSO AOUT2 96 CXD2588Q/R CXD2588Q/R Pin Description Pin No. CXD CXD 2588R 2588R 2588Q 2588Q Symbol I/O Output values 1, 0 Description Sub Q 80-bit, PCM peak and level data outputs. CD TEXT data output. 1 3 SQSO O 2 4 SQCK I 3 5 SBSO O 4 6 EXCK I SBSO readout clock input. 5 7 XRST I System reset. Reset when low. 6 8 SYSM I Mute input. Muted when high. 7 9 DATA I Serial data input from CPU. 8 10 XLAT I Latch input from CPU. Serial data is latched at the falling edge. 9 11 CLOK I Serial data transfer clock input from CPU. 10 12 SENS O 11 13 SCLK I SENS serial data readout clock input. 12 14 PWMI I Spindle motor external control input. 13 15 VDD - - Digital power supply. 14 16 VDD - - Digital power supply. 15 17 ATSK I/O 1, 0 16 18 SPOA I Microcomputer extension interface (input A) 17 19 SPOB I Microcomputer extension interface (input B) 18 20 XLON O 1, 0 Microcomputer extension interface (output) 19 21 WFCK O 1, 0 WFCK output. 20 22 XUGF O 1, 0 XUGF output. MINT1 or RFCK is output by switching with the command. 21 23 XPCK O 1, 0 XPCK output. MNT0 is output by switching with the command. 22 24 GFS O 1, 0 GFS output. MNT3 or XROF is output by switching with the command. 23 25 C2PO O 1, 0 C2PO output. GTOP is output by switching with the command. 24 26 SCOR O 1, 0 Outputs a high signal when either subcode sync S0 or S1 is detected. 25 27 C4M O 1, 0 4.2336MHz output. In CAV-W mode, 1/4 frequency division output for VCKI. 26 28 WDCK O 1, 0 Word clock output. f = 2Fs. 27 29 COUT I/O 1, 0 Track count signal input/output. 28 30 MIRR I/O 1, 0 Mirror signal input/output. 29 31 DFCT I/O 1, 0 Defect signal input/output. 30 32 FOK I/O 1, 0 Focus OK signal input/output. 31 33 LOCK I/O 1, 0 GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. Or input when LKIN = 1. 32 34 MDP O 1, Z, 0 33 35 SSTP I 34 36 FSTO O SQSO readout clock input. 1, 0 1, 0 Sub Q P to W serial output. SENS output to CPU. Anti-shock input/output. Spindle motor servo control output. Disc innermost track detection signal input. 1, 0 2/3 frequency division output for XTAI pin. ­5­ CXD2588Q/R CXD2588Q/R Pin No. CXD CXD 2588R 2588R 2588Q 2588Q Symbol I/O Output values Description 35 37 FSTI I 36 38 SFDR O 1, 0 Sled drive output. 37 39 SRDR O 1, 0 Sled drive output. 38 40 TFDR O 1, 0 Tracking drive output. 39 41 TRDR O 1, 0 Tracking drive output. 40 42 FFDR O 1, 0 Focus drive output. 41 43 FRDR O 1, 0 Focus drive output. 42 44 VSS - - Digital GND. 43 45 VSS - - Digital GND. 44 46 TEST I Test pin. Normally, GND. 45 47 TES1 I Test pin. Normally, GND. 46 48 XTSL I Crystal selection input. Low when the crystal is 16.9344MHz; high when the crystal is 33.8688MHz. 47 49 VC I Center voltage input. 48 50 FE I Focus error signal input. 49 51 SE I Sled error signal input. 50 52 NC 51 53 TE I Tracking error signal input. 52 54 CE I Center servo analog input. 53 55 RFDC I RF signal input. 54 56 ADIO O Analog 55 57 AVSS0 - - 56 58 IGEN I 57 59 AVDD0 - - 58 60 ASYO O 1, 0 59 61 ASYI I Asymmetry comparator voltage input. 60 62 BIAS I Asymmetry circuit constant current input. 61 63 RFAC I EFM signal input. 62 64 AVSS3 - 63 65 CLTV I 64 66 FILO O 65 67 FILI I 66 68 PCO O 1, Z, 0 67 69 AVDD3 - - 68 70 VCTL I Wide-band EFM PLL VCO2 control voltage input. 69 71 VCKI I Wide-band EFM PLL VCO2 oscillation input. 2/3 frequency division input for XTAI pin. Test pin. No connected. Analog GND. Operational amplifier constant current input. - Analog power supply. EFM full-swing output. (low = Vss, high = VDD) Analog GND. Multiplier VCO1 control voltage input. Analog Master PLL filter output. (slave = digital PLL) Master PLL filter input. Master PLL charge pump output. Analog power supply. ­6­ CXD2588Q/R CXD2588Q/R Pin No. CXD CXD 2588R 2588R 2588Q 2588Q Symbol I/O Output values Description 70 72 V16M O 1, 0 71 73 VPCO O 1, Z, 0 72 74 VSS - - 73 75 TES2 74 76 VDD - - 75 77 DOUT O 1, 0 Digital Out output. 76 78 LRCK O 1, 0 D/A interface. LR clock output f = Fs. 77 79 KRCKI I 78 80 PCMD O 79 81 PCMDI I 80 82 BCK O 81 83 BCKI I 82 84 EMPH O 83 85 EMPHI I 84 86 XVDD - 85 87 XTAI I Crystal oscillation circuit input. Master clock is externally input from this pin. 86 88 XTAO O Crystal oscillation circuit output. 87 89 XVSS - - Master clock GND. 88 90 AVDD1 - - Analog power supply. 89 91 AOUT1 O L ch analog output. 90 92 AIN1 I L ch operational amplifier input. 91 93 LOUT1 O L ch LINE output. 92 94 AVSS1 - - Analog GND. 93 95 AVSS2 - - Analog GND. 94 96 LOUT2 O R ch LINE output. 95 97 AIN2 I R ch operational amplifier output. 96 98 AOUT2 O R ch analog output. 97 99 AVDD2 - - 98 100 RMUT O 1, 0 R ch zero detection flag. 99 1 LMUT O 1, 0 L ch zero detection flag. 100 2 NC I Wide-band EFM PLL VCO2 oscillation output. Wide-band EFM PLL charge pump output. Digital GND. Test pin. Normally GND. Digital power supply. D/A interface. LR clock input. 1, 0 D/A interface. Serial data output. (two's complement, MSB first) D/A interface. Serial data input. (two's complement, MSB first) 1, 0 D/A interface. Bit clock output. D/A interface. Bit clock input. 1, 0 Outputs a high signal when the playback disc has emphasis, and a low signal when there is no emphasis. Inputs a high signal when de-emphasis is on, and a low signal when de-emphasis is off. - Master clock power supply. Analog power supply. ­7­ CXD2588Q/R CXD2588Q/R Notes) · PCMD is a MSB first, two's complement output. · GTOP is used to monitor the frame sync protection status. (High: sync protection window released.) · XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync protection. · XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide. · The GFS signal goes high when the frame sync and the insertion timing match. · RFCK is derived from the crystal accuracy, and has a cycle of 136µs. · C2PO represents the data error status. · XROF is generated when the 16K RAM exceeds the ±4F jitter margin. Monitor Pin Output Combinations Command bit Output data MTSL1 MTSL0 0 0 XUGF XPCK GFS C2PO 0 1 MNT1 MNT0 MNT3 C2PO 1 0 RFCK XPCK XROF GTOP ­8­ CXD2588Q/R CXD2588Q/R Electrical Characteristics 1. DC Characteristics (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = ­20 to +75°C) Item Conditions Input voltage (1) High level input voltage VIH (1) Input voltage (2) High level input voltage VIH (2) Input voltage (3) High level input voltage VIH (3) Low level input voltage Low level input voltage Min. Low level input voltage VIN (4) Schmitt input Unit V 0.3VDD 0.8VDD V V 0.2VDD 0.8VDD VIL (3) Input voltage Max. 0.7VDD VIL (1) VIL (2) Typ. V V 0.2VDD V Vss VDD V High level output voltage VOH (1) IOH = ­2mA Output Avoltage (1) Low level output voltage VOL (1) IOL = 4mA VDD ­ 0.8 VDD V Vss 0.4 V High level output voltage VOH (2) IOH = ­4mA Output Avoltage (2) Low level output voltage VOL (2) IOL = 8mA VDD ­ 0.8 VDD V Vss 0.4 V High level output voltage VOH (3) IOH = ­6mA Output Avoltage (3) Low level output voltage VOL (3) IOL = 4mA VDD ­ 0.8 VDD V Vss 0.4 V VDD V 0.4 V Input voltage (4) Analog input High level output voltage VOH (4) IOH = ­0.28mA VDD ­ 0.5 Output Avoltage (4) Low level output voltage VOL (4) IOL = 0.36mA Vss Applicable pins 1, 11 2, 12 3 4, 9, 10 5 6 7 8 Input leak current (1) ILI (1) VIN = VSS or VDD ­10 10 µA 1, 2 Input leak current (2) ILI (2) VIN = VSS or VDD ­40 40 µA 11, 12 Input leak current (3) ILI (3) VI = 1.5 to 3.5V ­20 20 µA 9 Input leak current (4) ILI (4) VI = 0 to 5.0V ­40 600 µA 10 Applicable pins 1 SYSM, DATA, XLAT, PWMI, SSTP, FSTI, XTSL, TEST, TES1, VCKI, TES2 2 SQCK, XRST, CLOK 3 LRCKI, PCMDI, BCKI, EMPHI 4 ASYI, RFAC, CLTV, FILI, VCTL 5 SQSO, SBSO, SENS, ATSK, XLON, WFCK, XUGF, XPCK, GFS, C2PO, SCOR, C4M, WDCK, COUT, MIRR, DFCT, FOK, LOCK, FSTO, SFDR, SRDR, TFDR, TRDR, FFDR, FRDR, ASYO, DOUT, LRCK, PCMD, BCK, EMPH, RMUT, LMUT 6 V16M 7 MDP, PCO, VPCO 8 FILO 9 VC, FE, SE, TE, CE 10 RFDC 11 EXCK, ATSK, COUT, MIRR, DFCT, FOK, LOCK 12 SCLK, SPOA, SPOB ­9­ CXD2588Q/R CXD2588Q/R 2. AC Characteristics (1) XTAI pin (a) When using self-excited oscillation (Topr = ­20 to +75°C, VDD = AVDD = 5.0V ± 5%) Item Oscillation frequency Symbol Max. Typ. 7 fMAX Unit 34 Min. MHz (b) When inputting pulses to XTAI pin (Topr = ­20 to +75°C, VDD = AVDD = 5.0V ± 5%) Item Symbol Min. Typ. Max. Unit High level pulse width tWHX 13 500 ns Low level pulse width tWLX 13 500 ns Pulse cycle tCK 26 1,000 ns Input high level VIHX VDD ­ 1.0 Input low level VILX 0.8 V Rise time, fall time tR, tF 10 ns V tCX tWLX tWHX VIHX VIHX × 0.9 VDD/2 XTAI VIHX × 0.1 VILX tR tF (c) When inputting sine waves to XTAI pin via a capacitor (Topr = ­20 to +75°C, VDD = AVDD = 5.0V ± 5%) Item Input amplitude Symbol Min. VI 2.0 Typ. Max. Unit VDD + 0.3 Vp-p ­ 10 ­ CXD2588Q/R CXD2588Q/R (2) CLOK, DATA, XLAT, COUT, SQCK, and EXCK pins (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = ­20 to +75°C) Item Min. Clock frequency Latch pulse width tWCK tSU tH tD tWL EXCK, SQCK frequency Typ. fCK Clock pulse width Max. fT Setup time Hold time Delay time Unit 0.65 Symbol MHz 750 ns 300 ns 300 ns 300 ns 750 ns 0.65Note) MHz 750Note) EXCK, SQCK pulse width fWT ns 1/fCK tWCK tWCK CLOK DATA XLAT tSU tH tD tWL EXCK SQCK tWT tWT 1/fT SBSO SQSO tSU tH Note) In quasi double-speed playback mode, except when SQSO is Sub Q Read, the SQCK maximum operating frequency is 300kHz and its minimum pulse width is 1.5µs. (3) BCKI, LRCKI and PCMDI pins (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = ­20 to +75°C) Item Symbol Conditions BCK pulse width DATAL, R hold time LRCK setup time Typ. Unit ns 18 ns 18 ns 18 ns tW(BCKI) tW(BCKI) BCKI Max. 94 tW tSU tH tSU DATAL, R setup time Min. VDD/2 VDD/2 tSU tH (PCMDI) (PCMDI) PCMDI tSU (LRCKI) LRCKI ­ 11 ­ CXD2588Q/R CXD2588Q/R (4) SCLK pin XLAT tDLS tSPW SCLK ··· 1/fSCLK Serial Read Out Data (SENS) Item MSB tSPW tDLS Typ. Delay time LSB Unit MHz fSCLK SCLK pulse width Min. Max. 16 Symbol SCLK frequency ··· 31.3 ns 15 µs (5) COUT, MIRR and DFCT pins Operating frequency (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = ­20 to +75°C) Item Symbol Min. Typ. Max. Unit Conditions COUT maximum operating frequency fCOUT 40 kHz 1 MIRR maximum operating frequency fMIRR 40 kHz 2 DFCT maximum operating frequency fDFCTH 5 kHz 3 1 When using a high-speed traverse TZC 2 B A When the RF signal continuously satisfies the following conditions during the above traverse. · A = 0.12VDD 12VDD to 0.26VDD 26VDD · B = 25% A+B 3 During complete RF signal omission When settings related to DFCT signal generation are Typ. ­ 12 ­ CXD2588Q/R CXD2588Q/R 1-bit DAC and LPF Block Analog Characteristics Analog characteristics (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Ta = 25°C) Item Symbol Total harmonic distortion THD Signal-to-noise ratio S/N Typ. Max. 384Fs 0.0050 0.0070 768Fs 0.0045 0.0065 Min. Crystal Conditions 1kHz, 0dB data 384Fs 96 100 768Fs 1kHz, 0dB data (Using A-weighting filter) 96 100 Fs = 44.1kHz in all cases. The total harmonic distortion and signal-to-noise ratio measurement circuits are shown below. 12k AOUT1 (2) 680p 12k 12k SHIBASOKU (AM51A AM51A) AIN1 (2) 150p LOUT1 (2) Audio Analyzer 22µ 100k LPF external circuit diagram 768Fs/384Fs Rch DATA TEST DISC A Lch B RF CXD2588Q/R CXD2588Q/R Audio Analyzer Block diagram of analog characteristics measurement ­ 13 ­ Unit % dB CXD2588Q/R CXD2588Q/R (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Topr = ­20 to +75°C) Item Symbol Output voltage RL 8 Max. Unit Applicable pins Vrms 1 k Typ. 1.12 VOUT Load resistance Min. 1 Measurement is conducted for the LPF external circuit diagram with the sine wave output of 1kHz and 0dB. Applicable pins 1 LOUT1, LOUT2 ­ 14 ­ CXD2588Q/R CXD2588Q/R Contents §1. CPU Interface §1-1. CPU Interface Timing . 16 §1-2. CPU Interface Command Table . 16 §1-3. CPU Command Presets . 26 §1-4. Description of SENS Signals and Commands . 31 §2. Subcode Interface §2-1. P to W Subcode Readout . 51 §2-2. 80-bit Sub Q Readout . 51 §3. Description of Modes §3-1. CLV-N Mode . 56 §3-2. CLV-W Mode . 56 §3-3. CAV-W Mode . 56 §4. Description of Other Functions §4-1. Channel Clock Regeneration by the Digital PLL Circuit . 58 §4-2. Frame Sync Protection . 60 §4-3. Error Correction . 60 §4-4. DA Interface . 61 §4-5. Digital Out . 63 §4-6. Servo Auto Sequence . 63 §4-7. Digital CLV . 70 §4-8. CD-DSP Block Playback Speed . 71 §4-9. DAC Block Playback Speed . 71 §4-10. DAC Block Input Timing . 72 §4-11. Description of DAC Block Functions . 72 §4-12. LPF Block . 76 §4-13. Asymmetry Compensation . 77 §4-14. CD Text Data Demodulation . 78 §5. Description of Servo Signal Processing System Functions and Commands §5-1. General Description of Servo Signal Processing System . 80 §5-2. Digital Servo Block Master Clock (MCK) . 81 §5-3. AVRG Measurement and Compensation . 81 §5-4. E:F Balance Adjustment Function . 83 §5-5. FCS Bias Adjustment Function . 83 §5-6. AGCNTL Function . 85 §5-7. FCS Servo and FCS Search . 87 §5-8. TRK and SLD Servo Control . 88 §5-9. MIRR and DFCT Signal Generation . 89 §5-10. DFCT Countermeasure Circuit . 90 §5-11. Anti-Shock Circuit . 90 §5-12. Brake Circuit . 91 §5-13. COUT Signal . 92 §5-14. Serial Readout Circuit . 92 §5-15. Writing to the Coefficient RAM . 93 §5-16. PWM Output . 93 §5-17. Servo Status Changes Produced by the LOCK Signal . 95 §5-18. Description of Commands and Data Sets . 95 §5-19. List of Servo Filter Coefficients . 110 §5-20. Filter Composition . 112 §5-21. TRACKING and FOCUS Frequency Response . 119 §6. Application Circuit . 120 Explanation of abbreviations AVRG: AGCNTL: FCS: TRK: SLD: DFCT: Average Auto gain control Focus Tracking Sled Defect ­ 15 ­ CXD2588Q/R CXD2588Q/R §1. CPU Interface §1-1. CPU Interface Timing · CPU interface This interface uses DATA, CLOK and XLAT to set the modes. The interface timing chart is shown below. 750ns or more CLOK DATA D0 D1 D18 D19 D20 D21 D22 D23 750ns or more XLAT Valid Registers · The internal registers are initialized by a reset when XRST = 0. Note) Be sure to set SQCK to high when XLAT is low. §1-2. CPU Interface Command Table Total bit length for each register Register 0 to 2 3 Total bit length 8 bits 8 to 24 bits 4 to 6 8 bits 7 20 bits 8 28 bits 9 24 bits A 28 bits B 16 bits C 8 bits D 16 bits E 20 bits ­ 16 ­ 0 TRACKING CONTROL FOCUS CONTROL 1 Command Register 0001 0000 - - - - 0 0 0 0 0 1 1 ­ 17 ­ 0 - - - 1 0 - - - - - 1 0 D18 - - - - - 1 0 - - - - 1 1 1 0 - - D17 Data 1 1 D23 to D20 D19 Address Command Table ($0X to 1X) 0 1 - - - - - - 1 0 - - - - D16 - - - - - - - - - - - - - - D15 - - - - - - - - - - - - - - D14 - - - - - - - - - - - - - - D13 Data 2 - - - - - - - - - - - - - - D12 - - - - - - - - - - - - - - D11 - - - - - - - - - - - - - - D10 - - - - - - - - - - - - - - D9 Data 3 - - - - - - - - - - - - - - D8 - - - - - - - - - - - - - - D7 - - - - - - - - - - - - - - D6 - - - - - - - - - - - - - - D5 Data 4 - - - - - - - - - - - - - - D4 - - - - - - - - - - - - - - D3 - - - - - - - - - - - - - - D2 - - - - - - - - - - - - - - D1 Data 5 - - - - - - - - - - - - - - D0 -: Don't care TRACKING GAIN UP FILTER SELECT 2 TRACKING GAIN UP FILTER SELECT 1 TRACKING GAIN UP TRACKING GAIN NORMAL BRAKE OFF BRAKE ON ANTI SHOCK OFF ANTI SHOCK ON FOCUS SEACH VOLTAGE UP FOCUS SEARCH VOLTAGE DOWN FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT FOCUS SERVO OFF, 0V OUT FOCUS SERVO ON (FOCUS GAIN DOWN) FOCUS SERVO ON (FOCUS GAIN NORMAL) CXD2588Q/R CXD2588Q/R ­ 18 ­ 3 SELECT Command TRACKING MODE 2 Register Command Register 1 1 - 0 1 - 0011 0 0 0 0 0 0 D18 0 D23 to D20 D19 - - - - - - 1 0 Address 0010 0 D18 0 1 0 1 0 - - - - D16 1 1 0 0 D17 1 0 1 0 D16 Data 1 1 1 0 0 - - - - D17 Data 1 0 D23 to D20 D19 Address Command Table ($2X to 3X) - - - - D15 - - - - - - - - D15 - - - - - - - - D13 - - - - D14 - - - - D13 Data 2 - - - - - - - - D14 Data 2 - - - - D12 - - - - - - - - D12 - - - - D11 - - - - - - - - D11 - - - - - - - - D9 - - - - D10 - - - - D9 Data 3 - - - - - - - - D10 Data 3 - - - - D8 - - - - - - - - D8 - - - - D7 - - - - - - - - D7 - - - - - - - - D5 - - - - D6 - - - - D5 Data 4 - - - - - - - - D6 Data 4 - - - - D4 - - - - - - - - D4 - - - - D3 - - - - - - - - D3 - - - - - - - - D1 - - - - D2 - - - - D1 Data 5 - - - - - - - - D2 Data 5 - - - - D0 - - - - - - - - D0 -: Don't care SLED KICK LEVEL (±4 × basic value) SLED KICK LEVEL (±3 × basic value) SLED KICK LEVEL (±2 × basic value) SLED KICK LEVEL (±1 × basic value) (Default) REVERSE SLED MOVE FORWARD SLED MOVE SLED SERVO ON SLED SERVO OFF REVERSE TRACK JUMP FORWARD TRACK JUMP TRACKING SERVO ON TRACKING SERVO OFF CXD2588Q/R CXD2588Q/R 3 Register SELECT Command Address 2 Address 3 0011 0100 0000 0 0 1 1 1 0 0 0 0 0 0 ­ 19 ­ 0 0 0 1 1 1 1 1 1 0 0 0 0 D10 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D9 Address 4 0 D23 to D20 D19 to D16 D15 to D12 D11 Address 1 Command Table ($340X) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 D8 D6 D5 D4 D3 D2 D1 Data 2 D0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 D7 Data 1 KRAM DATA (K0F) FOCUS DEFECT HOLD GAIN KRAM DATA (K0E) FOCUS PHASE COMPENSATE FILTER A KRAM DATA (K0D) FOCUS LOW BOOST FILTER B-L KRAM DATA (K0C) FOCUS LOW BOOST FILTER B-H KRAM DATA (K0B) FOCUS LOW BOOST FILTER A-L KRAM DATA (K0A) FOCUS LOW BOOST FILTER A-H KRAM DATA (K09) FOCUS HIGH CUT FILTER B KRAM DATA (K08) FOCUS HIGH CUT FILTER A KRAM DATA (K07) SLED AUTO GAIN KRAM DATA (K06) FOCUS INPUT GAIN KRAM DATA (K05) SLED OUTPUT GAIN KRAM DATA (K04) SLED LOW BOOST FILTER B-L KRAM DATA (K03) SLED LOW BOOST FILTER B-H KRAM DATA (K02) SLED LOW BOOST FILTER A-L KRAM DATA (K01) SLED LOW BOOST FILTER A-H KRAM DATA (K00) SLED INPUT GAIN CXD2588Q/R CXD2588Q/R 3 Register SELECT Command Address 2 Address 3 0011 0100 0001 0 0 1 1 1 0 0 0 0 0 0 ­ 20 ­ 0 0 0 1 1 1 1 1 1 0 0 0 0 D10 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D9 Address 4 0 D23 to D20 D19 to D16 D15 to D12 D11 Address 1 Command Table ($341X) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 D8 D6 D5 D4 D3 D2 D1 Data 2 D0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 D7 Data 1 KRAM DATA (K1F) TRACKING LOW BOOST FILTER B-L KRAM DATA (K1E) TRACKING LOW BOOST FILTER B-H KRAM DATA (K1D) TRACKING LOW BOOST FILTER A-L KRAM DATA (K1C) TRACKING LOW BOOST FILTER A-H KRAM DATA (K1B) TRACKING HIGH CUT FILTER B KRAM DATA (K1A) TRACKING HIGH CUT FILTER A KRAM DATA (K19) TRACKING INPUT GAIN KRAM DATA (K18) FIX KRAM DATA (K17) HPTZC / AUTO GAIN LOW PASS FILTER B KRAM DATA (K16) ANTI SHOCK HIGH PASS FILTER A KRAM DATA (K15) HPTZC / AUTO GAIN HIGH PASS FILTER B KRAM DATA (K14) HPTZC / AUTO GAIN HIGH PASS FILTER A KRAM DATA (K13) FOCUS AUTO GAIN KRAM DATA (K12) ANTI SHOCK INPUT GAIN KRAM DATA (K11) FOCUS OUTPUT GAIN KRAM DATA (K10) FOCUS PHASE COMPENSATE FILTER B CXD2588Q/R CXD2588Q/R 3 Register SELECT Command Address 2 Address 3 0011 0100 0010 0 0 1 1 1 0 0 0 0 0 0 ­ 21 ­ 0 0 0 1 1 1 1 1 1 0 0 0 0 D10 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D9 Address 4 0 D23 to D20 D19 to D16 D15 to D12 D11 Address 1 Command Table ($342X) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 D8 D6 D5 D4 D3 D2 D1 Data 2 D0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 D7 Data 1 KRAM DATA (K2F) NOT USED KRAM DATA (K2E) NOT USED KRAM DATA (K2D) FOCUS GAIN DOWN OUTPUT GAIN KRAM DATA (K2C) FOCUS GAIN DOWN PHASE COMPENSATE FILTER B KRAM DATA (K2B) FOCUS GAIN DOWN DEFECT HOLD GAIN KRAM DATA (K2A) FOCUS GAIN DOWN PHASE COMPENSATE FILTER A KRAM DATA (K29) FOCUS GAIN DOWN LOW BOOST FILTER B-L KRAM DATA (K28) FOCUS GAIN DOWN LOW BOOST FILTER B-H KRAM DATA (K27) FOCUS GAIN DOWN LOW BOOST FILTER A-L KRAM DATA (K26) FOCUS GAIN DOWN LOW BOOST FILTER A-H KRAM DATA (K25) FOCUS GAIN DOWN HIGH CUT FILTER B KRAM DATA (K24) FOCUS GAIN DOWN HIGH CUT FILTER A KRAM DATA (K23) TRACKING AUTO GAIN KRAM DATA (K22) TRACKING OUTPUT GAIN KRAM DATA (K21) TRACKING PHASE COMPENSATE FILTER B KRAM DATA (K20) TRACKING PHASE COMPENSATE FILTER A CXD2588Q/R CXD2588Q/R 3 Register SELECT Command Address 2 Address 3 0011 0100 0011 0 0 1 1 1 0 0 0 0 0 0 ­ 22 ­ 0 0 0 1 1 1 1 1 1 0 0 0 0 D10 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D9 Address 4 0 D23 to D20 D19 to D16 D15 to D12 D11 Address 1 Command Table ($343X) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 D8 D6 D5 D4 D3 D2 D1 Data 2 D0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 D7 Data 1 KRAM DATA (K3F) NOT USED KRAM DATA (K3E) TRACKING GAIN UP OUTPUT GAIN KRAM DATA (K3D) TRACKING GAIN UP PHASE COMPENSATE FILTER B KRAM DATA (K3C) TRACKING GAIN UP PHASE COMPENSATE FILTER A KRAM DATA (K3B) TRACKING GAIN UP2 LOW BOOST FILTER B-L KRAM DATA (K3A) TRACKING GAIN UP2 LOW BOOST FILTER B-H KRAM DATA (K39) TRACKING GAIN UP2 LOW BOOST FILTER A-L KRAM DATA (K38) TRACKING GAIN UP2 LOW BOOST FILTER A-H KRAM DATA (K37) TRACKING GAIN UP2 HIGH CUT FILTER B KRAM DATA (K36) TRACKING GAIN UP2 HIGH CUT FILTER A KRAM DATA (K35) ANTI SHOCK FILTER COMPARATE GAIN KRAM DATA (K34) ANTI SHOCK HIGH PASS FILTER B-L KRAM DATA (K33) ANTI SHOCK HIGH PASS FILTER B-H KRAM DATA (K32) NOT USED KRAM DATA (K31) ANTI SHOCK LOW PASS FILTER B KRAM DATA (K30) SLED INPUT GAIN (when SFSK = 1 TG up2) CXD2588Q/R CXD2588Q/R 3 Register SELECT Command Address 2 Address 3 0011 0100 0100 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 D10 1 ­ 23 ­ 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D9 Address 4 0 D23 to D20 D19 to D16 D15 to D12 D11 Address 1 Command Table ($344X) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 D8 D6 D5 D4 D3 D2 D1 Data 2 D0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 D7 Data 1 KRAM DATA (K4F) NOT USED KRAM DATA (K4E) NOT USED KRAM DATA (K4D) FOCUS HOLD FILTER OUTPUT GAIN KRAM DATA (K4C) FOCUS HOLD FILTER B-L KRAM DATA (K4B) FOCUS HOLD FILTER B-H KRAM DATA (K4A) FOCUS HOLD FILTER A-L KRAM DATA (K49) FOCUS HOLD FILTER A-H KRAM DATA (K48) FOCUS HOLD FILTER INPUT GAIN KRAM DATA (K47) NOT USED KRAM DATA (K46) TRACKING HOLD INPUT GAIN (when THSK = 1 TG up2) KRAM DATA (K45) TRACKING HOLD FILTER OUTPUT GAIN KRAM DATA (K44) TRACKING HOLD FILTER B-L KRAM DATA (K43) TRACKING HOLD FILTER B-H KRAM DATA (K42) TRACKING HOLD FILTER A-L KRAM DATA (K41) TRACKING HOLD FILTER A-H KRAM DATA (K40) TRACKING HOLD FILTER INPUT GAIN CXD2588Q/R CXD2588Q/R 3 Register SELECT Command 0011 D17 D17 0 1 0 1 0 0 1 1 0 ­ 24 ­ 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 1 0 D18 Address 0 1 1 0 D18 0 D23 to D20 D19 0011 0 D23 to D20 D19 Address 1 Command Table ($34FX to 3FX) 1 0 1 0 1 0 1 0 1 0 1 D16 0 0 0 D16 1 1 1 D13 D13 D12 1 1 1 D12 FT0 D8 TJ2 TJ1 D6 D5 D4 D3 D2 D1 Data 3 TV5 FB5 D6 D5 Data 3 TV6 FB6 D4 TV4 FB4 D3 TV3 FB3 TV1 FB1 D2 D1 Data 4 TV2 FB2 D0 TV0 - FTZ FG6 FG5 FG4 FG3 FG2 FG1 FG0 D7 TV7 FB7 - D0 TJ0 SFJP TG6 TG5 TG4 TG3 TG2 TG1 TG0 FS2 FS1 FS0 FS3 D9 D8 TV9 TV8 FB9 FB8 D10 TJ3 D7 Data 2 FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 D9 Data 2 0 1 0 D10 D11 0 0 1 D11 Data 1 LEVEL/AUTO GAIN/ DFSW/ (Initialize) FZSL/SLED MOVE/ Voltage/AUTO GAIN DTZC/TRACK JUMP VOLTAGE/AUTO GAIN FOCUS SEARCH SPEED/ VOLTAGE/AUTO GAIN TRVSC DATA FOCUS BIAS DATA FOCUS BIAS LIMIT 0 0 TLD2 TLD1 TLD0 0 0 0 AGG4 XT4D XT2D 0 DRR2 DRR1 DRR0 0 0 0 0 0 0 0 0 0 0 0 AGHF ASOT Others -: Don't care SLED FILTER TZC/COUT BOTTOM/MIRR Operation for MIRR/ DFCT/FOK LKIN COIN MDFI MIRI XT1D Filter 0 0 ASFG FTQ LPAS SRO1 0 0 BTS1 BTS0 MRC1 MRC0 F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD SFID SFSK THID THSK 0 0 SJHD INBK MTI0 FOCUS BIAS 0 0 TJD0 FPS1 FPS0 TPS1 TPS0 0 COSS COTS CETZ CETF COT2 COT1 MOT2 0 0 0 FBON FBSS FBUP FBV1 FBV0 0 SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT 0 0 DAC SD6 SD5 SD4 SD3 SD2 SD1 SD0 0 SERIAL DATA READ MODE/SELECT VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0 FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT TJ4 FS5 FS4 D14 Data 1 1 1 1 D14 TDZC DTZC TJ5 FT1 D15 1 1 1 D15 Address 2 CXD2588Q/R CXD2588Q/R 0 0 0 0 0 0 0 1 1 1 1 Blind (A, E), Overflow (C) Brake (B) KICK (D) Auto sequence (N) track jump count setting MODE specification Function specification Audio CTRL Serial bus CTRL Spindle servo coefficient setting CLV CTRL CLV mode 6 7 8 9 A B C D E 0 0 ­ 25 ­ 1 1 0 1 1 0 1 1 0 0 0 1 1 1 0 1 1 1 1 1 1 0 5 1 0 D1 Auto sequence D2 4 D3 Address Command Register Instruction Table 1 1 0 1 0 1 0 0 1 1 0 1 0 1 0 D0 D2 D1 D0 - - - D3 - - - D2 - - - D1 Data 2 0 TB TP SYCOF SYCOF - - - 0 0 0 0 ZDPL ZMUT ZDPL ZMUT 0 4 - - - D2 0 - VCO2 THRU 2 - - - D1 Data 4 0 - 0 1 - - - D0 0 - 0 - - - - D3 DCOF - 0 - - - - D2 0 - 0 - - - - D1 Data 5 0 - 0 - - - - D0 - - - - D2 - - - - D1 - - - - D0 - - - - - - - - - - - - TXON TXOUT OUTL1 OUTL0 - - - - D3 Data 6 - 0 0 - Gain Gain CAV1 CAV0 - - - 0 - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FMUT LRWO BSBST BBSL AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 0 0 0 8 - - - D3 - - 16 - - - D0 Gain VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0 CLVS - 32 - - - D1 - - 0 OPSL2 EMPH SMUT 1 0 OPSL1 MCSL 1 OPSL1 MCSL 0 OPSL2 EMPH SMUT 0 0 64 - - - D2 CM3 CM2 CM1 CM0 EPWM SPDC ICAP SFSL VC2C HIFC LPWR VPON 0 0 0 0 128 - - - D3 VCO KSL3 KSL2 KSL1 KSL0 SEL2 TRMI TRMO MTSL1 MTSL0 0 0 0 0 SOCT 256 - - - D0 Data 3 - 0 Mute ATT Mute ATT 0 SL0 CPUSR 0 0 DSPB ON/OFF 0 0 0 DSPB ON/OFF 0 0 VCO DOUT DOUT WSEL SEL1 Mute ON/OFF Gain Gain Gain Gain MDP1 MDP0 MDS1 MDS0 SL1 0 0 0 0 CDROM 32768 16384 8192 4096 2048 1024 512 11.6ms 5.8ms 2.9ms 1.45ms 0.36ms 0.18ms 0.09ms 0.05ms 0.18ms 0.09ms 0.05ms 0.02ms AS3 AS2 AS1 AS0 D3 Data 1 CXD2588Q/R CXD2588Q/R Command Register SELECT 0010 TRACKING MODE 2 3 0001 TRACKING CONTROL 1 0 0 0 ­ 26 ­ 0011 0 D18 0 0 0 D18 0 1 D18 0 1 0 D16 0 D17 0 D17 0 D16 0 D16 Data 1 0 0 0 D17 Data 1 Address 1 0 D23 to D20 D19 0011 D23 to D20 D19 Address 0000 FOCUS CONTROL 0 D23 to D20 D19 Command Register Address Command Preset Table ($0X to 34X) §1-3. CPU Command Presets 0 D15 - D15 - - - D15 - - - D13 - D13 D14 D13 Address 2 - D14 Data 2 - - - D14 Data 2 D12 - D12 - - - D12 D11 - D11 - - - D11 - - - D9 - D9 D9 D8 - D8 - - - D8 D6 - D5 D6 D5 Data 1 - - D7 - - - D5 Data 4 - - - D6 D7 - - - D7 Data 4 D4 - D4 - - - D4 See "Coefficient ROM Preset Values Table". D10 Address 3 - D10 Data 3 - - - D10 Data 3 D3 - D3 - - - D3 - - - D1 - D0 D2 D0 Data 2 - D2 Data 5 - - - D2 Data 5 D0 - D0 - - - D0 -: Don't care KRAM DATA ($3400XX 3400XX to $344fXX) SLED KICK LEVEL (±1 × basic value) (Default) TRACKING SERVO OFF SLED SERVO OFF TRACKING GAIN UP FILTER SELECT 1 FOCUS SERVO OFF, 0V OUT CXD2588Q/R CXD2588Q/R 3 Register SELECT Command 0011 D17 D17 0 1 0 1 0 0 1 1 0 ­ 27 ­ 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 1 0 D18 Address 0 1 1 0 D18 0 D23 to D20 D19 0011 0 D23 to D20 D19 Address 1 Command Preset Table ($34FX to 3FX) 1 0 1 0 1 0 1 0 1 0 1 D16 0 0 0 D16 1 1 1 D13 0 0 0 0 0 1 1 D11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 D12 0 0 1 D11 1 0 0 0 0 0 0 D13 1 1 1 D12 1 0 0 0 1 0 1 D14 Data 1 1 1 1 D14 1 0 0 0 0 0 0 D15 1 1 1 D15 Address 2 0 0 0 D9 0 0 0 0 0 0 0 0 0 1 0 D10 0 0 0 0 0 0 0 0 0 1 0 D9 Data 2 0 1 0 D10 0 0 0 0 0 0 0 0 0 0 0 D8 0 0 0 D8 Data 1 0 0 0 1 0 0 0 0 1 0 0 D7 0 0 0 D7 0 0 0 D5 0 0 0 0 1 0 0 0 0 0 0 D6 0 0 0 0 0 0 0 0 1 1 1 D5 Data 3 0 0 0 D6 Data 2 0 0 0 0 1 0 0 0 1 0 0 D4 0 0 0 D4 0 0 0 0 0 0 0 0 1 1 1 D3 0 0 0 D3 0 0 0 D1 0 0 0 0 0 0 0 0 0 1 1 D2 0 0 0 0 0 0 0 0 1 1 0 D1 Data 4 0 0 0 D2 Data 3 0 0 0 0 0 0 0 0 0 0 1 D0 0 0 0 D0 Others Filter -: Don't care SLED FILTER TZC/COUT BOTTOM/MIRR Operation for MIRR/ DFCT/FOK FOCUS BIAS SERIAL DATA READ MODE/SELECT LEVEL/AUTO GAIN/ DFSW/ (Initialize) FZSL/SLED MOVE/ Voltage/AUTO GAIN DTZC/TRACK JUMP VOLTAGE AUTO GAIN FOCUS SEARCH SPEED/ VOLTAGE AUTO GAIN TRVSC DATA FOCUS BIAS DATA FOCUS BIAS LIMIT CXD2588Q/R CXD2588Q/R 0 1 1 Auto sequence (N) track jump count setting MODE specification Function specification 7 8 9 1 0 KICK (D) 6 1 1 1 1 Audio CTRL 0 Blind (A, E), Overflow (C) Brake (B) 5 Serial bus CTRL Spindle servo coefficient setting CLV CTRL CLV mode A 0 Auto sequence 4 D3 Command Register Reset Initialization B ­ 28 ­ C D E 1 1 1 0 0 0 0 1 1 1 1 D2 1 0 0 1 1 0 0 1 1 0 0 D1 Address 0 1 0 1 0 1 0 1 0 1 0 D0 0 0 0 0 0 0 0 0 0 0 0 D3 0 0 1 0 0 0 0 0 1 1 0 D2 0 0 1 1 1 0 0 0 1 0 0 D1 Data 1 0 0 0 0 1 0 0 0 1 1 0 D0 0 1 - 0 0 0 0 0 - - - D3 0 1 - 1 0 0 0 0 - - - D2 0 1 - 0 0 0 0 0 - - - D1 Data 2 0 0 - 0 0 0 0 1 - - - D0 0 0 - 0 0 0 0 0 - - - D3 0 0 - 0 1 0 0 0 - - - D2 0 0 - 0 0 0 1 0 - - - D1 Data 3 0 0 - 0 0 0 0 0 - - - D0 0 - - - 0 0 0 0 - - - D3 0 - - - 0 0 0 0 - - - D2 0 - - - 0 0 0 0 - - - D1 Data 4 0 - - - 0 0 0 0 - - - D0 - - - - 0 0 0 - - - - D3 - - - - 0 0 0 - - - - D2 - - - - 0 0 0 - - - - D1 Data 5 - - - - 0 0 0 - - - - D0 - - - - 0 - 0 - - - - D3 - - - - 0 - 0 - - - - D2 - - - - 0 - 0 - - - - D1 Data 6 - - - - 0 - 0 - - - - D0 CXD2588Q/R CXD2588Q/R CXD2588Q/R CXD2588Q/R ADDRESS DATA K00 K01 K02 K03 K04 K05 K06 K07 K08 K09 K0A K0B K0C K0D K0E K0F E0 81 23 7F 6A 10 14 30 7F 46 81 1C 7F 58 82 7F SLED INPUT GAIN SLED LOW BOOST FILTER A-H SLED LOW BOOST FILTER A-L SLED LOW BOOST FILTER B-H SLED LOW BOOST FILTER B-L SLED OUTPUT GAIN FOCUS INPUT GAIN SLED AUTO GAIN FOCUS HIGH CUT FILTER A FOCUS HIGH CUT FILTER B FOCUS LOW BOOST FILTER A-H FOCUS LOW BOOST FILTER A-L FOCUS LOW BOOST FILTER B-H FOCUS LOW BOOST FILTER B-L FOCUS PHASE COMPENSATE FILTER A FOCUS DEFECT HOLD GAIN K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K1A K1B K1C K1D K1E K1F 4E 32 20 30 80 77 80 77 00 F1 7F 3B 81 44 7F 5E FOCUS PHASE COMPENSATE FILTER B FOCUS OUTPUT GAIN ANTI SHOCK INPUT GAIN FOCUS AUTO GAIN HPTZC / Auto Gain HIGH PASS FILTER A HPTZC / Auto Gain HIGH PASS FILTER B ANTI SHOCK HIGH PASS FILTER A HPTZC / Auto Gain LOW PASS FILTER B Fix TRACKING INPUT GAIN TRACKING HIGH CUT FILTER A TRACKING HIGH CUT FILTER B TRACKING LOW BOOST FILTER A-H TRACKING LOW BOOST FILTER A-L TRACKING LOW BOOST FILTER B-H TRACKING LOW BOOST FILTER B-L K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K2A K2B K2C K2D K2E K2F 82 44 18 30 7F 46 81 3A 7F 66 82 44 4E 1B 00 00 TRACKING PHASE COMPENSATE FILTER A TRACKING PHASE COMPENSATE FILTER B TRACKING OUTPUT GAIN TRACKING AUTO GAIN FOCUS GAIN DOWN HIGH CUT FILTER A FOCUS GAIN DOWN HIGH CUT FILTER B FOCUS GAIN DOWN LOW BOOST FILTER A-H FOCUS GAIN DOWN LOW BOOST FILTER A-L FOCUS GAIN DOWN LOW BOOST FILTER B-H FOCUS GAIN DOWN LOW BOOST FILTER B-L FOCUS GAIN DOWN PHASE COMPENSATE FILTER A FOCUS GAIN DOWN DEFECT HOLD GAIN FOCUS GAIN DOWN PHASE COMPENSATE FILTER B FOCUS GAIN DOWN OUTPUT GAIN NOT USED NOT USED CONTENTS Fix indicates that normal preset values should be used. ­ 29 ­ CXD2588Q/R CXD2588Q/R ADDRESS DATA CONTENTS K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K3A K3B K3C K3D K3E K3F 80 66 00 7F 6E 20 7F 3B 80 44 7F 77 86 0D 57 00 SLED INPUT GAIN (Only when TRK Gain Up2 is accessed with SFSK = 1.) ANTI SHOCK LOW PASS FILTER B NOT USED ANTI SHOCK HIGH PASS FILTER B-H ANTI SHOCK HIGH PASS FILTER B-L ANTI SHOCK FILTER COMPARATE GAIN TRACKING GAIN UP2 HIGH CUT FILTER A TRACKING GAIN UP2 HIGH CUT FILTER B TRACKING GAIN UP2 LOW BOOST FILTER A-H TRACKING GAIN UP2 LOW BOOST FILTER A-L TRACKING GAIN UP2 LOW BOOST FILTER B-H TRACKING GAIN UP2 LOW BOOST FILTER B-L TRACKING GAIN UP PHASE COMPENSATE FILTER A TRACKING GAIN UP PHASE COMPENSATE FILTER B TRACKING GAIN UP OUTPUT GAIN NOT USED K40 K41 K42 K43 K44 K45 K46 K47 K48 K49 K4A K4B K4C K4D K4E K4F 04 7F 7F 79 17 6D 00 00 02 7F 7F 79 17 54 00 00 TRACKING HOLD FILTER INPUT GAIN TRACKING HOLD FILTER A-H TRACKING HOLD FILTER A-L TRACKING HOLD FILTER B-H TRACKING HOLD FILTER B-L TRACKING HOLD FILTER OUTPUT GAIN TRACKING HOLD FILTER INPUT GAIN (Only when TRK Gain Up2 is a accessed with THSK = 1.) NOT USED FOCUS HOLD FILTER INPUT GAIN FOCUS HOLD FILTER A-H FOCUS HOLD FILTER A-L FOCUS HOLD FILTER B-H FOCUS HOLD FILTER B-L FOCUS HOLD FILTER OUTPUT GAIN NOT USED NOT USED ­ 30 ­ CXD2588Q/R CXD2588Q/R §1-4. Description of SENS Signals and Commands SENS output Microcomputer serial register (latching not required) SENS output $0X FZC - $1X As (Anti Shock) - $2X TZC - $30 to 37 SSTP - $38 AGOK - $38 XA VEBSY - $3904 TE Avrg Reg. 9bit $3908 FE Avrg Reg. 9bit $390C VC Avrg Reg. 9bit $391C TRVSC Reg. 9bit $391D FB Reg. 9bit $391F RFDC Avrg. Reg. 8bit $3A FBIAS count STOP - $3B to 3F SSTP - $4X XBUSY - $5X FOK - $6X, 7X, 8X, 9X 0 - $AX GFS - $BX 0 - $CX COUT frequency division - $DX 0 - $EX OV64 - $FX 0 - Output data length The SENS output can be read from the SQSO pin when SOUT = 0, SL1 = 1 and SL0 = 0. $38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement. SSTP is output in all other cases. Description of SENS Signals SENS output Contents XBUSY Low while the auto sequencer is in operation, high when operation terminates. FOK Outputs the same signal as the FOK pin. High for "focus OK". GFS High when the regenerated frame sync is obtained with the correct timing. COUT frequency division Counts the number of tracks with frequency division ratio set by $B. High when $C is latched, and toggles each time COUT is counted just for the frequency division ratio set by $B. OV64 Low when the EFM signal is lengthened by 64 channel clock pulses or more after passing through the sync detection filter. ­ 31 ­ CXD2588Q/R CXD2588Q/R The meaning of the data for each address is explained below. $4X commands AS3 AS2 AS1 AS0 CANCEL 0 0 0 0 FOCUS-ON 0 1 1 1 1 TRACK JUMP 1 0 0 RXF 10 TRACK JUMP 1 0 1 RXF 2 NTRACK JUMP 1 1 0 RXF N TRACK MOVE 1 1 1 RXF Command RXF = 0 FORWARD RXF = 1 REVERSE · When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted. · When the Track jump/Move commands ($48 to $4F) are canceled, $25 is sent and the auto sequence is interrupted. $5X commands Auto sequence timer setting Set timers: A, E, C, B Command D23 D22 D21 D20 Blind (A, E), Over flow (C) 0.18ms 0.09ms 0.05ms 0.02ms Brake (B) 0.36ms 0.18ms 0.09ms 0.05ms e.g.) D2 = D0 = 1, D3 = D1 = 0 (Initial Reset) A = E = C = 0.11ms B = 0.23ms $6X commands Auto sequence timer setting Set timer: D Command KICK (D) D23 D22 D21 D20 11.6ms 5.8ms 2.9ms 1.45ms e.g.) D3 = 0, D2 = D1 = D0 = 1 (Initial Reset) D = 10.15ms $7X commands Auto sequence track jump/move count setting (N) Data 1 Command Data 2 Data 3 Data 4 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 Auto sequence track jump 215 214 213 212 211 210 count setting 29 28 27 26 25 24 23 22 21 20 This command is used to set N when a 2N-track jump or N-track move is executed for auto sequence. · The maximum track count is 65,535, but note that with a 2N-track jump the maximum track jump count depends on the mechanical limitations of the optical system. · The number of tracks jumped is counted according to the COUT signals. ­ 32 ­ CXD2588Q/R CXD2588Q/R $8X commands Command Data 1 D3 D2 D1 Data 2 D0 D3 Data 3 D2 DOUT DOUT VCO Mode CDROM WSEL Mute ON/OFF SEL1 specification D1 D0 D3 D2 D1 D0 0 SOCT VCO SEL2 KSL3 KSL2 KSL1 KSL0 See "$BX Commands". Data 4 Data 5 Data 6 D3 D2 D1 D0 D3 D2 D1 D0 0 0 VCO2 THRU 0 0 0 0 0 D3 D2 D1 D0 TXON TXOUT OUTL1 OUTL0 Command bit C2PO timing Processing CDROM = 1 See Timing Chart 1-1. CDROM mode; average value interpolation and pre-value hold are not performed. CDROM = 0 See Timing Chart 1-1. Audio mode; average value interpolation and pre-value hold are performed. Command bit Processing DOUT Mute = 1 Digital Out output is muted. (DA output is not muted.) DOUT Mute = 0 If other mute conditions are not set, Digital Out is not muted. Command bit Processing DOUT ON/OFF = 1 Digital Out is output from the DOUT pin. DOUT ON/OFF = 0 Digital Out is not output from the DOUT pin. WSEL = 1 Sync protection window width ±26 channel clock1 Anti-rolling is enhanced. WSEL = 0 ±6 channel clock Sync window protection is enhanced. Command bit Application 1 In normal-speed playback, channel clock = 4.3218MHz. ­ 33 ­ CXD2588Q/R CXD2588Q/R Command bit Processing VCOSEL1 KSL3 KSL2 0 0 0 Multiplier PLL VCO1 is set to normal speed, and the output is 1/1 frequency-divided. 0 0 1 Multiplier PLL VCO1 is set to normal speed, and the output is 1/2 frequency-divided. 0 1 0 Multiplier PLL VCO1 is set to normal speed, and the output is 1/4 frequency-divided. 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Multiplier PLL VCO1 is set to normal speed, and the output is 1/8 frequency-divided. Multiplier PLL VCO1 is set to high speed1, and the output is 1/1 frequency-divided. Multiplier PLL VCO1 is set to high speed1, and the output is 1/2 frequency-divided. Multiplier PLL VCO1 is set to high speed1, and the output is 1/4 frequency-divided. Multiplier PLL VCO1 is set to high speed1, and the output is 1/8 frequency-divided. 1 Approximately twice the normal speed Command bit Processing VCOSEL2 KSL1 KSL0 0 0 0 Wide-band PLL VCO2 is set to normal speed, and the output is 1/1 frequency-divided. 0 0 1 Wide-band PLL VCO2 is set to normal speed, and the output is 1/2 frequency-divided. 0 1 0 Wide-band PLL VCO2 is set to normal speed, and the output is 1/4 frequency-divided. 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Wide-band PLL VCO2 is set to normal speed, and the output is 1/8 frequency-divided. Wide-band PLL VCO2 is set to high speed2, and the output is 1/1 frequency-divided. Wide-band PLL VCO2 is set to high speed2, and the output is 1/2 frequency-divided. Wide-band PLL VCO2 is set to high speed2, and the output is 1/4 frequency-divided. Wide-band PLL VCO2 is set to high speed2, and the output is 1/8 frequency-divided. 2 Approximately twice the normal speed ­ 34 ­ CXD2588Q/R CXD2588Q/R Command bit Processing VCO2 THRU = 0 V16M output is internally connected to VCKI. Set VCKI to low. VCO2 THRU = 1 V16M output is not internally connected. Input the clock from VCKI. These bits select the internal or external connection for the VCO2 used in CAV-W mode. Command bit Processing TXON = 0 When CD TEXT data is not demodulated, set TXON to 0. TXON = 1 When CD TEXT data is demodulated, set TXON to 1. See "$4-14. CD TEXT Data Demodulation" Command bit Processing TXOUT = 0 Various signals except for CD TEXT is output from the SQSO pin. TXOUT = 1 CD TEXT data is output from the SQSO pin. See "$4-14. CD TEXT Data Demodulation" Command bit Processing OUTL1 = 0 WFCK, XPCK C4M, WDCK and FSTO are output. The signal input to FSTI is supplied to the digital servo block. OUTL1 = 1 WFCK, XPCK C4M, WDCK and FSTO outputs are set to low. FSTO and FSTI are internally connected. Set FSTI to low. Command bit Processing OUTL0 = 0 PCMD, BCK, LRCK and EMPH are output. OUTL0 = 1 PCMD, BCK, LRCK and EMPH outputs are low. PCMD and PCMDI, BCK and BCKI, LRCK and LRCKI and EMPH and EMPHI are internally connected. Set PCMDI, BCKI, LRCKI and EMPHI to low. ­ 35 ­ ­ 36 ­ C2PO CDROM = 1 C2PO CDROM = 0 LRCK Timing Chart 1-1 C2 Pointer for lower 8bits Rch C2 Pointer C2 Pointer for upper 8bits Rch 16bit C2 Pointer C2 Pointer for lower 8bits Lch C2 Pointer C2 Pointer for upper 8bits Lch 16bit C2 Pointer If C2 Pointer = 1, data is NG CXD2588Q/R CXD2588Q/R CXD2588Q/R CXD2588Q/R Data 2 D0 and subsequent data are for DF/DAC function settings. $9X commands (OPSL1= 0) Data 1 Command Function specification D3 D2 D1 0 DSPB ON/OFF 0 Data 2 D0 D3 to D1 D0 0 Data 4 Data 3 D3 000 SYCOF D2 D1 D0 0 MCSL 0 0 D3 D2 ZDPL ZMUT OPSL1 D1 D0 - - Data 5 D3 Function specification Data 1 D2 D1 0 DSPB ON/OFF 0 D0 - - - Data 2 D0 and subsequent data are for DF/DAC function settings. $9X commands (OPSL1= 1) D3 D1 - Command D2 Data 3 Data 2 D0 D3 to D1 D0 0 Data 4 D3 000 SYCOF D2 D1 D0 1 MCSL 0 0 D3 D2 ZDPL ZMUT OPSL1 D1 D0 0 0 Data 5 D3 D2 D1 D0 0 DCOF 0 0 Processing Command bit DSPB = 1 Double-speed playback (CD-DSP block) DSPB = 0 Normal-speed playback (CD-DSP block) Processing Command bit SYCOF = 1 LRCK asynchronous mode SYCOF = 0 Normal operation Set SYCOF = 0 in advance when setting the $AX command LRWO to 1. Processing Command bit OPSL1 = 1 DCOF can be set. OPSL1 = 0 DCOF cannot be set. Command bit Processing MCSL = 1 DF/DAC block master clock selection. Crystal = 768Fs (33.8688MHz) MCSL = 0 DF/DAC block master clock selection. Crystal = 384Fs (16.9344MHz) ­ 37 ­ CXD2588Q/R CXD2588Q/R Processing Command bit ZDPL = 1 LMUT and RMUT pins are high when muted. ZDPL = 0 LMUT and RMUT pins are low when muted. See "Mute flag output" for the mute flag output conditions. Processing Command bit ZMUT = 1 Zero detection mute is on. ZMUT = 0 Zero detection mute is off. Processing Command bit DCOF = 1 DC offset is off. DCOF = 0 DC offset is on. DCOF can be set when OPSL1 = 1. Set DC offset to off when zero detection mute is on. Data 2 and subsequent data are for DF/DAC function settings. $AX commands (OPSL2 = 0) Command Audio CTRL Data 1 Data 3 Data 2 D3 D2 D1 D0 D3 D2 D1 0 0 Mute ATT 0 0 0 D0 D3 EMPH SMUT D2 0 OPSL2 Data 3 Data 4 Data 6 Data 5 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 - - - - Data 2 and subsequent data are for DF/DAC function settings. $AX commands (OPSL2 = 1) Command Audio CTRL Data 3 Data 2 Data 1 D3 D2 D1 D0 D3 D2 D1 0 0 Mute ATT 0 0 1 D0 D3 EMPH SMUT D2 0 OPSL2 Data 3 Data 4 Data 6 Data 5 D1 D0 D3 D2 D1 D0 D3 D2 D1 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 ­ 38 ­ D0 D3 D2 D1 D0 AD0 FMUT LRWO BSBST BBSL CXD2588Q/R CXD2588Q/R Processing Command bit Mute = 1 CD-DSP block mute is on. 0 data is output from the CD-DSP block. Mute = 0 CD-DSP block mute is off. Processing Command bit ATT = 1 CD-DSP block output is attenuated (­12dB). ATT = 0 CD-DSP block output attenuation is off. Meaning Command bit OPSL2 = 1 FMUT, LRWO, BSBST and BBSL can be set. OPSL2 = 0 FMUT, LRWO, BSBST and BBSL cannot be set. Processing Command bit EMPH = 1 De-emphasis is on. EMPH = 0 De-emphasis is off. If either the EMPHI pin or EMPH is high, de-emphasis is on. Processing Command bit SMUT = 1 Soft mute is on. SMUT = 0 Soft mute is off. If either the SMUT pin or SMUT is high, soft mute is on. Meaning Command bit AD10 to 0 Attenuation data. The attenuation data consists of 11 bits, and is set as follows. Attenuation data Audio output 400h 0dB 3FEh 3FDh : 001h ­0.0085dB ­0.0170dB 000h The attenuation data (AD10 to AD0) consists of 11bits, and can be set in 1024 different ways in the range of 000h to 400h. The audio output from 001h to 400h is obtained using the following equation. ­60.206dB ­ Audio output = 20log ­ 39 ­ Attenuation data [dB] 1024 CXD2588Q/R CXD2588Q/R Command bit Meaning FMUT = 1 Forced mute is on. FMUT = 0 Forced mute is off. FMUT can be set when OPSL2 = 1. Meaning Command bit LRWO = 1 Forced synchronization mode Note) LRWO = 0 Normal operation. LRWO can be set when OPSL2 = 1. Note) Synchronization is performed at the first falling edge of LRCK during reset, so there is normally no need to set this mode. However, synchronization can be forcibly performed by setting LRWO = 1. Processing Command bit BSBST = 1 Bass boost is on. BSBST = 0 Bass boost is off. BSBST can be set when OPSL2 = 1. Processing Command bit BBSL = 1 Bass boost is Max. BBSL = 0 Bass boost is Mid. BBSL can be set when OPSL2 = 1. ­ 40 ­ SL1 1 1 0 0 0 0 0 1 1 1 0 0 ­ 41 ­ 1 1 0 1 0 1 0 1 0 0 L1 SPOB L0 mode D Peak meter PER1 PER0 mode C PER2 VF1 PER1 C B A SubQ D SENS L2 0 PER2 VF2 PER3 Peak meter SubQ mode CPUSR D1 VF0 SPOA D2 SL0 SL0 PER0 SL1 D3 Data 1 mode B mode A SQCK XLAT 1 1 0 SOCT Serial bus CTRL Command $BX commands L3 WFCK PER3 VF3 PER4 0 D0 D2 D1 D0 L4 SCOR PER4 VF4 PER5 L5 GFS PER5 VF5 PER6 L6 GTOP PER6 VF6 PER7 L7 EMPH PER7 VF7 C1F1 R0 FOK 0 ALOCK C1F2 R1 LOCK C1F1 C1F1 0 0 0 C2F2 R2 R3 RFCK XRAOF C1F2 C1F2 C2F1 R4 C1F1 C2F1 C2F1 0 R5 C1F2 C2F2 C2F2 FOK R6 C2F1 0 0 GFS R7 C2F2 FOK FOK LOCK to the register when they are set at the falling edge of XLAT. Sub Q is loaded to the register with each SCOR, and Peak meter is loaded when a peak is detected. The SQSO pin output can be switched to the various signals by setting the SOCT command of $8X and the SL1 and SL0 commands of $BX. Set SQCK to high at the falling edge of XLAT. Except for Sub Q and peak meter, the signals are loaded TRM1 TRM0 MTSL1 MTSL0 D3 Data 2 GFS GFS LOCK LOCK EMPH ALOCK EMPH EMPH VF0 VF1 VF2 VF3 VF4 VF5 VF6 VF7 CXD2588Q/R CXD2588Q/R CXD2588Q/R CXD2588Q/R Signal Description PER0 to 7 RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB. FOK Focus OK GFS High when the frame sync and the insertion protection timing match. LOCK GFS is sampled at 460Hz; when GFS is high, a high signal is output. If GFS is low eight consecutive samples, a low signal is output. EMPH High when the playback disc has emphasis. ALOCK GFS is sampled at 460Hz; when GFS is high eight consecutive samples, a high signal is output. If GFS is low eight consecutive samples, a low signal is output. VF0 to 7 Used in CAV-W mode. Results of measuring the disc rotational velocity. (See Timing Chart 2-3.) VF0 = LSB, VF7 = MSB. SPOA, B SPOA and B pin inputs. WFCK Write frame clock output. SCOR High when either subcode sync S0 or S1 is detected. GTOP High when the sync protection window is open. RFCK Read frame clock output. XRAOF Low when the built-in 16K RAM exceeds the ±4 frame jitter margin. L0 to L7, R0 to R7 Peak meter register output. L0 to 7 are the left-channel and R0 to 7 are the right-channel peak data. L0 and R0 are LSB. C1F1 C1F2 0 0 1 1 C1 correction status C2F1 C2F2 No Error 0 0 No Error 0 Single Error Correction 1 0 Single Error Correction 1 Irretrievable Error 1 1 Irretrievable Error Processing Command bit CPUSR = 1 XLON pin is high. CPUSR = 0 XLON pin is low. ­ 42 ­ C2 correction status CXD2588Q/R CXD2588Q/R Peak meter XLAT SQCK SQSO L0 L1 L2 L3 L4 L5 L6 L7 R0 R1 R2 R3 R4 R5 R6 R7 (Peak meter) Setting the SOCT command of $8X to 0 and the SL1 and SL0 commands of $BX to 0 and 1, respectively, results in peak detection mode. The SQSO output is connected to the peak register. The maximum PCM data values (absolute value, upper 8bits) for the left and right channels can be read from SQSO by inputting 16 clocks to SQCK. Peak detection is not performed during SQCK input, and the peak register does not change during readout. This SQCK input judgment uses a retriggerable monostable multivibrator with a time constant of 270µs to 400µs. The time during which SQCK input is high should be 270µs or less. Also, peak detection is restarted 270µs to 400µs after SQCK input. The peak register is reset with each readout (16 clocks input to SQCK). The maximum value in peak detection mode is detected and held in this status until the next readout. When switching to peak detection mode, readout should be performed one time initially to reset the peak register. Peak detection can also be performed for previous value hold and average value interpolation data. Traverse monitor count value setting These bits are set when monitoring the traverse condition of the SENS output according to the COUT frequency division. Command bit Processing TRM1 TRM0 0 0 1/64 frequency division 0 1 1/128 frequency division 1 0 1/256 frequency division 1 1 1/512 frequency division Monitor output switching The monitor output can be switched to the various signals by setting the MTSL1 and MTSL0 commands of $B. Output data Symbol Command bit XUGF XPCK GFS C2PO MTSL1 MTSL0 0 0 XUGF XPCK GFS C2PO 0 1 MNT1 MNT0 MNT3 C2PO 1 0 RFCK XPCK XROF GTOP ­ 43 ­ CXD2588Q/R CXD2588Q/R $CX commands D3 Command Servo coefficient setting D2 D1 D0 Gain MDP1 Gain MDP0 Gain MDS1 Gain MDS0 Gain CLVS CLV CTRL ($DX) · CLV mode gain setting: GCLVS Gain MDS1 Gain MDS0 Gain CLVS GCLVS 0 0 0 ­12dB 0 0 1 ­6dB 0 1 0 ­6dB 0 1 1 0dB 1 0 0 0dB 1 0 1 +6dB · CLVP mode gain setting: GMDP: GMDS Gain MDP1 Gain MDP0 GMDP Gain MDS1 Gain MDS0 GMDS 0 0 ­6dB 0 0 ­6dB 0 1 0dB 0 1 0dB 1 0 +6dB 1 0 +6dB ­ 44 ­ CXD2588Q/R CXD2588Q/R $DX commands Data 1 Command Data 3 Data 2 D3 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 0 CLV CTRL D2 TB TP Gain CLVS VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0 See the $CX commands. Command bit Description TB = 0 Bottom hold at a cycle of RFCK/32 RFCK/32 in CLVS mode. TB = 1 Bottom hold at a cycle of RFCK/16 RFCK/16 in CLVS mode. TP = 0 Peak hold at a cycle of RFCK/4 in CLVS mode. TP = 1 Peak hold at a cycle of RFCK/2 in CLVS mode. Command bit VP0 to 7 = F0 (H) : VP0 to 7 = E0 (H) : VP0 to 7 = C0 (H) The rotational velocity R of the spindle can be expressed with the following equation. Description Playback at half (normal) speed to Playback at normal (double) speed to Playback at (quadruple) speed R= 256 ­ n 32 R: Relative velocity at normal speed = 1 n: VP0 to 7 setting value Note) · Values in parentheses are for when DSPB is 1. · Values when crystal is 16.9344MHz and XTSL is low or when crystal is 33.8688MHz and XTSL is high. · VP0 to 7 setting values are valid in CAV-W mode. 4 R ­ Relative velocity [multiple] 3.5 3 2.5 2 PB =1 DS 1.5 1 DSP B=0 0.5 F0 E0 VP0 to 7 setting value [HEX] Fig. 1-1 ­ 45 ­ D0 C0 CXD2588Q/R CXD2588Q/R $EX commands Data 1 Command Data 2 D3 D1 CM3 CLV mode D2 CM2 CM1 D0 D2 D3 Data 3 D1 D0 CM0 EPWM SPDC ICAP Command bit Mode D3 SFSL VC2C D2 D1 D0 HIFC LPWR VPON Description CM3 CM2 CM1 CM0 0 0 0 0 STOP Spindle stop mode.1 1 0 0 0 KICK Spindle forward rotation mode.1 1 0 1 0 BRAKE Spindle reverse rotation mode. Valid only when LPWR = 0 in any mode.1 1 1 1 0 CLVS Rough servo mode. When the RF-PLL circuit isn't locked, this mode is used to pull the disc rotations within the RFPLL capture range. 1 1 1 1 CLVP PLL servo mode. 0 1 1 0 CLVA Automatic CLVS/CLVP switching mode. Used for normal playback. 1 See Timing Charts 1-2 to 1-6. Command bit EPWM SPDC Mode ICAP SFSL VC2C HIFC LPWR VPON Description 0 0 0 0 0 0 0 0 CLV-N Crystal reference CLV servo. 0 0 0 0 1 1 0 0 CLV-W Used for normal-speed playback in CLV-W mode.2 0 1 1 0 0 1 0 1 CAV-W Spindle control with VP0 to 7. 1 0 1 0 0 1 0 1 CAV-W Spindle control with the external PWM. 2 Figs. 3-1 and 3-2 show the control flow with the microcomputer software in CLV-W mode. ­ 46 ­ CXD2588Q/R CXD2588Q/R Data 4 Command SPD mode D3 D2 Gain Gain CAV1 CAV0 Gain CAV1 Gain CAV0 Gain 0 0 1 0 1 0 · This sets the gain when controlling the spindle with the phase comparator in CAV-W mode. ­12dB 1 0 ­6dB 1 D0 0dB 0 D1 ­18dB Mode BRAKE 1-3 (b) 1-3 (c) 1-4 (a) BRAKE 1-4 (b) 1-4 (c) 1-5 (a) BRAKE 1-5 (b) STOP 1-5 (c) KICK 1-6 (a) BRAKE 1-6 (b) STOP 1 1-3 (a) KICK CAV-W 1-2 (c) STOP 0 1-2 (b) KICK 1 BRAKE STOP CLV-W 1-2 (a) KICK 0 Timing chart STOP 0 Command KICK CLV-N LPWR 1-6 (c) Mode LPWR Timing chart CLV-N 0 1-7 0 1-8 1 1-9 0 1-10 (EPWM = 0) 1 1-11 (EPWM = 0) 0 1-12 (EPWM = 1) 1 1-13 (EPWM = 1) CLV-W CAV-W ­ 47 ­ CXD2588Q/R CXD2588Q/R Timing Chart 1-2 CLV-N mode LPWR = 0 KICK BRAKE Z H MDP STOP MDP Z MDP L (a) KICK (b) BRAKE Z (c) STOP Timing Chart 1-3 CLV-W mode (when following the spindle rotational velocity) LPWR = 0 KICK MDP BRAKE STOP Z H MDP Z MDP L (b) BRAKE (a) KICK Z (c) STOP Timing Chart 1-4 CLV-W mode (when following the spindle rotational velocity) LPWR = 1 KICK BRAKE H MDP Z MDP Z (a) KICK STOP MDP (b) BRAKE Z (c) STOP Timing Chart 1-5 CAV-W mode LPWR = 0 KICK BRAKE STOP H MDP MDP (a) KICK L MDP (b) BRAKE Z (c) STOP Timing Chart 1-6 CAV-W mode LPWR = 1 KICK MDP H (a) KICK BRAKE MDP Z (b) BRAKE ­ 48 ­ STOP MDP Z (c) STOP CXD2588Q/R CXD2588Q/R Timing Chart 1-7 CLV-N mode LPWR = 0 n · 236 (ns) n = 0 to 31 Acceleration MDP Z 132kHz Deceleration 7.6µs Timing Chart 1-8 CLV-W mode LPWR = 0 Acceleration MDP Z 264kHz 3.8µs Deceleration Timing Chart 1-9 CLV-W mode LPWR = 1 Acceleration MDP Z 264kHz 3.8µs The BRAKE pulse is masked when LPWR = 1. Timing Chart 1-10 CAV-W mode EPWM = LPWR = 0 Acceleration MDP Z 264kHz 3.8µs Deceleration Timing Chart 1-11 CAV-W mode EPWM = LPWR = 1 Acceleration MDP Z 264kHz 3.8µs The BRAKE pulse is masked when LPWR = 1. ­ 49 ­ CXD2588Q/R CXD2588Q/R Timing Chart 1-12 CAV-W mode EPWM = 1, LPWR = 0 H PWMI L Acceleration H MDP L Deceleration Timing Chart 1-13 CAV-W mode EPWM = LPWR = 1 H PWMI L Acceleration H MDP Z The BRAKE pulse is masked when LPWR = 1. ­ 50 ­ CXD2588Q/R CXD2588Q/R §2. Subcode Interface This section explains the subcode interface. There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read from SBSO by inputting EXCK to the CXD2588Q/R CXD2588Q/R. Sub Q can be readout after checking the CRC of the 80 bits in the subcode frame. Sub Q can be readout from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes correctly and CRCF is high. §2-1. P to W Subcode Readout Data can be readout by inputting EXCK immediately after WFCK falls. (See Timing Chart 2-1.) §2-2. 80-bit Sub Q Readout Fig. 2-1 shows the peripheral block of the 80-bit Sub Q register. · First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check circuit. · 96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80 bits are loaded into the parallel/serial register. When SQSO goes high 400µs (monostable multivibrator time constant) or more after subcode readout, the CPU determines that new data (which passed the CRC check) has been loaded. · The CRCF reset is performed by inputting SQCK. When the subcode data is discontinuous after track jump, etc. CRCF is reset by inputting SQCK. Then, if CRCF =1, the CPU determines that the new data has been loaded. · When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of bytes is the same, the bits within the bytes are now ordered LSB first. · Once the 80-bit data load is confirmed, SQCK is input so that the data can be read. The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low. · The retriggerable monostable multivibrator has a time constant from 270µs to 400µs. When the duration when SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the serial/parallel register is not loaded into the parallel/serial register. · While the monostable multivibrator is being reset, data cannot be loaded in the 80-bit parallel/serial register. In other words, while reading out with a clock cycle shorter than this time constant, the register will not be rewritten by CRCOK and others. (See Timing Chart 2-2.) · The high and low intervals for SQCK should be between 750ns and 120µs. ­ 51 ­ CXD2588Q/R CXD2588Q/R Timing Chart 2-1 Internal PLL clock 4.3218 ± MHz WFCK SCOR EXCK 400ns max SBSO S0 · S1 Q R WFCK SCOR EXCK SBSO S0·S1 Q R S T U V W S0·S1 Same P1 Q R S T U V W P1 Same Sub Code P.Q.R.S.T.U.V.W Read Timing ­ 52 ­ P2 P3 SUBQ SI LD H G F E D C B A A B C D E F G H SIN Order Inversion ­ 53 ­ CRCC SUBQ 8 LD 8 (AMIN) 80-bit P/S Register 8 80-bit S/P Register Mono/Multi LD (ASEC) SHIFT LD (AFRAM) 8 8 8 8 LD Mix CRCF 8 SHIFT SQSO 8 ADDRS CTRL LD Fig. 2-1. Block Diagram SQCK SO CXD2588Q/R CXD2588Q/R LD LD ­ 54 ­ SQSO SQCK CRCF Mono/multi (Internal) SQCK SQSO SCOR WFCK Timing Chart 2-2 CRCF1 1 2 Order Inversion ADR1 93 2 1 94 Determined by mode 3 92 91 ADR2 ADR3 CTL0 270µs to 400µs for SQCK = High Registere load forbidder 80 clocks 750ns to 120µs 300ns max ADR0 3 95 L CTL1 96 CTL2 97 CTL3 CRCF2 98 CXD2588Q/R CXD2588Q/R CXD2588Q/R CXD2588Q/R Timing Chart 2-3 Measurement interval (approximately 3.8µs) Reference window (132.2kHz) Measurement pulse (VCKI/2) Measurement counter Load m VF0 to 7 The relative velocity R of the disc can be expressed with the following equation. R= m+1 32 (R: Relative velocity, m: Measurement results) VF0 to 7 is the result obtained by counting VCKI/2 pulses while the reference signal (132.2kHz) generated from the crystal (384Fs) is high. This count is 31 when the disc is rotating at normal speed and 63 when it is rotating at double speed (when DSPB is low). ­ 55 ­ CXD2588Q/R CXD2588Q/R §3. Description of Modes This LSI has three basic operating modes using a combination of spindle control and the PLL. The operations for each mode are described below. §3-1. CLV-N Mode This mode is compatible with the CXD2507AQ CXD2507AQ, and operation is the same as for the conventional control. The PLL capture range is ±150kHz. §3-2. CLV-W Mode This is the wide capture range mode. This mode allows the PLL to follow the rotational velocity of the disc. This rotational following control has two types: using the built-in VCO2 or providing an external VCO. The spindle is the same CLV servo as for the conventional series. Operation using the built-in VCO2 is described below. (When using an external VCO, input the signal from the VPCO pin to the low-pass filter, use the output from the low-pass filter as the control voltage for the external VCO, and input the oscillation output from the VCO to the VCKI pin.) When starting to rotate the disc and/or speeding up to the lock range from the condition where the disc is stopped, CAV-W mode should be used. Specifically, first send $E6650 E6650 to set CAV-W mode and kick the disc, then send $E60C0 E60C0 to set CLV-W mode if ALOCK is high, which can be readout serially from the SQSO pin. CLV mode can be used while ALOCK is high. The microcomputer monitors the serial data output, and must return the operation to the speed adjusting state (CAV-W mode) when ALOCK becomes low. The control flow according to the microcomputer software is shown in Fig. 3-2. In CLV-W mode (normal), low power consumption is achieved by setting LPWR to high. Control was formerly performed by applying acceleration and deceleration pulses to the spindle motor. However, when LPWR is set to high, deceleration pulses are not output, thereby achieving low power consumption mode. Note) The capture range for CLV-W mode has theoretically the range up to the signal processing limit. §3-3. CAV-W Mode This is CAV mode. In this mode, the external clock is fixed and it is possible to control the spindle to variable rotational velocity. The rotational velocity is determined by the VP0 to 7 setting values or the external PWM. When controlling the spindle with VP0 to 7, setting CAV-W mode with the $E6650 E6650 command and controlling VP0 to 7 with the $DX commands allows the rotational velocity to be varied from low speed to double speed. (See the $DX commands.) Also, when controlling the spindle with the external PWM, the PWMI pin is binary input which becomes KICK during high intervals and BRAKE during low intervals. The microcomputer can know the rotational velocity using V16M. The reference for the velocity measurement is a signal of 132.2kHz obtained by 1/128-frequency dividing the crystal (384Fs). The velocity is obtained by counting V16M/2 V16M/2 pulses while the reference is high, and the result is output from the new CPU interface as 8 bits (VF0 to 7). These measurement results are 31 when the disc is rotating at normal speed or 63 when it is rotating at double speed. These values match those of the 256-n for control with VP0 to 7. In CAV-W mode, the spindle is set to the desired rotational velocity and the operation speed for the entire system follows this rotational velocity. Therefore, the cycles for the Fs system clock, PCM data and all other output signals from this LSI change according to the rotational velocity of the disc. Note) The capture range for this mode is theoretically up to the signal processing limit. ­ 56 ­ CXD2588Q/R CXD2588Q/R CAV-W CLV-W Operation mode Rotational velocity CLVS CLVP Spindle mode Target velocity KICK Time LOCK ALOCK Fig. 3-1. Disc Stop to Normal Condition in CLV-W Mode CLV-W Mode CLV-W MODE START KICK $E8000 E8000 Mute OFF $A0XXXXX CAV-W $E6650 E6650 (CLVA) NO ALOCK = H ? YES CLV-W $E60C0 E60C0 (CLVA) (WFCK PLL) YES ALOCK = L ? NO Fig. 3-2. CLV-W Mode Flow Chart ­ 57 ­ CXD2588Q/R CXD2588Q/R §4. Description of Other Functions §4-1. Channel Clock Regeneration by the Digital PLL Circuit · The channel clock is necessary for demodulating the EFM signal regenerated by the optical system. Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that is the channel clock, is necessary. In an actual player, the PLL is necessary to regenerate the channel clock because the fluctuation in the spindle rotation alters the width of the EFM signal pulses. The block diagram of this PLL is shown in Fig. 4-1. The CXD2588Q/R CXD2588Q/R has a built-in three-stage PLL. · The first-stage PLL is for the wide-band PLL. When the internal VCO2 is used, an external LPF is necessary; when not using the internal VCO2, external LPF and VCO are required. The output of this first-stage PLL is used as a reference for all clocks within the LSI. · The second-stage PLL generates the high-frequency clock needed by the third-stage digital PLL. · The third-stage PLL is a digital PLL that regenerates the actual channel clock. · A new digital PLL has been provided for CLV-W mode to follow the rotational velocity of the disc in addition to the conventional secondary loop. ­ 58 ­ CXD2588Q/R CXD2588Q/R Block Diagram 4-1 CLV-W CAV-W Spindle rotation information 1/32 XTSL 1/2 1/n Phase comparator 1/2 Selector OSC VPCO CLV-N CLV-W CAV-W /CLV-N Microcomputer control n = 1 to 256 (VP7 to 0) 1/K (KSL1, 0) LPF VCOSEL2 VCTL VCO2 V16M 2/1 MUX VCKI VPON 1/M 1/N Phase comparator X'tal PCO FILI FILO 1/K (KSL3, 2) CLTV VCO1 VCOSEL1 Digital PLL RFPLL CXD2588Q/R CXD2588Q/R ­ 59 ­ CXD2588Q/R CXD2588Q/R §4-2. Frame Sync Protection · In normal-speed playback, a frame sync is recorded approximately every 136µs (7.35kHz). This signal is used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be recognized, the data is processed as error data because the data cannot be recognized. As a result, recognizing the frame sync properly is extremely important for improving playability. · In the CXD2588Q/R CXD2588Q/R, window protection and forward protection/backward protection have been adopted for frame sync protection. These functions achieve very powerful frame sync protection. There are two window widths: one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is fixed to 13, and the backward protection counter to 3. Concretely, when the frame sync is being played back normally and then cannot be detected due to scratches etc., a maximum of 13 frames are inserted. If the frame sync cannot be detected for 13 frames or more, the window opens to resynchronize the frame sync. In addition, immediately after the window opens and the resynchronization is executed, if a proper frame sync cannot be detected within 3 frames, the window opens immediately. §4-3. Error Correction · In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code is created with 28-byte information and 4-byte C1 parity. For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed-Solomon codes with a minimum distance of 5. · The CXD2588Q/R CXD2588Q/R's SEC strategy uses powerful frame sync protection and C1 and C2 error correction to achieve high playability. · The correction status can be monitored externally. See Table 4-2. · When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an average value interpolation was made for the data. MNT3 MNT1 MNT0 Description 0 0 0 No C1 errors 0 0 1 One C1 error corrected 0 1 1 C1 correction impossible 1 0 0 No C2 errors 1 0 1 One C2 error corrected 1 1 0 C2 correction impossible Table 4-2. ­ 60 ­ CXD2588Q/R CXD2588Q/R Timing Chart 4-3 Normal-speed PB t = Dependent on error condition MNT3 C1 correction C2 correction MNT1 MNT0 Strobe Strobe §4-4. DA Interface · The CXD2588Q/R CXD2588Q/R DA interface is as described below. This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel. ­ 61 ­ R0 1 2 3 ­ 62 ­ PCMD BCK (4.23M) LRCK (88.2k) R0 1 2 4 5 Lch MSB (15) Lch MSB (15) 48-bit slot Double-Speed Playback PCMD BCK (2.12M) LRCK (44.1k) 48-bit slot Normal-Speed Playback Timing Chart 4-4 6 7 8 9 L14 10 L13 11 L12 12 L0 24 L11 L9 Rch MSB L10 L8 L7 L6 L5 L4 L3 L2 L1 L0 24 RMSB CXD2588Q/R CXD2588Q/R CXD2588Q/R CXD2588Q/R §4-5. Digital Out There are three Digital Out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD2588Q/R CXD2588Q/R supports type 2 form 1. Sub Q data which are matched twice in succession after a CRC check are input to the first four bits (bits 0 to 3) of the channel status. Digital Out C bit 0 0 ID0 16 1 2 3 0 4 5 6 7 8 9 10 11 12 13 14 15 0 From sub Q 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0 ID1 COPY Emph 0 0 0 32 48 0 176 Bits 0 to 3 Sub Q control bits that matched twice with CRCOK Bit 29 1 when VPON = 1 Table 4-5. §4-6. Servo Auto Sequence This function performs a series of controls, including auto focus and track jumps. When the auto sequence command is received from the CPU, auto focus, 1-track jump, 2N-track jump and N-track move are executed automatically. The commands which enable transfer to the CXD2588Q/R CXD2588Q/R during the execution of auto sequence are $4X to $EX. When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of 100µs after that point. ­ 63 ­ CXD2588Q/R CXD2588Q/R (a) Auto focus ($47) Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on. If $47 is received from the CPU, the focus servo is turned on according to Fig. 4-3. The auto focus starts with focus search-up, and note that the pickup should be lowered beforehand (focus search down). In addition, blind E of register 5 is used to eliminate FZC chattering. Concretely, the focus servo is turned on at the falling edge of FZC after FZC has been continuously high for a longer time than E. Auto focus Focus search up FOK=H NO YES (Check whether FZC is continuously high for the period of time E set with register 5.) FZC = H NO YES FZC = L NO YES Focus servo ON END Fig. 4-6-(a). Auto Focus Flow Chart ­ 64 ­ CXD2588Q/R CXD2588Q/R $47latch XLAT FOK (FZC) BUSY Command for DSSP Blind E $08 $03 Fig. 4-6-(b). Auto Focus Timing Chart (b) Track jump 1, 10 and 2N-track jumps are performed respectively. Always use this when the focus, tracking, and sled servos are on. Note that tracking gain-up and braking-on should be sent beforehand because they are not involved in this sequence. · 1-track jump When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance with Fig. 4-7. Set blind A and brake B with register 5. · 10-track jump When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed in accordance with Fig. 4-8. The principal difference from the 1-track jump is to kick the sled. In addition, after kicking the actuator, when 5 tracks have been counted through COUT, the brake is applied to the actuator. Then, when the actuator speed is found to have slowed up enough (determined by the COUT cycle becoming longer than the overflow C set with register 5), the tracking and sled servos are turned on. · 2N-track jump When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in accordance with Fig. 4-9. The track jump count N is set with register 7. Although N can be set to 216 tracks, note that the setting is actually limited by the actuator. COUT is used for counting the number of jumps. Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "D", set with register 6. · N-track move When $4E ($4F for REV) is received from the CPU, a FWD (REV) N-track move is performed in accordance with Fig. 4-10. N can be set to 216 tracks. COUT is used for counting the number of jumps. The N-track move is executed only by moving the sled, and is therefore suited for moving across several thousand to several ten-thousand tracks. ­ 65 ­ CXD2588Q/R CXD2588Q/R Track (REV kick for REV jump) Track FWD kick sled servo OFF WAIT (Blind A) COUT = NO YES Track REV kick (FWD kick for REV jump) WAIT (Brake B) Track, sled servo ON END Fig. 4-7-(a). 1-Track Jump Flow Chart $48 (REV = $49) latch XLAT COUT BUSY Brake B Blind A Command for DSSP $28 ($2C) $2C ($28) Fig. 4-7-(b). 1-Track Jump Timing Chart ­ 66 ­ $25 CXD2588Q/R CXD2588Q/R 10 Track Track, sled FWD kick WAIT (Blind A) COUT = 5 ? NO (Counts COUT × 5) NO (Check whether the COUT cycle is longer than ove