CXA3271AGE E00Y20-PS 65VDD 35VDD 30PIN 05MAX 25MAX LLGA-30P-01 - Datasheet Archive

 

Fingerprint Sensor Description The CXA3271AGE is an electrostatic capacitance method fingerprint sensor. This monolithic IC

 

CXA3271AGE CXA3271AGE Fingerprint Sensor Description The CXA3271AGE CXA3271AGE is an electrostatic capacitance method fingerprint sensor. This monolithic IC integrates the sensor block, sense amplifier (3-bit gain adjustment), sample-andhold, output amplifier and output buffer needed to acquire fingerprint images, as well as the timing generator for determining the operation of these functions onto a single chip. 30 pin LLGA (Plastic) Features · Electrostatic capacitance type sensor (charge transfer method) · Number of pixels: 192 × 128 · 317 DPI · Low power consumption (50mW or less) · Single 3.3V power supply · Sensor gain control: 3 bits · S/N ratio improved by on-chip sensor block parasitic capacitance cancel function Applications Fingerprint verification units Structure Silicon gate CMOS IC Absolute Maximum Ratings (Ta = 25°C) VSS ­ 0.5 to +7.0 · Supply voltage AVDD, DVDD · Input voltage VI VSS ­ 0.5 to VDD + 0.5 · Output voltage VO VSS ­ 0.5 to VDD + 0.5 · Operating temperature Topr ­20 to +75 · Storage temperature Tstg ­25 to +125 · Allowable power dissipation PD 1100 Recommended Operating Conditions · Supply voltage AVDD, DVDD · Ambient operating temperature Ta 3.15 to 3.45 0 to +50 V V V °C °C mW V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. ­1­ E00Y20-PS E00Y20-PS CXA3271AGE CXA3271AGE Block Diagram C_SP UC UC SENSOR . 128 . CLK (D/I) Timing Generator XSP (D/I) UC 128 Column Shift Register C_CLK UC UC ADCLK (D/O) UC UC UC UC . 192 . UC UC UC UC 192 S_CNT Sense AMP (×192) 3-bit DAC DI (D/I) 192 Load S/H & SW (×192) Output Buffer AOUT (A/O) 192 R_SP Row Shift Register VOS (Bias) R_CLK ­2­ 3 CXA3271AGE CXA3271AGE Detailed Block Diagram VCS_O Pin Symbol BIAS_O 7C 27 AVSS (P/S) 7D 26 AOUT (A/O) 7E 25 VCS_O (Bias) 7F 24 VOS (Bias) 6B C_COUT SR_C 23 VH (Bias) 6C SR (1:192) 22 VM (Bias) 6D 21 VL (Bias) 6E 20 VCS_S (Bias) 6F 19 DVDD (P/S) 5B 18 DVSS (P/S) 5C 17 DVSS (P/S) 5D 16 CSRO (D/O) 5E 15 RSRO (D/O) 5F 14 ADCLK (D/O) 4F 13 C_CK (D/O) 4E 12 C_CLK (D/I) 4D 11 CLK (D/I) 4C 10 HD (D/I) 4B 9 XSP (D/I) 3F 8 DI2 (D/I) 3E 7 DI1 (D/I) 3D 6 DI0 (D/I) 3C 5 MODE (D/I) 3B 4 TEST2 (D/I) 2F 3 TEST1 (D/I) 2E 2 AVSS (P/S) 2D 1 AVDD (P/S) 2C BUF C_CLK VOS VCS_O AVDD (P/S) OAMP 28 C_LOG SR (1:128) N C_CO XSP DCLK R_SP CLK R_LOG 192 SC (1:192) N SC (1:192) 192 SC (1:192) S (3:5) S (3:5) N SR_S VH, VM, VL VCS_S OUT ­3­ VCS_S BIAS_REF BIAS_SA IN VOS VOS AMP VH VM VL DA 3 6 8 VS (1:8) N VS (3:8) DATEST VH, VM, VL S1, S2, S11 S3CNT SR_C DI (0:2) DATEST VS (3:8) C_CR VS (1:8) N DEC XSP IN OUT R_SP 2 DSELG TEST (1:2) DSELN SC (1:192) N S (6:7) OUT C (1:192) 192 IN_N (1:192) UC UC UC . 192 . UC UC UC S (3:5) S (3:5) N DCLK SR_S SR_C DA AMP C_SP SIN, S2N, S11, S11N XSP MODE S3CNT TG HD C_CLK C_CK SENSOR (UC) UC UC UC UC SR (1:192) . 128 . UC UC UC . 192 (Dummy) . UC UC UC SR (1:128) N S (6:7) N 128 SAMP (192) 128 UC C_SP LAND No. CXA3271AGE CXA3271AGE Pin Description Serial No. Land No. Symbol Description I/O 2B SUB Power Substrate electrode (chip rear surface electrode) 3.3V. 1 2C AVDD Power Analog power supply 3.3V. 2 2D AVSS Power Analog GND. 3 2E TEST1 D/I Test mode selection. Connect to GND. 4 2F TEST2 D/I Test mode selection. Connect to GND. 5 3B MODE D/I Connect to GND. 6 3C DI0 D/I Gain setting input. (LSB) 7 3D DI1 D/I Gain setting input. 8 3E DI2 D/I Gain setting input. (MSB) 9 3F XSP D/I Sense start pulse input (negative pulse). The column and row shift registers and the timing generator are cleared by this signal. 10 4B HD D/I Connect to GND. 11 4C CLK D/I Main clock. (1 to 2MHz) 12 4D C_CLK D/I Column shift register clock. Connect to C_CK (4E). 13 4E C_CK D/O Column shift register clock output. Connect to C_CLK (4D). 14 4F ADCLK D/O Outputs the internally delayed input clock. 19 5B DVDD Power Digital power supply 3.3V. 18 5C DVSS Power Digital GND. 17 5D DVSS Power Digital GND. 16 5E CSRO D/O Column shift register final output. (Connection is not required.) 15 5F RSRO D/O Row shift register final output. (Connection is not required.) 24 6B VOS A/O Output amplifier reference voltage monitor. (1.65V) 23 6C VH A/O Sensor charge voltage monitor. (1 LSB = 80mV) Adjustable within the range of 1.92 to 2.48V by the three bits DI[0:2]. 22 6D VM A/O Sense amplifier reference voltage monitor. (1.85V) 21 6E VL A/O Dummy cell charge voltage monitor for canceling parasitic capacitance. VL = 2VM ­ VH 20 6F VCS_S A/O Sense amplifier current source bias monitor. (Do not connect.) 7B SUB Power Substrate electrode (chip rear surface electrode) 3.3V. 28 7C AVDD Power Analog power supply 3.3V. 27 7D AVSS Power Analog GND. 26 7E AOUT A/O Sensor output. 25 7F VCS_O A/O Output amplifier and output buffer current source bias monitor. (Do not connect.) ­4­ CXA3271AGE CXA3271AGE Electrical Characteristics 1. DC Characteristics Item (Vss = 0V, Ta = 25°C) Min. Conditions Symbol Typ. Max. Unit Analog supply voltage AVDD 3.15 3.3 3.45 V Digital supply voltage DVDD 3.15 3.3 3.45 V Input voltage (High) VIH CMOS input cell 0.7VDD VDD V Input voltage (Low) VIL CMOS input cell Vss 0.3VDD V Output voltage (High) CMOS VIH VDD = 3.3V, IOH = ­800µA 2.8 3.3 V Output voltage (Low) CMOS VIL VDD = 3.3V, IOL = 2.4mA 0 0.4 V Input leak current IL VDD = 3.3V, CMOS input pin (3.3V/0V) ­5 5 µA Output voltage VH VDD = 3.3V (D0 D1 D2) = (L L L) 1.92 V Output voltage VH VDD = 3.3V (D0 D1 D2) = (H H H) 2.48 V Output voltage VL VDD = 3.3V (D0 D1 D2) = (L L L) 1.76 V Output voltage VL VDD = 3.3V (D0 D1 D2) = (H H H) 1.2 V Output voltage VM VDD = 3.3V (D0 D1 D2) = ( ) 1.75 1.84 1.92 V Output voltage VOS VDD = 3.3V (D0 D1 D2) = ( ) 1.55 1.65 1.75 V Current consumption IDD VDD = 3.3V 5 7.5 11 mA 2. AC Characteristics Item Clock input period (VDD = 3.3V, VSS = 0V, Ta = 25°C) Applicable pins Conditions Symbol CLK Min. Output voltage Water Level Max. 400 Number of sensor defects Output voltage Air Level Typ. Unit ns 5 AOUT 1 AOUT 2 Defects 1000 1550 mV 250 450 mV 1 Output voltage Air Level means the output level in the condition where nothing is placed against the sensor surface (in other words, in air). This rating value is obtained by measuring 32 points within one line of the sensor output and then taking the average. The gain setting for this measurement is (011). 2 Output voltage Water Level specifies the degree to which the output level changes from the Air Level when a drop of water is placed on the sensor surface. However, it is unrealistic to place a drop of water on each sensor surface when sorting products, so 32 virtual capacitors (parasitic capacitance equal to the level when a drop of water is placed on the surface) are built into the sensor chip, and the average of these output values is calculated. The difference from the Air Level noted above becomes the Water Level. The gain setting for this measurement is (011). ­5­ CXA3271AGE CXA3271AGE Electrical Characteristics Measurement Circuit Digital input pin Digital output pin Analog output pin AVDD AVSS 27 VCS_O/O VH/O 0.1µF VL/O 0.1µF DVDD 28 25 26 23 24 21 22 VOS/O VM/O 19 20 17 16 13 14 11 12 9 10 7 8 5 6 3 4 1 2 0.1µF VCS_S/O 18 15 0.1µF DVSS 1.0µF AOUT/O DVSS RSRO/O CSRO/O C_CK/O ADCLK/O S1 CLK/I C_CLK/I XSP/I HD/I DI1/I DI2/I MODE/I TEST1/I AVDD 1.0µF DI0/I TEST2/I AVSS Vcc 3.3V 30pF or more is added to each pin. ­6­ CXA3271AGE CXA3271AGE Application Circuit Flash Registered data Microcomputer During registration DRAM During verification Fingerprint sensor chip ASIC Binary value, verification 8-bit A/D Verification results Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. ­7­ CXA3271AGE CXA3271AGE Description of Operation · Fingerprint sensor principle The principle of this newly developed fingerprint sensor is described below (Fig. 1). The sensor block contains an array of metal electrodes which are covered on top by an insulating film (overcoat). When a finger (which is conductive matter) is placed directly against this surface, the three elements of the metal electrode, the insulating film and the finger form a capacitor. The difference between the fingerprint ridges and valleys is the difference in distance to the metal electrodes, and becomes the difference in the capacitance values of the individually formed capacitors. (The ridge capacitance values are determined by the dielectric constant of the insulating film, but the valleys contain air in addition to this, making the difference between the ridge and valley capacitance values even greater than the difference in distance.) Using this principle, by applying a constant voltage to all metal electrodes, the charge level accumulated in each electrode differs, making it possible to output the unevenness of the fingerprint as an electric signal by transferring and converting these charges to voltages. Ridge Valley Fingerprint unevenness Overcoat Metal electrode Inter-layer film Si Fig. 1 ­8­ CXA3271AGE CXA3271AGE S4 S6 Cf1 Cf2 Cs Sr Voi Vsl S5 Vcel Sc S7 S3 Cp Vsns Cp' S11 VL S2 Aout Ch1 S_Amp Vdmy Sensor block (192 × 128) Buf Voo O_Amp S1 Ch2 VOS VM VH Sense amplifier block (192) Output block (1) Fig. 2 · Fingerprint sensor operation (Fig. 2) Description of characters Cs: Capacitance formed between the finger and the metal electrode Cp: Parasitic capacitance formed between the metal electrode and the silicon substrate Cp': Capacitance for canceling Cp (Cp Cp') Ch: Hold capacitance Cf: Feedback capacitance for determining the gain S: Switch V: Node voltage VH ­ VM VM ­ VL · Detailed description of operation (All switches are off in the default status.) 1. S1, S4 and Sr are turned on, and Vcel is set to voltage VH. Vcel accumulated charge (Cs + Cp) VH 2. S1 and Sr are turned off. 3. S11 and S3 are turned on, and Vdmy is set to voltage VL. Vdmy accumulated charge Cp'VL 4. S3 and S11 are set to off. 5. S2 is turned on and Vsl is set to VM. 6. S4 is turned off. 7. Sr, S3 and S5 are turned on. At this time, the charge level that moves from Vcel and Vdmy to Vsl (actually between capacitances) is: (Cs + Cp) (VH ­ VM) ­ Cp' (VM ­ VL) Cs (VH ­ VM) This means that the sense amplifier gain is determined independently of the parasitic capacitance, making it possible to obtain the required large signal dynamic range. Vsns = VM ­ Cs (VH ­ VM)/Cf1 The voltage Vsns determined as shown above is accumulated in Ch1. 8. S5 is turned off. 9. S6 is turned on and the Voi voltage is set to VOS. 10. S6 is turned off. 11. Sc and S7 are turned on. At this time, the charge level that moves from Ch1 to Cf2 is: (VOS ­ Vsns) Ch1 This determines the Voo voltage which is accumulated in Ch2 and output to Aout via the buffer. ­9­ CXA3271AGE CXA3271AGE Appearance and Readout Order 15.36mm Cell (1, 1) Scan Formation Cell (1, 1) to Cell (1, 192) Cell (1, 192) Sensor Area 192 × 128 10.24mm Cell (128, 1) 16.8mm Cell (128, 192) Cell (128, 1) to Cell (128, 192) 19.8mm Flip G F E D C B A 1 2 3 4 5 6 ­ 10 ­ 7 8 CXA3271AGE CXA3271AGE Notes on Operation S4 S6 Cf1 Cf2 Cs Sr Voi Vsl S5 Vcel Buf Voo Sc S7 S3 Cp Vsns Cp' S11 VL S2 Aout Ch1 S_Amp Vdmy O_Amp S1 Ch2 VOS VM VH · Aout output variance Aout output variance can be broadly classified into two types. The first is variance intrinsic to the IC, and the second is variance caused by the influence of external noise due to the extremely high sensitivity. · Variance intrinsic to the IC 1. The Aout output DC level fluctuates widely due to the IC. This is caused by the Cp and Cp' capacitance values, the VM voltage level, the voltage differences VH ­ VM and VM ­ VL, and the VOS voltage level in the figure above. VOS, VH, VM and VL appear externally as pins. The Aout output level can be set to the desired potential by applying the VOS voltage from an external source. The Aout dynamic range is approximately 0.6 to 2.1V, so checking this output level and externally applying the VOS voltage to set the optimum level is recommended. 2. 192 variances within one line One line is comprised of 192 sensors. Each sensor is connected to a separate S_Amp, so the S_Amp offset appears in the output. (approximately 100 to 200mV) 3. The DC level of a line changes with a certain regularity for some ICs. This is also caused by the S_Amp DC offset. · Variance due to the influence of external noise 1. Output fluctuation due to cross talk from the power supply Power supply fluctuation has a large influence on the Aout output of this IC. In addition to the capacitances between the power supply and GND (approximately 1µF, both sides if possible), attaching capacitances of approximately 0.1µF to VOS, VH, VM and VL is recommended. 2. Finger stabilization The human body acts as an antenna, so the finger potential changes during the sensing period, producing noise in the Aout output. To prevent this, the potential of the area around the finger being sensed must be equalized with the sensor GND. Measures such as placing a metal plate connected to GND around the sensor so that the finger touches this place during sensing are recommended. ­ 11 ­ CXA3271AGE CXA3271AGE Fingerprint sensors have the silicon chip directly exposed, so care should be taken for the following points. In addition, a cover should be attached to protect the sensor surface during operation. Sensor surface electrostatic strength Contact discharge (150pF, 330): ±1.25kV or more Body charge (when the charge accumulated in the body is discharged over the sensor surface): ±4kV or more Body charge differs between individuals. Sensor surface strength The sensor surface is covered with only a thin coating in order to acquire fingerprint information. Therefore, care should be taken when handling the sensor. Problems have been confirmed not to occur during the following tests. · Pressing 10,000 times with a finger (Pressing time: 2s/time) · Rubbing 10,000 times with a finger (Back and forth, 2s/time) · Scratching with a fingernail (20 times back and forth) · Rubbing strongly with a pencil (6H hardness) (20 times back and forth) · Rubbing with a tissue (1,000 times back and forth) Note that problems also occurred with the sensor surface during the following tests. · Pressing strongly with a needle (normal sewing needle) · Rubbing with an eraser · Rubbing with the tip of a ball point pen · Rubbing with steel wool ­ 12 ­ CXA3271AGE CXA3271AGE Timing Chart 500ns XSP (3F) CLK (4C) Strobe Point 250ns 250ns 250ns 480ns Input level VIH = 0.7VDD VIL = 0.3VDD Output level High 0.65VDD 65VDD X 0.35VDD 35VDD Low ­ 13 ­ CXA3271AGE CXA3271AGE Input/Output Signal CK1 clock 2MHz Strobe point (CK Rise + 480ns) CLK (4C) Input F = 2.0MHz 500ns (1clk) 250ns XSP (3F) Input 750ns 750ns (Repeat 128 Times) AOUT (7E) Output Analog output 256.5µs (513clk) (192 + 1 + 63) × 2 + 1) 96µs (192clk) 1st Culumn 32µs (64clk) 96µs 32µs (192clk) (64clk) 2nd Culumn Air level 1.0 to 1.55V 2.1V Dynamic range average analog output AOUT (7E) Detail 0.6V 500ns (1clk) ­ 14 ­ CXA3271AGE CXA3271AGE Package Outline Unit: mm 30PIN 30PIN LLGA (PLASTIC) 2.6 ± 0.25 20 17.58 ± 0.25 (15.16) X 1.45 ± 0.2 0.05MAX 05MAX 0.2 ± 0.2 (10.04) 4-R1.0MAX 17 0.2 M S B PIN1 INDEX 12.64 ± 0.25 2.42 ± 0.25 0.1 S 0.2 M S A (0.85) Y 0.15 SENSOR AREA S 52-1.2 ± 0.08 2.54 2.3 3-2.2 0.1 M S A B 0.25MAX 25MAX TYP 2.54 G F E D DETAIL Y C B A B 1 2 3 4 5 6 7 8 2.2 2.3 3.65 3.42 2.07 2.2 2.07 A 0.25MAX 25MAX TYP DETAIL X NOTE1: Dimension "" does not include breedout of sensor area. NOTE2: The length of breedout is 0.25MAX 25MAX. PACKAGE STRUCTURE PACKAGE MATERIAL ORGANIC SUBSTRATE TERMINAL TREATMENT GOLD PLATING EIAJ CODE TERMINAL MATERIAL COPPER PLATING JEDEC CODE PACKAGE MASS SONY CODE LLGA-30P-01 LLGA-30P-01 ­ 15 ­ 0.7 g Sony Corporation