NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
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ML53812-2 CT812 ML53612 CT612 100/H QS3244 CBT3244 110CT MVIP-90 1-800-OKI-6388 - Datasheet Archive
O K I N E T W O R K P R O D U C T S Design Considerations for Multiple Device Implementation with ML53812-2 (CT812) and ML53612
APPLICATION NOTE O K I N E T W O R K P R O D U C T S Design Considerations for Multiple Device Implementation with ML53812-2 ML53812-2 (CT812 CT812) and ML53612 ML53612 (CT612 CT612) (H.100 and H.110) November 1999 s s CONTENTS Overview .1 System Capacity Issues .1 Card-Level Considerations. 3 Potential Bus Contention . 3 Implementation Issues Common to H.100 (PCI) and H.110 (cPCI) .4 Implementation Issues Specific to H.100 (PCI).6 Implementation Issues Specific to H.110 (cPCI) .10 Related Documentation .13 Oki Semiconductor Documentation .13 Subject References .13 Author Hervé R. AUCH-ROY < auchroy@okisemi.com > Oki Semiconductor Design Considerations for Multiple Device Implementation with ML53812-2 ML53812-2 (CT812 CT812) and ML53612 ML53612 (CT612 CT612) ML53612 ML53612 and ML53812-2 ML53812-2 Bus System Interface and Time Slot Interchange (H.100 / H.110) OVERVIEW This document addresses some of the multiple implementation issues involved when designing the ML53812-2 ML53812-2 (CT812 CT812) or ML53612 ML53612 (CT612 CT612) onto the same CT card. The illustrations in this application note illustrate the following implementations: · CT812 CT812 multiple implementation only · CT612 CT612 multiple implementation only · Mixed CT812 CT812 and CT612 CT612 implementation H.100 (PCI) and H.110 (cPCI) cases are also described. SYSTEM CAPACITY ISSUES The CT system capacity is defined by the ability to provide switching between the Local Bus and the CT Bus on the one hand, and the Local Bus itself on the other hand. However, Local-to-CT Bus switching is inherently limited by the size of the CT Bus (4,096 time slots). Too many connections of this kind would end up in a blocking system, or result in highly complex control software. Moreover, the system configuration must comply with the recommendations of the H.100 and H.110 Specifications, related to Master and Slaves assignments. Also, the common sense of system reliability suggests that Primary Master and Secondary Master should not be on the same card (See Figures 1 and 2). Oki Semiconductor 1 s Design Considerations for Multiple Device Implementation with ML53812-2 ML53812-2 (CT812 CT812) and ML53612 ML53612 (CT612 CT612) s C T_C8_A / T_FR AME _A_N C CT_C8_A/CT_FRAME_A_N CT_C8_B/CT_FRAME_B_N C T_C 8_B /C T_FRA ME_B _N CT_NETREF C T_N ETR EF S S N etw k or PM PM Clock Master C loc Ma st k er N etw ork S S SM SM Standby Master St andbyMaste r S S S S Participating Sl Partipang Slave ic ti ave onfi d a gure s PM CTx12 cConfigured as a PM CTx12 Primary M r Prmar Master i y aste gure s SM CTx12 cConfigured as a SM CTx12 onfi d a Secondary Ma r Secondary Master ste CTx12 Configured as Slave S CTx12 c gure a S ve onfi d s la N etw ork S S DigitallTr D igi Trunk Card ta unk C d ar Figure 1. Master / Slave Configuration (H.100) CT_C8_A/CT_FRAME_A_N C T_C 8_A /C T_FRA ME_A _N CT_C8_B/CT_FRAME_B_N C T_C 8_B / CT_FR AM E_B_N CT_NETREF_1 C T_NETR EF_1 C T_CT_NETREF_2 N E TRE F_2 S N etw k or PM PM Primary Pria ry m Masterr M ast e S S Net k wor SM SM Secondary Secon y dar Master M astr e S S S S N etw k or Slave Digital S lav Di al e git Trunk Card Tru C ard nk N etw ork Tx1 onfi d i mar er PM CTx12 Configureds Pr P M : C 2 c gure aas a y Mast Primary Master Tx1 onfi d c ste SM : C 2 c gure aasSeondary Ma Master SM CTx12 Configureds a Secondary r CTx12 Configured as Slave Tx1 onfi d s ave S S : C 2 c gure a Sl S S S Slave D it Sl Digital ave igal Trunk Card Trun Card k Figure 2. Master / Slave Configuration (H.110) 2 Oki Semiconductor s Design Considerations for Multiple Device Implementation with ML53812-2 ML53812-2 (CT812 CT812) and ML53612 ML53612 (CT612 CT612) s Card Level Considerations To achieve a larger number of Local-to-Local connections on the card, the ML53812-2 ML53812-2 (CT812 CT812) and ML53612 ML53612 (CT612 CT612) can be implemented as multiple devices on the same card. This is made possible using a low profile package (LQFP) with an easy and flexible configuration of the device. The modularity of the ML53812-2 ML53812-2 and ML53612 ML53612 simplifies the system development roadmap, by allowing the engineer to reuse most of the design (hardware and software) and implement as many devices as needed to achieve the target capacity. When proceeding with a multiple implementation, some attention must be given to the following points: · The wiring length between the device's CT_D pins and the H.100/H 100/H.110 connector must not exceed 3.75 inches. This is to comply with the H.100/H 100/H.110 Specification, section 5.5 "PCB Layout and Considerations" (H.100) and section 5.3 "CT Bus Card Requirements" (H.110). · The wiring length between the device's CT Bus clock pins (CT_C8_A, CT_C8_B, CT_FRAME_A_N , CT_FRAME_B_N, CT_NETREF_1, CT_NETREF_2), and the H.100/H 100/H.110 connector must not exceed 1.75 inches (per the same H.100/H 100/H.110 Specification requirement as above). While some differences exist between H.100 and H.110 implementations, there are also similarities. The following subsections and diagrams illustrate the similarities between H.100 and H.110 implementations. Potential Bus Contention Unfortunately, using slave-to-local mode (described below) will prevent the devices (CT812 CT812 and CT612 CT612) from meeting the Data Output to HiZ time (Tdoz) and Data HiZ to Data Output time (Tzdo) parameters. These parameters are defined to prevent potential bus contention on the CT_D lines at time-slot boundaries. For a brief period of time, bus contention can occur when two devices are assigned consecutive time-slot connections, as one device is getting off (3-stating) the other is getting on (driving). The 33-Ohm resistor in series with each CT_D lines helps minimize the current flow during this condition. Both devices (CT612 CT612 and CT812 CT812) meet this requirement by 3-stating CT_D one 7.5-ns clock period before the end of a time-slot. Due to PLL uncertainty, the exact time-slot boundary cannot be determined by the slave-tolocal device, and a period of contention could result. The alternative is to connect both devices to the CT_C8 signal, but the disadvantages of loading down CT_C8 are greater than the potential for bus contention. Oki Semiconductor 3 s Design Considerations for Multiple Device Implementation with ML53812-2 ML53812-2 (CT812 CT812) and ML53612 ML53612 (CT612 CT612) s Implementation Issues Common to H.100 (PCI) and H.110 (cPCI) The following is common to both H.100 and H.110 implementation, as shown in Figures 3 and 4: · Oscillator and analog PLL filtering. · Optional message channel interface and compatibility signals (FR_COMP_N, SCLK, SCLKx2_N). ML53812-2 ML53812-2 (CT812 CT812) ML53612 ML53612 (CT612 CT612) Oscillator (2.048 MHz to 65.536 MHz) APLL_CLKREF System Power 5 V (3.3 V) APLL_VDDO APLL_VDDC (See note 1) 10 µF 100 19.1k 0.1 µF 0.01 µF APLL_PC APLL_VCO APLL_VSSO APLL_VSSC APLL_TEST TEST TMS TCK TEST_N GND 200 GND 200 GND 200 GND RESET System Reset ML53812-2 ML53812-2 (CT812 CT812) ML53612 ML53612 (CT612 CT612) APLL_CLKREF System Power (See note 2 5 V (3.3 V) APLL_VDDO APLL_VDDC (See note 1) 10 µF 100 19.1k 0.1 µF 0.01 µF APLL_PC APLL_VCO APLL_VSSO APLL_VSSC APLL_TEST TEST TMS TCK TEST_N GND 200 GND System Reset 200 GND 200 GND RESET Note 1: No filter inductors specific value is available, and essentially depends upon the power supply and load of the card. The designer can contact vendors for specific advice. Note 2: The power rails for the APLL must be isolated between the chips. (i.e. there must be as many sets of inductors and capacitors as there are devices, as shown above.) Figure 3. Oscillator and Analog PLL Connections (H.100 and H.110) 4 Oki Semiconductor s Design Considerations for Multiple Device Implementation with ML53812-2 ML53812-2 (CT812 CT812) and ML53612 ML53612 (CT612 CT612) s ML53812-2 ML53812-2 (CT812 CT812) ML53612 ML53612 (CT612 CT612) Message Bus Controller 5 V (3.3 V) TXDA RXDA CXDA DCLK MC_TXD MC_RXD 4k (3k ) CT_MC CT_MC MC_CLK 5 V (3.3 V) 100k (68k ) FR_COMP_N FR_COMP_N See note 3 5 V (3.3 V) Device #1 100k (68k ) SCLK SCLK See note 4 CT_D_DISABLE L_CLK_1 L_FS_1 5 V (3.3 V) SCLKx2_N 100k (68k ) SCLKx2_N ML53812-2 ML53812-2 (CT812 CT812) ML53612 ML53612 (CT612 CT612) 5 V (3.3 V) MC_TXD MC_RXD CT_MC See note 4 4k (3k ) MC_CLK FR_COMP_N Device #2 SCLK L_FS_1 L_CLK_1 CT_D_DISABLE SCLKx2_N See note 5 Note 3: The Optional Message Channel Interface allows signaling information to be carried on a dedicated bus without using time slots on the data bus; no information is currently available on the Message Bus Controller. Please refer to section 7.2 "Message Channel" of the H.100 Specification, or section 8.2 "Message Channel" of the H.110 Specification. Note4: The ML53812-2 ML53812-2 and ML53612 ML53612 have a slave-to-local option that allows a second (or third, etc.) chip to slave to the first and therefore not present additional loading on the CT_BUS clock and sync lines. To accomplish this: Tie one of the L_CLK and L_FS pairs between the two (or more) chips (the figure shows L_CLK_1 and L_FS_1, but L_CLK_0 and L_FS_0 is also an option). Have the chip connected to the CT Bus (Device#1) output L_CLK and L_FS (C_[64] or C_[65] depending on the pair of signals chosen), and have the other chip(s) (Device#2) slave-to-local on that input (C_[9:8] = 11 and C_[10] = 0 or 1, depending on the pair of signals chosen). Compensate for delay by setting the Advance Master PLL timing bit (C[19] = 1) in the slave-to-local chip(s) (Device#2). The jumpers are for testing and diagnostic purposes. Note 5: The CT_D_DISABLE pins should be connected between the devices; it provides a way of avoiding CT Bus contention in the event of a clocking error. (See the Generic Application Note for the CT812 CT812 (ML53812-2 ML53812-2) from Dialogic, section 2.2.6 "CT_D_Disable operation"). The Chip connected to the CT Bus (Device#1) should source this signal (C_[67] = 1, C_[69] = 0) and the other chips (Device#2) listen to it (C_[67] = 0, C_[69] = 1). For testing and diagnostic purposes, it is recommended that you connect the CT Bus clock signals of the slave-to-local device(s) (Device#2) through removable jumpers. Figure 4. Optional Message Channel Interface and Compatibility Signals (H.100 and H.110) Oki Semiconductor 5 s Design Considerations for Multiple Device Implementation with ML53812-2 ML53812-2 (CT812 CT812) and ML53612 ML53612 (CT612 CT612) s Implementation Issues Specific to H.100 (PCI) Figures 5, 6, 7, and 8 illustrate the following requirements for H.100: · · · · CT Bus Data and CT_NETREF signals CT Bus terminations MVIP terminations SC Bus CLKFAIL signal x32 5 V (3.3 V) ML53812-2 ML53812-2 (CT812 CT812) ML53612 ML53612 (CT612 CT612) 100k (68k ) CT_D[31:0] 24 CT_D[31:0] 5 V (3.3 V) 100k (68k ) CT_NETREF_1 24 CT_NETREF 5 V (3.3 V) CT_NETREF_2 100k (68k ) ML53812-2 ML53812-2 (CT812 CT812) ML53612 ML53612 (CT612 CT612) CT_D[31:0] CT_NETREF_1 5 V (3.3 V) CT_NETREF_2 100k (68k ) Figure 5. CTBus Data and CT_NETREF Signals (H.100 Only) 6 Oki Semiconductor s Design Considerations for Multiple Device Implementation with ML53812-2 ML53812-2 (CT812 CT812) and ML53612 ML53612 (CT612 CT612) s 5 V (3.3 V) 10k (10k ) 5 V (3.3 V) CT_C8_B 100k (68k ) 100k (68k ) CT_C8_A CT_C8_B QS3244 QS3244 A or CBT3244 CBT3244 Y 5 V (3.3 V) ML53812-2 ML53812-2 (CT812 CT812) ML53612 ML53612 (CT612 CT612) G G CT_C8_A QS3244 QS3244 or Y CBT3244 CBT3244 A 100 100 100 pF 100 pF Device #1 GND GND 5 V (3.3 V) 100k (68k ) 5 V (3.3 V) CT_FRAME_B_N CT_FRAME_A_N 100k (68k ) QS3244 QS3244 A or CBT3244 CBT3244 Y CT_FRAME_B_N G G 100 100 pF 100 100 pF GND GPIO_0 L_CLK_1 L_FS_1 CT_D_DISABLE GND Optional jumper (See note 6) See note 5 See note 4 CT_FRAME_A_N QS3244 QS3244 or Y CBT3244 CBT3244 A See note 4 GND ML53812-2 ML53812-2 (CT812 CT812) ML53612 ML53612 (CT612 CT612) CT_C8_A CT_C8_B Device #2 CT_FRAME_B_N CT_FRAME_A_N See note 4 L_CLK_1 L_FS_1 CT_D_DISABLE GPIO_0 Note4: The ML53812-2 ML53812-2 and ML53612 ML53612 have a slave-to-local option that allows a second (or third, etc.) chip to slave to the first and therefore not present additional loading on the CT_BUS clock and sync lines. To accomplish this: Tie one of the L_CLK and L_FS pairs between the two (or more) chips (the figure shows L_CLK_1 and L_FS_1, but L_CLK_0 and L_FS_0 is also an option). Have the chip connected to the CT Bus (Device#1) output L_CLK and L_FS (C_[64] or C_[65] depending on the pair of signals chosen), and have the other chip(s) (Device#2) slave-to-local on that input (C_[9:8] = 11 and C_[10] = 0 or 1, depending on the pair of signals chosen). Compensate for delay by setting the Advance Master PLL timing bit (C[19] = 1) in the slave-to-local chip(s) (Device#2). The jumpers are for testing and diagnostic purposes. Note 5: The CT_D_DISABLE pins should be connected between the devices; it provides a way of avoiding CT Bus contention in the event of a clocking error. (See the Generic Application Note for the CT812 CT812 (ML53812-2 ML53812-2) from Dialogic, section 2.2.6 "CT_D_Disable operation"). The Chip connected to the CT Bus (Device#1) should source this signal (C_[67] = 1, C_[69] = 0) and the other chips (Device#2) listen to it (C_[67] = 0, C_[69] = 1). For testing and diagnostic purposes, it is recommended that you connect the CT Bus clock signals of the slave-to-local device(s) (Device#2) through removable jumpers. Note 6: The jumper allows termination to be enabled at installation time rather than under software control (applies only to H.100). Figure 6. CT Bus Terminations (H.100 Only) Oki Semiconductor 7 s Design Considerations for Multiple Device Implementation with ML53812-2 ML53812-2 (CT812 CT812) and ML53612 ML53612 (CT612 CT612) s 5 V (3.3 V) 10k (10k ) 5 V (3.3 V) 100k (68k ) C16_POS_N 5 V (3.3 V) ML53812-2 ML53812-2 (CT812 CT812) ML53612 ML53612 (CT612 CT612) 100k (68k ) C2 C16_POS_N G QS3244 QS3244 or Y CBT3244 CBT3244 A G C2 A QS3244 QS3244 or Y CBT3244 CBT3244 1k 1000 pF Device #1 100 GND 5 V (3.3 V) 100k (68k ) 5 V (3.3 V) 100k (68k ) C15_NEG_N C4_N C15_NEG_N G C4_N QS3244 QS3244 or Y CBT3244 CBT3244 A 1k 1000 pF L_CLK_1 L_FS_1 CT_D_DISABLE GPIO_1 Optional jumper (See note 6) See note 5 See note 4 GND GND See note 4 ML53812-2 ML53812-2 (CT812 CT812) ML53612 ML53612 (CT612 CT612) C16_POS_N C2 Device #1 C4_N C15_NEG_N See note 4 L_CLK_1 L_FS_1 CT_D_DISABLE GPIO_1 Note4: The ML53812-2 ML53812-2 and ML53612 ML53612 have a slave-to-local option that allows a second (or third, etc.) chip to slave to the first and therefore not present additional loading on the CT_BUS clock and sync lines. To accomplish this: Tie one of the L_CLK and L_FS pairs between the two (or more) chips (the figure shows L_CLK_1 and L_FS_1, but L_CLK_0 and L_FS_0 is also an option). Have the chip connected to the CT Bus (Device#1) output L_CLK and L_FS (C_[64] or C_[65] depending on the pair of signals chosen), and have the other chip(s) (Device#2) slave-to-local on that input (C_[9:8] = 11 and C_[10] = 0 or 1, depending on the pair of signals chosen). Compensate for delay by setting the Advance Master PLL timing bit (C[19] = 1) in the slave-to-local chip(s) (Device#2). The jumpers are for testing and diagnostic purposes. Note 5: The CT_D_DISABLE pins should be connected between the devices; it provides a way of avoiding CT Bus contention in the event of a clocking error. (See the Generic Application Note for the CT812 CT812 (ML53812-2 ML53812-2) from Dialogic, section 2.2.6 "CT_D_Disable operation"). The Chip connected to the CT Bus (Device#1) should source this signal (C_[67] = 1, C_[69] = 0) and the other chips (Device#2) listen to it (C_[67] = 0, C_[69] = 1). For testing and diagnostic purposes, it is recommended that you connect the CT Bus clock signals of the slave-to-local device(s) (Device#2) through removable jumpers. Note 6: The jumper allows termination to be enabled at installation time rather than under software control (applies only to H.100). Figure 7. MVIP Terminations (H.100 Only) 8 Oki Semiconductor s Design Considerations for Multiple Device Implementation with ML53812-2 ML53812-2 (CT812 CT812) and ML53612 ML53612 (CT612 CT612) s ML53812-2 ML53812-2 (CT812 CT812) ML53612 ML53612 (CT612 CT612) 5V (3.3 V) GPIO_2 4.7k (3k ) Reserved Pin 68 (CLKFAIL) Jumper ML53812-2 ML53812-2 (CT812 CT812) ML53612 ML53612 (CT612 CT612) GPIO_2 Figure 8. SC Bus CLKFAIL Signal (H.100 Only) Oki Semiconductor 9 s Design Considerations for Multiple Device Implementation with ML53812-2 ML53812-2 (CT812 CT812) and ML53612 ML53612 (CT612 CT612) s Implementation Issues Specific to H.110 (cPCI) In an H.110 environment, CT_NETREF_1 and CT_NETREF_2 are both used, and there is no provision for MVIP compatibility. Therefore, the implementation has the following specificity, and is shown in Figures 9, 10, and 11: · CT Bus Data, CT_NETREF_1, and CT_NETREF_2 signals · A Master and B Master signals (CT_C8_A, CT_FRAME_A_N, CT_C8_B, CT_FRAME_B_N) · MVIP compatibility signals (tie-ups only) ML53812-2 ML53812-2 (CT812 CT812) ML53612 ML53612 (CT612 CT612) CT_D[31:0] x32 0.7 V 24 18k CT_D[31:0] 0.7 V 24 18k CT_NETREF_1 CT_NETREF_1 0.7 V 18k CT_NETREF_2 24 CT_NETREF_2 ML53812-2 ML53812-2 (CT812 CT812) ML53612 ML53612 (CT612 CT612) CT_D[31:0] CT_NETREF_1 CT_NETREF_2 Figure 9. CT Bus Data and CT_NETREF Signals (H.110 Only) 10 Oki Semiconductor s Design Considerations for Multiple Device Implementation with ML53812-2 ML53812-2 (CT812 CT812) and ML53612 ML53612 (CT612 CT612) s 5 V (3.3 V) 5 V (3.3 V) 10k (10k ) ML53812-2 ML53812-2 (CT812 CT812) ML53612 ML53612 (CT612 CT612) 10k (10k ) 33 33 CT_C8_A CT_C8_B CT_C8_A CT_C8_B Y A A G G QS3244 QS3244 or CBT3244 CBT3244 QS3244 QS3244 or CBT3244 CBT3244 GPIO_0 GPIO_1 No optional jumper here See note 7 G Y Y A CT_FRAME_B_N No optional jumper here See note 7 Device #1 G A Y CT_FRAME_A_N CT_FRAME_A_N 33 CT_FRAME_B_N 33 See note 4 L_CLK_1 L_FS_1 CT_D_DISABLE See note 5 ML53812-2 ML53812-2 (CT812 CT812) ML53612 ML53612 (CT612 CT612) See note 4 L_CLK_1 L_FS_1 CT_D_DISABLE See note 4 Device #2 CT_C8_A CT_C8_B GPIO_0 CT_FRAME_A_N CT_FRAME_B_N Note4: The ML53812-2 ML53812-2 and ML53612 ML53612 have a slave-to-local option that allows a second (or third, etc.) chip to slave to the first and therefore not present additional loading on the CT_BUS clock and sync lines. To accomplish this: Tie one of the L_CLK and L_FS pairs between the two (or more) chips (the figure shows L_CLK_1 and L_FS_1, but L_CLK_0 and L_FS_0 is also an option). Have the chip connected to the CT Bus (Device#1) output L_CLK and L_FS (C_[64] or C_[65] depending on the pair of signals chosen), and have the other chip(s) (Device#2) slave-to-local on that input (C_[9:8] = 11 and C_[10] = 0 or 1, depending on the pair of signals chosen). Compensate for delay by setting the Advance Master PLL timing bit (C[19] = 1) in the slave-to-local chip(s) (Device#2). The jumpers are for testing and diagnostic purposes. Note 5: The CT_D_DISABLE pins should be connected between the devices; it provides a way of avoiding CT Bus contention in the event of a clocking error. (See the Generic Application Note for the CT812 CT812 (ML53812-2 ML53812-2) from Dialogic, section 2.2.6 "CT_D_Disable operation"). The Chip connected to the CT Bus (Device#1) should source this signal (C_[67] = 1, C_[69] = 0) and the other chips (Device#2) listen to it (C_[67] = 0, C_[69] = 1). For testing and diagnostic purposes, it is recommended that you connect the CT Bus clock signals of the slave-to-local device(s) (Device#2) through removable jumpers. Note 6: The jumper allows termination to be enabled at installation time rather than under software control (applies only to H.100). Note 7: No jumper here. The clock termination by-pass must be done under software control (applies to H.110 only). Figure 10. A Master and B Master Signals (H.110 Only) Oki Semiconductor 11 s Design Considerations for Multiple Device Implementation with ML53812-2 ML53812-2 (CT812 CT812) and ML53612 ML53612 (CT612 CT612) s ML53812-2 ML53812-2 (CT812 CT812) ML53612 ML53612 (CT612 CT612) C2] 5 V (3.3 V) 100k (68k ) 5 V (3.3 V) C4_N 100k (68k ) 5 V (3.3 V) C16_POS_N 100k (68k ) 5 V (3.3 V) C16_NEG_N 100k (68k ) See note 8 ML53812-2 ML53812-2 (CT812 CT812) ML53612 ML53612 (CT612 CT612) C2] 5 V (3.3 V) 100k (68k ) 5 V (3.3 V) C4_N 100k (68k ) 5 V (3.3 V) C16_POS_N 100k (68k ) 5 V (3.3 V) C16_NEG_N 100k (68k ) Note 8: For cost reduction purposes, a single pull-up resistor of higher value can be used (not recommended), provided that the outputs are never turned on by software. Using a single resistor here is NOT RECOMMENDED, as inadvertently turning those outputs on by software would result in damaging the device(s). Figure 11. MVIP Compatibility Signals (H.110 Only) 12 Oki Semiconductor s Design Considerations for Multiple Device Implementation with ML53812-2 ML53812-2 (CT812 CT812) and ML53612 ML53612 (CT612 CT612) s RELATED DOCUMENTATION Oki Semiconductor Documentation The ML53612 ML53612 and ML53812-2 ML53812-2 Data Sheets (H.100/H 100/H.110CT 110CT Bus System Interface and Time Slot Interchange) are available from Oki Semiconductor, and may be obtained from Oki's web site, http://www.okisemi.com, or from a local sales office. An application note for Hot-Swap environment (H.110 only) is also available from Oki's web site or from a local sales office. A Generic Application Note for CT812 CT812 (ML53812-2 ML53812-2) may be obtained from the Dialogic Corporation web site, http://support.dialogic.com/ct812/white.htm. Data Sheets for other communication devices may also be also obtained from Oki's web site or from a local sales office. Subject References · ECTF H.100 and H.110 Hardware Compatibility Specifications : CT Bus (Revision 1.0) Oki Semiconductor 13 s Design Considerations for Multiple Device Implementation with ML53812-2 ML53812-2 (CT812 CT812) and ML53612 ML53612 (CT612 CT612) s 14 Oki Semiconductor The information contained herein can change without notice owing to product and/or technical improvements. Please make sure before using the product that the information you are referring to is up-to-date. The outline of action and examples of application circuits described herein have been chosen as an explanation of the standard action and performance of the product. When you actually plan to use the product, please ensure that the outside conditions are reflected in the actual circuit and assembly designs. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters outside the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right,etc.is granted by us in connection with the use of product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges, including but not limited to operating voltage, power dissipation, and operating temperature. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g.,office automation, communication equipment, measurement equipment, consumer electronics, etc.).These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property or death or injury to humans. Such applications include, but are not limited to: traffic control, automotive, safety, aerospace, nuclear power control, and medical, including life support and maintenance. Certain parts in this document may need governmental approval before they can be exported to certain countries. The purchaser assumes the responsibility of determining the legality of export of these parts and will take appropriate and necessary steps, at their own expense, for export to another country. Copyright 1999 Oki Semiconductor; Copyright 1999 Dialogic Corporation. This document may not, in whole or in part, be reproduced, stored in a retrieval system, translated, or transmitted in any form or by any means, electronic or mechanical, without the express written consent of Dialogic Corporation or Oki Semiconductor. This document contains preliminary information that is subject to change without notice. While every effort has been made to ensure the accuracy of this document, due to ongoing improvements and revisions neither Dialogic nor Oki Semiconductor can guarantee the accuracy of printed material after the date of publication, nor can they accept responsibility for errors or omissions. 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