CS5850 OUT255 OUT256 OUT253 OUT254 VGON-45 - Datasheet Archive

 

TFT-LCD Gate Driver (256 Outputs) GENERAL DESCRIPTION FEATURES CS5850 is a TFT LCD gate driver with 256 outputs for XGA/SXGA

 

CS5850 CS5850 TFT-LCD Gate Driver (256 Outputs) GENERAL DESCRIPTION FEATURES CS5850 CS5850 is a TFT LCD gate driver with 256 outputs for XGA/SXGA display systems. The logic and control portion is implemented in standard CMOS circuits while the output drivers use high voltage CMOS design. The low voltage part includes a 256stage bidirectional shift register with right and left shift I/O for cascading. The output of the shift register is then level translated to drive the high voltage output buffer. There are four supply voltages for CS5850 CS5850. VDD/VLL are the supply voltages for logic interfaces. Typically VDD is at 3.3V while VLL is 0V. VGON and VSS are the supply voltages for the output driver. VSS is the most negative supply voltage for the internal substrate of CS5850 CS5850. CS5850 CS5850 allows three output enable controls (OE13) and one global enable signal (XON). · · · · · · · 256 gate drive outputs Bidirectional shift control and cascadable Output enable and global on control Maximum shift clock frequency up to 100KHz 3.3V CMOS logic I/O High voltage output drive Operating supply range Logic (VDD-VLL: 3.3V) Output Drive (VGON -VSS: 40V) · TCP package BLOCK DIAGRAM DIOL DIOR SCLK RL SHIFT CONTROL REGISTER OE1,2,3 XON VDD VLL ENABLE CONTROL VGON LEVEL SHIFT VSS OUTPUT BUFFER OUT1 OUT2 OUT255 OUT255 OUT256 OUT256 CS5850 CS5850 Myson Century, Inc. Taiwan: No. 2, Industry East Rd. III, Science-Based Industrial Park, Hsin-Chu, Taiwan Tel: 886-3-5784866 Fax: 886-3-5784349 USA: 4020 Moorpark Avenue Suite 115 San Jose, CA, 95117 Tel: 408-243-8388 Fax: 408-243-3188 Sales@myson.com.tw www.myson.com.tw Rev.1.1 February 2003 page 1 of 11 CS5850 CS5850 PIN CONNECTION DIAGRAM OUT1 OUT2 OUT3 OUT4 VSS VSS VLL DIOL XON RL SCLK OE1 CS5850 CS5850 OE2 OE3 DIOR VDD VGON VAA OUT253 OUT253 OUT254 OUT254 OUT255 OUT255 OUT256 OUT256 RESETN IC top view. This diagram shows CS5850 CS5850's pin configuration only. It does not necessarily correspond to the pad layout on the chip. Figure-1 page 2 of 11 CS5850 CS5850 PIN DESCRIPTION Name Pin Description SCLK I Shift clock. This is a 3.3V CMOS level input for shift register clock. The rising edge of SCLK is used. RL I Right/Left shift control. RL=1 is shift right (OUT1 -> OUT256 OUT256), RL=0 is shift left (OUT256 OUT256 -> OUT1). DIOR I/O Right Data I/O. This is a bidirectional shift data for the right side. It is an output when RL=1, and an input when RL=0. DIOR and DIOL are used to cascade multiple CS5850s to form more than 256 outputs. DIOL I/O Left Data I/O. This is the bidirectional shift data for the left side. OE1, OE2, OE3 I Output enable control. The output is forced low when OE is high. OE1 controls output 1,4,.,253,256. The control is asynchronous to SCLK. OE2 controls output 2,5,.,251,254. The control is asynchronous to SCLK. OE3 controls output 3,6,.,252,255. The control is asynchronous to SCLK. XON I Global on control. When XON=0, all outputs are forced high. XON is asychronous to SCLK. OUT [1-256] O Output drive. These are the gate drive outputs. The high level is VGON and the low level is VSS. VDD P Positive supply for the CMOS logic I/O. This is typically 3.3V. VLL P Negative supply for the CMOS logic I/O. This is typically 0V. VGON P Positive supply for the output driver. This is typically the most positive supply voltage to CS5850 CS5850. VAA P Positive supply for the internal logic circuits. VSS P Negative supply for the output drive and the substrate. This is the most negative supply voltage to CS5850 CS5850. RESETN I Active low reset pin. This signal uses to reset internal shift registers. Note: RESETN and VAA is not connected to the TCP package. LCD drive output VGON VDD Input DIOR DIOL VLL Internal logic VAA VSS Figure-2 page 3 of 11 CS5850 CS5850 FUNCTIONAL DESCRIPTION 1. When RL is "HIGH" and a start pulse inputs the DIOL pin, this pulse is shifted right by the shift control register at the rising edge of SCLK. While the output of the shift control register is "HIGH", the OUTn [n=1, 2, 3,., 256] is pulled to VGON. If the output of the shift control register is "LOW", OUTn [n=1, 2, 3,., 256] is pushed to VSS; DIOR is pulled to high at the falling edge of the 256th clock of SCLK and is pushed to low at the falling edge of the 257th clock of SCLK. Please refer to operating waveform (1). 2. When RL is "LOW" and a start pulse inputs the DIOR pin, this pulse is shifted left by the shift control register at the rising edge of SCLK. While the output of the shift control register is "HIGH", the OUTn [n=256, 255, 254,., 1] is pulled to VGON. If the output of the shift control register is "LOW", OUTn [n=256, 255, 254,., 1] is pushed to VSS; DIOL is pulled to high at the falling edge of the 256th clock of SCLK and is pushed to low at the falling edge of the 257th clock of SCLK. Please refer to operating waveform (2). 3. If there is a long start pulse input, the consecutive "HIGH"s may be shifted at the consecutive rising edges of the SCLK. The CS5850 CS5850 will shift only two consecutive "HIGH"s at most. That is, the CS5850 CS5850 will only shifted the first two input "HIGH"s at the consecutive two rising edges of the SCLK, meaning that the first two input "HIGH"s are detected, and the other "HIGH"s are ignored and regarded as "LOW". Please refer to Figure-3. 4. OE1, OE2, and OE3 can disable OUTn [n=1, 2, 3,., 256]. They are asynchronous to SCLK. OUTn [n=1, 4, 7,., 253, 256] is pushed to VSS when OE1 is "HIGH". OUTn [n=2, 5, 8,., 251, 254] is pushed to VSS when OE2 is "HIGH". OUTn [n=3, 6, 9,., 252, 255] is pushed to VSS when OE3 is "HIGH". Please refer to operating waveform (1) and (2). 5. The global on control XON can enable OUTn [n=1, 2, 3,., 256]. It is asynchronous to SCLK. Whenever XON is "LOW", all outputs of CS5850 CS5850 are pulled to VGON at the same time. Please refer to operating waveform (3). 1 2 3 4 5 6 7 8 SCLK DIOL (DIOR) input OUT1 (OUT256 OUT256) Figure-3 page 4 of 11 CS5850 CS5850 TIMING DIAGRAM RL=1, shift right 1 2 3 4 5 254 255 256 257 256 257 SCLK DIOL OE1 OE2 OE3 OUT1 OUT2 OUT3 OUT256 OUT256 DIOR Figure-4 Operating Waveforms (1) RL=0, shift left 1 2 3 4 5 254 255 SCLK DIOR OE1 OE2 OE3 OUT256 OUT256 OUT255 OUT255 OUT254 OUT254 OUT1 DIOL Figure-5 Operating Waveforms (2) page 5 of 11 CS5850 CS5850 XON=0, RL=1 1 2 3 4 5 254 255 256 257 SCLK DIOL OE1 OE2 OE3 XON OUT1 OUT2 OUT3 OUT256 OUT256 DIOR Figure-6 Operating Waveforms (3) page 6 of 11 CS5850 CS5850 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATING VLL = 0V Symbol VDD VGON Parameter Rating Unit Logic Supply Voltage -0.3 ~ +7.0 V Positive Supply Voltage -0.3 ~ +45 V VSS Most Negative Supply Voltage VGON-45 VGON-45 ~ +0.3 V VIN Logic Input Voltage -0.3 ~ VDD +0.3 V Ta Operation Ambient Temperature -30 ~ +85 °C Storage Temperature Range -55 ~ +120 °C Tstg RECOMMENDED OPERATING RANGE VLL = 0V Symbol Min Typ Max Unit Logic Supply Voltage 3.0 3.3 3.6 V Positive Supply Voltage 10 VSS + 40 V VSS Most Negative Supply Voltage -25 -5 V Ta Operation Ambient Temperature -20 +75 °C VDD VGON Parameter Note: Power ON/OFF sequence is as below: 1. Power ON sequence: VLL VDD VSS VGON. 2. Power OFF sequence: VGON VSS VDD VLL. Voltage VGON VDD VLL Time VSS Figure-7 page 7 of 11 CS5850 CS5850 DC ELECTRICAL CHARACTERISTICS 1. Supply current VLL = 0V Symbol Parameter IVDD Operating current IVGON1 IVDD IVGON2 Condition Min Typ Standby current µA 100 VGON = 15V µA 600 VSS = -15V µA 300 VDD = 3.3V Unit 800 fSCLK = 15.7KHz fSL = 60Hz VDD = 3.3V VSS = -15V VGON = 15V no loading Max µA 2. Input pin: RL, SCLK, OE1, OE2, OE3, XON VLL = 0V Symbol Parameter Condition Min Typ Max Unit VIH1 Input Voltage, HIGH 0.8xVDD VDD V VIL1 Input Voltage, LOW 0 0.2xVDD V ILI1 Input Leakage Current -10 10 µA 3. I/O pin: DIOL, DIOR VLL = 0V Symbol Parameter Condition Min Typ Max Unit VIH2 Input Voltage, HIGH 0.8xVDD VDD V VIL2 Input Voltage, LOW 0 0.2xVDD V VOH Output Voltage, HIGH -100µA VOL Output Voltage, LOW 100µA VDD-0.4 V 0.4 V page 8 of 11 CS5850 CS5850 4. Output pin: OUT1 ~OUT256 OUT256 Ta = 25°C, VLL = 0V ° Symbol ILO1 Parameter Condition Output Leakage Current Min Typ Unit 50 -50 Max µ Output ON Resistance RON-VSS 650 1000 VGON = 15V VSS = -10V VOUT = VSS + 0.5V RON-VGON VGON = 15V VSS = -15V VOUT = VGON -0.5V VOUT is output Voltage on Output terminal OUT1 ~ OUT256 OUT256 250 500 AC CHARACTERISTICS Ta = 25°C, VLL = 0V Symbol tSCLK Parameter Condition Min Typ Max Unit 10 Shift Clock Period µs tWH Shift Clock Pulse Width, HIGH 4 µs tWL Shift Clock Pulse Width, LOW 4 µs tr Shift Clock Rise Time 100 ns tf Shift Clock Fall Time 100 ns tsu DIOL/DIOR Input Setup Time 50 ns tn DIOL/DIOR Input Hold Time 350 ns tpd1 DIOL/DIOR Output Delay Time CL = 50pF 300 ns tpd2 OUTn Output Delay Time CL = 300pF 800 ns tpd3 OUTn Output Delay Time (XON only) CL = 300pF 1000 ns page 9 of 11 CS5850 CS5850 AC Characteristics Waveforms tWL tWH 80% 80% 20% 20% SCLK tSCLK 90% 50% 20% 10% tr tsu 50% 10% tf th 80% 90% 80% DIOL/DIOR Input tpd1 tpd1 60% DIOL/DIOR Output 40% tpd2 60% 40% OUTn 80% 20% OEm tpd2 tpd2 60% OUTn 40% 80% XON 20% tpd3 tpd3 60% 40% OUTn Figure-8 page 10 of 11 CS5850 CS5850 ORDERING INFORMATION Standard Configuration Prefix Part Type Package Type CS 5850 E: TCP page 11 of 11