CS1087 AN24-AN29 AN1-AN23 PLCC17 MS-011 MO-047 MS-026 CS1087XN40 CS1087XFN44 - Datasheet Archive

 

CS1087 Vacuum Fluorescent Display Tube Driver Features Description The VFD Driver is a microprocessor interface IC that drives a

 

CS1087 CS1087 CS1087 CS1087 Vacuum Fluorescent Display Tube Driver Features Description The VFD Driver is a microprocessor interface IC that drives a multiplexed VF (Vacuum Fluorescent) display tube. It consists of a 32-bit shift register, a 32-bit transparent data latch, a metal mask ROM, six 20mA anode output drivers, twenty-three 2mA anode output drivers, and three 50mA grid drivers with output enables. The metal mask programmable ROM (at factory request) allows the 29 anode outputs and 3 grid outputs to be assigned to any of the 32 serial data bits. s Metal Mask ROM s Six 20mA Anode drivers s Twenty-three, 2mA Anode Drivers s Three, 50mA Grid Drivers s Power On Reset s Display Dimming Possible Absolute Maximum Ratings Supply Voltage (VBB) .-0.6V to 18.0V Input Voltages (DIN, CLK, STB, GREN).-0.6V to 6.0V Junction Temperature Range.-40°C to 150°C Storage Temperature Range .-55°C to 150°C ESD Susceptibility (Human Body Model).2kV ESD Susceptibility (Machine Model) .200V Lead Temperature Soldering Wave Solder(through hole styles only) .10 sec. max, 260°C peak Reflow (SMD styles only) .60 sec. max above 183°C, 230°C peak Package Options 40 Lead PDIP 1 40 Application Diagram Chip Select 44 Lead PLCC Clock 1 44 Data Out VIGN SPI Functions 12V Regulator VBB VBAT 0.1µF 5V Gnd VCC CS1087 CS1087 µP DOUT PORT 48 Lead LQFP CLK PORT Gnd FILAMENT VFD DIN PORT Anodes 1:29 STB PORT GREN Gnd GRID1 GRID2 GRID3 Gnd GRID1 48 1 GRID2 GRID3 ON Semiconductor 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885­3600 Fax: (401)885­5786 N. American Technical Support: 800-282-9855 Web Site: www.onsemi.com June, 2000 - Rev. 6 1 CS1087 CS1087 Electrical Characteristics: 8.0V VBB 16.5V, Gnd = 0V, -40°C TJ 105°C; unless otherwise stated. PARAMETER s VBB Input VBB Input Voltage IBB0 Current Reset Mode TEST CONDITIONS MIN TYP 8.0 MAX UNIT 16.5 2 6.5 V 5 7.5 mA V 1.6 No outputs active, VBB = 16.5V All outputs forced low. V V µA s DIN, CLK, STB Inputs VILl, Input Low Voltage VIH, Input High Voltage IIL, Input Current s GREN Input VIL, Input Low Voltage VIH, Input High Voltage IIH, Input Pull-down Current 3.3 0 VIN = VIH 20.0 1.6 60 V V µA 0.5 VBB mA mA V V 0.5 VBB µA mA V V 0.5 VBB µA mA V V 0.5 5.0 mA mA V V 3.3 VIN = 3.325V 30 s GRID1, GRID2, GRID3 Outputs IOL Sink Current IOH VOL VOH 7.5 1.0 50 Source Current IOUT = 1mA IOUT = -50mA, VBB = 12V s AN24-AN29 AN24-AN29 Outputs IOL IOH VOL VOH Sink Current Source Current IOUT = 400µA IOUT = -20mA, VBB = 12V s AN1-AN23 AN1-AN23 Outputs IOL IOH VOL VOH VBB - 0.75 Sink Current Source Current IOUT = 100µA IOUT = -2mA, VBB = 12V 400 20 VBB - 0.5 100 2.0 VBB - 0.5 s DOUT Output IOL IOH VOL VOH Sink Current Source Current IOUT = 1mA IOUT = -1mA 1.0 1.0 3.9 s AC Characteristics: Input and Output Timing FC, CLK Frequency TCL, CLK Low Time TCH, CLK High Time 0 200 200 2 1 MHz ns ns PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 100 100 200 ns ns ns 200 200 5.0 ns ns ns ns µs VBB = 12V 2 µs VBB = 12V 5 µs 2.00 2.00 2.00 2.50 µs µs µs µs s AC Characteristics: Input and Output Timing: continued TCR, CLK Rise Time TCF, CLK Fall Time TCD, CLK Low to DOUT Propagation Delay TDR, DOUT Rise Time TDF, DOUT Fall Time TSC, STB Low to CLK High Time TST, STB High Time TAN, STB High to Anode Output Propagation Delay TGL, Grid Turn On Propagation Delay TG0, Grid Turn Off Propagation Delay TGR, Grid Rise Time TGF, Grid Fall Time TAR, Anode Rise Time TAF, Anode Fall Time 50 500 At rated load. At rated load. At rated load. At rated load. 0.50 0.35 0.40 0.40 Note: Grid and anode rise/fall times are measured from 10% and 90% points. Output currents are at the maximum rated currents for the respective stages. Package Lead Description PACKAGE LEAD # LEAD SYMBOL FUNCTION 40L DIP 44L PLCC 48L LQFP (29 Anode Configuration) 1 14 8 GRID1 50mA grid output. 2 15 9 GRID2 50mA grid output. 3 16 10 GRID3 50mA grid output. 4 17 11 AN1 2mA anode output. 5 18 13 AN2 2mA anode output. 6 19 14 AN3 2mA anode output. 7 20 15 AN4 2mA anode output. 8 21 16 AN5 2mA anode output. 9 22 17 AN6 2mA anode output. 10 24 19 AN7 2mA anode output. 11 25 20 AN8 2mA anode output. 12 26 21 AN9 2mA anode output. 13 27 22 AN10 2mA anode output. 14 28 23 AN11 2mA anode output. 15 29 25 AN12 2mA anode output. 16 30 26 AN13 2mA anode output. 3 CS1087 CS1087 Electrical Characteristics: 8.0V VBB 16.5V, Gnd = 0V, -40°C TJ 105°C; unless otherwise stated. CS1087 CS1087 Package Lead Description: continued PACKAGE LEAD # LEAD SYMBOL FUNCTION 40L DIP 44L PLCC 48L LQFP (29 Anode Configuration) 17 31 27 AN14 2mA anode output. 18 32 28 AN15 2mA anode output. 19 33 29 AN16 2mA anode output. 20 35 31 Gnd Ground connection. 21 36 32 AN17 2mA anode output. 22 37 33 AN18 2mA anode output. 23 38 34 AN19 2mA anode output. 24 39 35 AN20 2mA anode output. 25 40 37 AN21 2mA anode output. 26 41 38 AN22 2mA anode output. 27 42 39 AN23 2mA anode output. 28 43 40 AN24 20mA anode output. 29 44 41 AN25 20mA anode output. 30 2 43 AN26 20mA anode output. 31 3 44 AN27 20mA anode output. 32 4 45 AN28 20mA anode output. 33 5 46 AN29 20mA anode output. 34 6 47 DOUT Shift register data output. 35 7 1 DIN Shift register data input. 36 8 2 CLK Shift register clock input. 37 9 3 STB Transfer contents of shift registers to output stages. 38 10 4 GREN 39 1, 11, 12, 23, 34 5, 6, 12, 18, 24, 30, 36, 42, 48 NC No Connection. 40 13 7 VBB Supply voltage input. Grid outputs enable. Operation Description The three GRID outputs are gated by the GREN input. When GREN is low, the GRID outputs are forced low regardless of the state of the corresponding latch output. When GREN is high, the GRID outputs correspond to the state of their respective latch outputs. The anode outputs, AN1 to AN29 are always enabled. Upon the initial application of power, the power on reset function will cause all of the anode and grid driver outputs to be off and all shift register outputs to be set low. Data is fed into the shift register through the DIN pin at the rising edge of the CLK input. Thirty two bits of data are capable of being stored by the shift register. Once the desired pattern is stored in the shift register, it can be transferred to the latch by setting the STB input high. The output of each latch drives its corresponding output stage. A logic high input to the shift register/latch will cause the corresponding output to turn on. A logic low input to the shift register/latch will cause the corresponding output to turn off. Please note that if the STB is held high, the outputs of the latch reflect the outputs of the corresponding shift register bits and will change if data is shifted in. The DOUT pin is the output of the last stage of the shift register to allow serial cascading of this IC with other devices. Data from the last stage of the shift register is supplied to the DOUT pin delayed by 1/2 CLK cycle. Data on the DOUT output changes with the falling edges of the CLK to prevent logic race conditions between the CLK and the DIN of the next IC in the serial chain. 4 CS1087 CS1087 Block Diagram AN1 GRID1 GRID2 GRID3 AN3 AN2 AN24 AN23 AN28 AN29 AN27 AN25 AN26 VBB VREG VREG POR Gnd VREG GREN METAL MASK ROM VREG STB D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q LE VREG LE LE LE LE LE LE LE LE LE LE LE LE VREG DIN D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK R VREG R R R R R R R R R R R R R DOUT CLK Output Drive Capability Grid Outputs: 50mA AN24 - AN29: 20mA AN1 - AN23: 2mA Application Information 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 G1 G2 G3 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 Bit # Pin Name 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 Bit # Pin Name Table 1: Bit Pattern, G = Grid, A = Anode. Typical Operation CLKIN 1 2 3 4 5 6 7 8 9 DIN BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 DOUT PREV BIT 1 PREV BIT 2 PREV BIT 3 PREV BIT 4 PREV BIT 5 PREV BIT 6 PREV BIT 7 PREV BIT 8 32 1 2 3 BIT 9 BIT 30 BIT 31 BIT 32 BIT 1 BIT 2 BIT 3 PREV BIT 9 PREV BIT 30 PREV BIT 1 PREV BIT 2 PREV BIT 3 STB ANODES GREN GRIDS * * Selected grid goes high only if input bit pattern from shift register to grid is high. 5 30 31 PREV BIT 31 PREV BIT 32 CS1087 CS1087 Package Specification PACKAGE DIMENSIONS IN mm (INCHES) PACKAGE THERMAL DATA D Lead Count Thermal Data Metric Max Min 50.3 53.2 40 Lead PDIP English Max Min 1.980 2.095 RJC RJA 40 Lead 44 Lead PDIP PLCC 20 16 45 55 typ typ 48 Lead LQFP ­ °C/W ­ °C/W A B A B Lead Count Metric English Max Min Max Min Max Min Max Min 44 Lead PLCC17 PLCC17.65 17.40 16.66 16.51 .695 .685 .656 .650 Plastic DIP (N); 600 mil wide PLCC (FN) 4.06 (.160) 3.69 (.145) A 14.73 (.580) 12.32 (.485) B .51 (.020) Min 15.87 (.625) 15.24 (.600) A 1.77 (.070) 1.14 (.045) B 2.54 (1.00) BSC .53 (.021) .33 (.013) 3.94 (.155) 3.18 (.125) .81 (.032) .66 (.026) 0.39 (.015) MIN .558 (.022) .356 (.014) REF: JEDEC MS-011 MS-011 1.27 (.050) BSC REF JEDEC MO-047 MO-047 D 48 Lead LQFP (FT) 7 × 7mm Body 1.45 (.057) 1.35 (.053) See Detail A 1.60 (.063) max 9.00 (.354) BSC 0.15 (.006) 0.05 (.002) 7.00 (.276) BSC 0.27 (.011) 0.17 (.007) DETAIL A 7.00 BSC (.276) 9.00 BSC (.354) 0.20 (.008) 0.09 (.004) 0.75 (.030) 0.45 (.018) 1.00 (.039) Ref 0.50 (.020) BSC REF JEDEC MS-026 MS-026 Ordering Information Part Number CS1087XN40 CS1087XN40 CS1087XFN44 CS1087XFN44 CS1087XFNR44 CS1087XFNR44 CS1087XFT48 CS1087XFT48 CS1087XFTR48 CS1087XFTR48 Description 40 Lead PDIP 44 Lead PLCC 44 Lead PLCC (tape & reel) 48 Lead LQFP 48 Lead LQFP (tape & reel) ON Semiconductor and the ON Logo are trademarks of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor reserves the right to make changes without further notice to any products herein. For additional information and the latest available information, please contact your local ON Semiconductor representative. 6 © Semiconductor Components Industries, LLC, 2000 Notes Notes