NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS

Datasheet Archive - Datasheet Search Engine

 

Direct from the Manufacturer

Part Manufacturer Description PDF Samples Ordering
UA78L05QLPR Texas Instruments IC VREG 5 V FIXED POSITIVE REGULATOR, PBCY3, PLASTIC, TO-226AA, TO-92, 3 PIN, Fixed Positive Single Output Standard Regulator ri Buy
UA78L05AQDR Texas Instruments IC VREG 5 V FIXED POSITIVE REGULATOR, PDSO8, PLASTIC, MS-012AA, SOIC-8, Fixed Positive Single Output Standard Regulator ri Buy
UA78L05QLP Texas Instruments IC VREG 5 V FIXED POSITIVE REGULATOR, PBCY3, PLASTIC, TO-226AA, TO-92, 3 PIN, Fixed Positive Single Output Standard Regulator ri Buy

CS 78L05 sb

Catalog Datasheet Results Type PDF Document Tags
Abstract: Interface DCLOCK CS/SHDN Please be aware that an important notice concerning availability, standard , VREF +In ­In GND 1 2 ADS7817 ADS7817 3 4 PDIP-8, SOIC-8, MSOP-8 6 5 DOUT CS/SHDN 8 7 +VCC DCLOCK PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 NAME VREF +In ­In GND CS/SHDN DOUT DCLOCK +VCC DESCRIPTION Reference Input. , edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After , at at at 1kHz 5kHz 1kHz 1kHz 0.1 CS = VCC CS = GND, fSAMPLE = 0Hz At Code FF8h fSAMPLE = 12.5kHz CS = ... Original
datasheet

18 pages,
348.83 Kb

DSPS6004 CS 78L05 sb wst 78L05 ADS7817 ADS7817 abstract
datasheet frame
Abstract: SAR VREF DOUT +In CDAC Serial Interface ­In S/H Amp Comparator DCLOCK CS/SHDN , DOUT GND 4 5 CS/SHDN PDIP-8, SOIC-8, MSOP-8 PIN DESCRIPTIONS PIN NAME 1 , Input. 4 GND 5 CS/SHDN Ground. 6 DOUT 7 DCLOCK 8 +VCC Chip Select , CS enables the serial output. After one null bit the data is valid for the next 12 edges. Data Clock , µA 2.5 5 5 20 1.3 0.001 CS = VCC CS = GND, fSAMPLE = 0Hz At Code FF8h ... Original
datasheet

18 pages,
312.2 Kb

A615 ADS7817 ADS7817E ADS7817EB ADS7817P ADS7817PB ADS7817PC ADS7817U ADS7817UB CS 78L05 sb wst 78L05 BR 78L05 ADS7817 abstract
datasheet frame
Abstract: Interface DCLOCK CS/SHDN Please be aware that an important notice concerning availability, standard , VREF +In ­In GND 1 2 ADS7817 ADS7817 3 4 PDIP-8, SOIC-8, MSOP-8 6 5 DOUT CS/SHDN 8 7 +VCC DCLOCK PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 NAME VREF +In ­In GND CS/SHDN DOUT DCLOCK +VCC DESCRIPTION Reference Input. , edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After , at at at 1kHz 5kHz 1kHz 1kHz 0.1 CS = VCC CS = GND, fSAMPLE = 0Hz At Code FF8h fSAMPLE = 12.5kHz CS = ... Original
datasheet

18 pages,
294.15 Kb

BR 78L05 ADS7817 ADS7817 abstract
datasheet frame
Abstract: Interface DCLOCK CS/SHDN Please be aware that an important notice concerning availability, standard , VREF +In ­In GND 1 2 ADS7817 ADS7817 3 4 PDIP-8, SOIC-8, MSOP-8 6 5 DOUT CS/SHDN 8 7 +VCC DCLOCK PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 NAME VREF +In ­In GND CS/SHDN DOUT DCLOCK +VCC DESCRIPTION Reference Input. , edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After , at at at 1kHz 5kHz 1kHz 1kHz 0.1 CS = VCC CS = GND, fSAMPLE = 0Hz At Code FF8h fSAMPLE = 12.5kHz CS = ... Original
datasheet

18 pages,
304.62 Kb

wst 78L05 ADS7817 ADS7817 abstract
datasheet frame
Abstract: Interface DCLOCK CS/SHDN Please be aware that an important notice concerning availability, standard , VREF +In ­In GND 1 2 ADS7817 ADS7817 3 4 PDIP-8, SOIC-8, MSOP-8 6 5 DOUT CS/SHDN 8 7 +VCC DCLOCK PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 NAME VREF +In ­In GND CS/SHDN DOUT DCLOCK +VCC DESCRIPTION Reference Input. , edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After , at at at 1kHz 5kHz 1kHz 1kHz 0.1 CS = VCC CS = GND, fSAMPLE = 0Hz At Code FF8h fSAMPLE = 12.5kHz CS = ... Original
datasheet

18 pages,
311.52 Kb

ADS7817 ADS7817 abstract
datasheet frame
Abstract: Interface DCLOCK CS/SHDN Please be aware that an important notice concerning availability, standard , VREF +In ­In GND 1 2 ADS7817 ADS7817 3 4 PDIP-8, SOIC-8, MSOP-8 6 5 DOUT CS/SHDN 8 7 +VCC DCLOCK PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 NAME VREF +In ­In GND CS/SHDN DOUT DCLOCK +VCC DESCRIPTION Reference Input. , edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After , at at at 1kHz 5kHz 1kHz 1kHz 0.1 CS = VCC CS = GND, fSAMPLE = 0Hz At Code FF8h fSAMPLE = 12.5kHz CS = ... Original
datasheet

18 pages,
300.46 Kb

ADS7817 ADS7817 abstract
datasheet frame
Abstract: Interface DCLOCK CS/SHDN Please be aware that an important notice concerning availability, standard , VREF +In ­In GND 1 2 ADS7817 ADS7817 3 4 PDIP-8, SOIC-8, MSOP-8 6 5 DOUT CS/SHDN 8 7 +VCC DCLOCK PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 NAME VREF +In ­In GND CS/SHDN DOUT DCLOCK +VCC DESCRIPTION Reference Input. , edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After , at at at 1kHz 5kHz 1kHz 1kHz 0.1 CS = VCC CS = GND, fSAMPLE = 0Hz At Code FF8h fSAMPLE = 12.5kHz CS = ... Original
datasheet

18 pages,
299.99 Kb

ADS7817 ADS7817 abstract
datasheet frame
Abstract: Interface DCLOCK CS/SHDN Please be aware that an important notice concerning availability, standard , VREF +In ­In GND 1 2 ADS7817 ADS7817 3 4 PDIP-8, SOIC-8, MSOP-8 6 5 DOUT CS/SHDN 8 7 +VCC DCLOCK PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 NAME VREF +In ­In GND CS/SHDN DOUT DCLOCK +VCC DESCRIPTION Reference Input. , edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After , at at at 1kHz 5kHz 1kHz 1kHz 0.1 CS = VCC CS = GND, fSAMPLE = 0Hz At Code FF8h fSAMPLE = 12.5kHz CS = ... Original
datasheet

21 pages,
472.25 Kb

ADS7817 ADS7817 abstract
datasheet frame
Abstract: Interface DCLOCK CS/SHDN Please be aware that an important notice concerning availability, standard , VREF +In ­In GND 1 2 ADS7817 ADS7817 3 4 PDIP-8, SOIC-8, MSOP-8 6 5 DOUT CS/SHDN 8 7 +VCC DCLOCK PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 NAME VREF +In ­In GND CS/SHDN DOUT DCLOCK +VCC DESCRIPTION Reference Input. , edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After , at at at 1kHz 5kHz 1kHz 1kHz 0.1 CS = VCC CS = GND, fSAMPLE = 0Hz At Code FF8h fSAMPLE = 12.5kHz CS = ... Original
datasheet

21 pages,
632.22 Kb

wst 78L05 ADS7817 ADS7817 abstract
datasheet frame
Abstract: SAR VREF DOUT +In CDAC Serial Interface ­In S/H Amp Comparator DCLOCK CS/SHDN , DOUT GND 4 5 CS/SHDN PDIP-8, SOIC-8, MSOP-8 PIN DESCRIPTIONS PIN NAME 1 , Input. 4 GND 5 CS/SHDN Ground. 6 DOUT 7 DCLOCK 8 +VCC Chip Select , CS enables the serial output. After one null bit the data is valid for the next 12 edges. Data Clock , µA 2.5 5 5 20 1.3 0.001 CS = VCC CS = GND, fSAMPLE = 0Hz At Code FF8h ... Original
datasheet

21 pages,
471.93 Kb

ADS7817UB ADS7817U ADS7817PC ADS7817PB ADS7817P ADS7817EB ADS7817E ADS7817 A615 ADS7817 abstract
datasheet frame

Datasheet Content (non pdf)

Abstract Saved from Date Saved File Size Type Download
Over 1.1 million files (1986-2014): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer.