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UA78L05QDR Texas Instruments 5V FIXED POSITIVE REGULATOR, PDSO8, SO-8 visit Texas Instruments
LM78L05ITPX/NOPB Texas Instruments 100 mA 5V Fixed Output Linear Regulator 8-DSBGA -40 to 85 visit Texas Instruments
UA78L05QD Texas Instruments 5V FIXED POSITIVE REGULATOR, PDSO8, SO-8 visit Texas Instruments
LM78L05ACZ Texas Instruments 5V FIXED POSITIVE REGULATOR, PBCY3, PLASTIC, TO-92, 3 PIN visit Texas Instruments
UA78L05CLPRE3 Texas Instruments 5V FIXED POSITIVE REGULATOR, PBCY3, ROHS COMPLIANT, PLASTIC, TO-226AA, TO-92, 3 PIN visit Texas Instruments
UA78L05AQD Texas Instruments 3/8 Pin 100mA Fixed 5V Positive Voltage Regulator 8-SOIC visit Texas Instruments

CS 78L05 sb

Catalog Datasheet MFG & Type PDF Document Tags

wst 78L05

Abstract: BR 78L05 Interface DCLOCK CS/SHDN Please be aware that an important notice concerning availability, standard , VREF +In ­In GND 1 2 ADS7817 3 4 PDIP-8, SOIC-8, MSOP-8 6 5 DOUT CS/SHDN 8 7 +VCC DCLOCK PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 NAME VREF +In ­In GND CS/SHDN DOUT DCLOCK +VCC DESCRIPTION Reference Input , edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After , at at at 1kHz 5kHz 1kHz 1kHz 0.1 CS = VCC CS = GND, fSAMPLE = 0Hz At Code FF8h fSAMPLE = 12.5kHz CS =
Texas Instruments
Original
wst 78L05 BR 78L05 SBAS066A

BR 78L05

Abstract: wst 78L05 SAR VREF DOUT +In CDAC Serial Interface ­In S/H Amp Comparator DCLOCK CS/SHDN , DOUT GND 4 5 CS/SHDN PDIP-8, SOIC-8, MSOP-8 PIN DESCRIPTIONS PIN NAME 1 , Input. 4 GND 5 CS/SHDN Ground. 6 DOUT 7 DCLOCK 8 +VCC Chip Select , CS enables the serial output. After one null bit the data is valid for the next 12 edges. Data Clock , µA 2.5 5 5 20 1.3 0.001 CS = VCC CS = GND, fSAMPLE = 0Hz At Code FF8h
Texas Instruments
Original
CS 78L05 sb A615 ADS7817E ADS7817EB ADS7817P ADS7817PB OPS7817

wst 78L05

Abstract: CS 78L05 sb Interface DCLOCK CS/SHDN Please be aware that an important notice concerning availability, standard , VREF +In ­In GND 1 2 ADS7817 3 4 PDIP-8, SOIC-8, MSOP-8 6 5 DOUT CS/SHDN 8 7 +VCC DCLOCK PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 NAME VREF +In ­In GND CS/SHDN DOUT DCLOCK +VCC DESCRIPTION Reference Input , edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After , at at at 1kHz 5kHz 1kHz 1kHz 0.1 CS = VCC CS = GND, fSAMPLE = 0Hz At Code FF8h fSAMPLE = 12.5kHz CS =
Texas Instruments
Original
DSPS6004 delta p

wst+78L05

Abstract: Interface DCLOCK CS/SHDN Please be aware that an important notice concerning availability, standard , VREF +In ­In GND 1 2 ADS7817 3 4 PDIP-8, SOIC-8, MSOP-8 6 5 DOUT CS/SHDN 8 7 +VCC DCLOCK PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 NAME VREF +In ­In GND CS/SHDN DOUT DCLOCK +VCC DESCRIPTION Reference Input , edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After , at at at 1kHz 5kHz 1kHz 1kHz 0.1 CS = VCC CS = GND, fSAMPLE = 0Hz At Code FF8h fSAMPLE = 12.5kHz CS =
Texas Instruments
Original
wst+78L05
Abstract: Interface DCLOCK CS/SHDN Please be aware that an important notice concerning availability, standard , VREF +In ­In GND 1 2 ADS7817 3 4 PDIP-8, SOIC-8, MSOP-8 6 5 DOUT CS/SHDN 8 7 +VCC DCLOCK PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 NAME VREF +In ­In GND CS/SHDN DOUT DCLOCK +VCC DESCRIPTION Reference Input , edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After , at at at 1kHz 5kHz 1kHz 1kHz 0.1 CS = VCC CS = GND, fSAMPLE = 0Hz At Code FF8h fSAMPLE = 12.5kHz CS = Texas Instruments
Original

wst 78L05

Abstract: Interface DCLOCK CS/SHDN Please be aware that an important notice concerning availability, standard , VREF +In ­In GND 1 2 ADS7817 3 4 PDIP-8, SOIC-8, MSOP-8 6 5 DOUT CS/SHDN 8 7 +VCC DCLOCK PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 NAME VREF +In ­In GND CS/SHDN DOUT DCLOCK +VCC DESCRIPTION Reference Input , edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After , at at at 1kHz 5kHz 1kHz 1kHz 0.1 CS = VCC CS = GND, fSAMPLE = 0Hz At Code FF8h fSAMPLE = 12.5kHz CS =
Texas Instruments
Original

BR 78L05

Abstract: Interface DCLOCK CS/SHDN Please be aware that an important notice concerning availability, standard , VREF +In ­In GND 1 2 ADS7817 3 4 PDIP-8, SOIC-8, MSOP-8 6 5 DOUT CS/SHDN 8 7 +VCC DCLOCK PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 NAME VREF +In ­In GND CS/SHDN DOUT DCLOCK +VCC DESCRIPTION Reference Input , edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After , at at at 1kHz 5kHz 1kHz 1kHz 0.1 CS = VCC CS = GND, fSAMPLE = 0Hz At Code FF8h fSAMPLE = 12.5kHz CS =
Texas Instruments
Original
Abstract: Interface DCLOCK CS/SHDN Please be aware that an important notice concerning availability, standard , VREF +In ­In GND 1 2 ADS7817 3 4 PDIP-8, SOIC-8, MSOP-8 6 5 DOUT CS/SHDN 8 7 +VCC DCLOCK PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 NAME VREF +In ­In GND CS/SHDN DOUT DCLOCK +VCC DESCRIPTION Reference Input , edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After , at at at 1kHz 5kHz 1kHz 1kHz 0.1 CS = VCC CS = GND, fSAMPLE = 0Hz At Code FF8h fSAMPLE = 12.5kHz CS = Texas Instruments
Original
Abstract: Interface DCLOCK CS/SHDN Please be aware that an important notice concerning availability, standard , VREF +In ­In GND 1 2 ADS7817 3 4 PDIP-8, SOIC-8, MSOP-8 6 5 DOUT CS/SHDN 8 7 +VCC DCLOCK PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 NAME VREF +In ­In GND CS/SHDN DOUT DCLOCK +VCC DESCRIPTION Reference Input , edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After , at at at 1kHz 5kHz 1kHz 1kHz 0.1 CS = VCC CS = GND, fSAMPLE = 0Hz At Code FF8h fSAMPLE = 12.5kHz CS = Texas Instruments
Original
Abstract: SAR VREF DOUT +In Serial Interface CDAC â'"In S/H Amp Comparator DCLOCK CS/SHDN , DCLOCK ADS7817 â'"In 3 6 DOUT GND 4 5 CS/SHDN PDIP-8, SOIC-8, MSOP-8 PIN , . 3 â'"In Inverting Input. 4 GND 5 CS/SHDN Ground. 6 DOUT 7 DCLOCK , clock pulse after the falling edge of CS enables the serial output. After one null bit the data is valid , 0.001 CS = VCC CS = GND, fSAMPLE = 0Hz At Code FF8h fSAMPLE = 12.5kHz CS = VCC UNITS T T Texas Instruments
Original
ISO/TS16949
Abstract: SAR VREF DOUT +In CDAC Serial Interface â'"In S/H Amp Comparator DCLOCK CS/SHDN , DCLOCK ADS7817 â'"In 3 6 DOUT GND 4 5 CS/SHDN PDIP-8, SOIC-8, MSOP-8 PIN , Inverting Input. Reference Input. 4 GND 5 CS/SHDN Ground. 6 DOUT 7 DCLOCK 8 , after the falling edge of CS enables the serial output. After one null bit the data is valid for the , V V V pF µA â» â» â» â» â» 2.5 5 5 20 1.3 0.001 CS = VCC CS = GND Burr-Brown
Original

CS 78L05 sb

Abstract: wst 78L05 SAR VREF DOUT +In CDAC Serial Interface ­In S/H Amp Comparator DCLOCK CS/SHDN , DOUT GND 4 5 CS/SHDN PDIP-8, SOIC-8, MSOP-8 PIN DESCRIPTIONS PIN NAME 1 , Input. 4 GND 5 CS/SHDN Ground. 6 DOUT 7 DCLOCK 8 +VCC Chip Select , CS enables the serial output. After one null bit the data is valid for the next 12 edges. Data Clock , µA 2.5 5 5 20 1.3 0.001 CS = VCC CS = GND, fSAMPLE = 0Hz At Code FF8h
Texas Instruments
Original
ADS7817PC ADS7817U ADS7817UB
Abstract: SAR VREF DOUT +In CDAC Serial Interface â'"In S/H Amp Comparator DCLOCK CS/SHDN , DCLOCK ADS7817 â'"In 3 6 DOUT GND 4 5 CS/SHDN PDIP-8, SOIC-8, MSOP-8 PIN , Inverting Input. Reference Input. 4 GND 5 CS/SHDN Ground. 6 DOUT 7 DCLOCK 8 , after the falling edge of CS enables the serial output. After one null bit the data is valid for the , V V V pF µA â» â» â» â» â» 2.5 5 5 20 1.3 0.001 CS = VCC CS = GND Texas Instruments
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A615

Abstract: ADS7817 SAR VREF DOUT +In CDAC Serial Interface ­In S/H Amp Comparator DCLOCK CS/SHDN , DOUT GND 4 5 CS/SHDN PDIP-8, SOIC-8, MSOP-8 PIN DESCRIPTIONS PIN NAME 1 , Input. 4 GND 5 CS/SHDN Ground. 6 DOUT 7 DCLOCK 8 +VCC Chip Select , CS enables the serial output. After one null bit the data is valid for the next 12 edges. Data Clock , µA 2.5 5 5 20 1.3 0.001 CS = VCC CS = GND, fSAMPLE = 0Hz At Code FF8h
Texas Instruments
Original
Abstract: Interface DCLOCK CS/SHDN Please be aware that an important notice concerning availability, standard , VREF +In ­In GND 1 2 ADS7817 3 4 PDIP-8, SOIC-8, MSOP-8 6 5 DOUT CS/SHDN 8 7 +VCC DCLOCK PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 NAME VREF +In ­In GND CS/SHDN DOUT DCLOCK +VCC DESCRIPTION Reference Input , edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After , at at at 1kHz 5kHz 1kHz 1kHz 0.1 CS = VCC CS = GND, fSAMPLE = 0Hz At Code FF8h fSAMPLE = 12.5kHz CS = Texas Instruments
Original

wst 78L05

Abstract: Interface DCLOCK CS/SHDN Please be aware that an important notice concerning availability, standard , VREF +In ­In GND 1 2 ADS7817 3 4 PDIP-8, SOIC-8, MSOP-8 6 5 DOUT CS/SHDN 8 7 +VCC DCLOCK PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 NAME VREF +In ­In GND CS/SHDN DOUT DCLOCK +VCC DESCRIPTION Reference Input , edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After , at at at 1kHz 5kHz 1kHz 1kHz 0.1 CS = VCC CS = GND, fSAMPLE = 0Hz At Code FF8h fSAMPLE = 12.5kHz CS =
Texas Instruments
Original

wst 78L05

Abstract: Interface DCLOCK CS/SHDN Please be aware that an important notice concerning availability, standard , VREF +In ­In GND 1 2 ADS7817 3 4 PDIP-8, SOIC-8, MSOP-8 6 5 DOUT CS/SHDN 8 7 +VCC DCLOCK PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 NAME VREF +In ­In GND CS/SHDN DOUT DCLOCK +VCC DESCRIPTION Reference Input , edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After , at at at 1kHz 5kHz 1kHz 1kHz 0.1 CS = VCC CS = GND, fSAMPLE = 0Hz At Code FF8h fSAMPLE = 12.5kHz CS =
Texas Instruments
Original
Abstract: Interface DCLOCK CS/SHDN Please be aware that an important notice concerning availability, standard , VREF +In ­In GND 1 2 ADS7817 3 4 PDIP-8, SOIC-8, MSOP-8 6 5 DOUT CS/SHDN 8 7 +VCC DCLOCK PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 NAME VREF +In ­In GND CS/SHDN DOUT DCLOCK +VCC DESCRIPTION Reference Input , edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After , at at at 1kHz 5kHz 1kHz 1kHz 0.1 CS = VCC CS = GND, fSAMPLE = 0Hz At Code FF8h fSAMPLE = 12.5kHz CS = Texas Instruments
Original

wst 78L05

Abstract: 78L05 Motorola SAR VREF DOUT +In CDAC Serial Interface ­In S/H Amp Comparator DCLOCK CS/SHDN , DOUT GND 4 5 CS/SHDN PDIP-8, SOIC-8, MSOP-8 PIN DESCRIPTIONS PIN NAME 1 , Input. 4 GND 5 CS/SHDN Ground. 6 DOUT 7 DCLOCK 8 +VCC Chip Select , CS enables the serial output. After one null bit the data is valid for the next 12 edges. Data Clock , µA 2.5 5 5 20 1.3 0.001 CS = VCC CS = GND, fSAMPLE = 0Hz At Code FF8h
Texas Instruments
Original
78L05 Motorola marking 78l05 CS 78L05 ISO130

TSC 78L05

Abstract: cm 78l05 TS78L03 DC Input Voltage TS 78L05 ~ T S 7 8L 1 8 TS78L24 Pow er D issipation O perating Junction Tem , rc TS 78L05 E le c tric a l C h a ra c te ris tic s {V in=10V , lout=40m A . 0°C:sTj:s125°C: C , =slouU40mA lO H z s fe l OOKHz; Tj=25°C f= 120H z, 8.5Vs:Virì=z21 V Iout=100m A, Tj=25°C Tj=25°C IOut= 5mA, 0°Cs , 0 H z , 2 1 V iV in s 3 3 V Iout=100m A, Tj=25°C Tj=25"C lout=5m A, 0°Cs:Tjs125oC - - mA , as above. In o rd er to m inim ize dissipation the TS 78L05 is chosen in this application. R esistor
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TSC 78L05 cm 78l05 78L05T 78l05 sot KI 78L05 78L05 sot-89 ST TS78L TS7SL00ACY TS73L00CY 73L00 TS78M TS78LOO
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