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Part Manufacturer Description Datasheet BUY
PIM400K6Z GE Critical Power PIM400 Series; ATCA Board Power Input Module, -36 to -75 Vdc; 400W/10A, I2C Digital Interface & Short pins (3.68mm) visit GE Critical Power
AXA016A0X3-SR12 GE Critical Power 12V Austin SuperLynxTM 16A: Non-Isolated DC-DC Power Module, 10Vdc –14Vdc input; 0.75Vdc to 5.5Vdc output; 16A Output Current, 100Ω Resistor between Sense and Output Pins visit GE Critical Power
AXA016A0X3-SR12Z GE Critical Power 12V Austin SuperLynxTM 16A: Non-Isolated DC-DC Power Module, 10Vdc –14Vdc input; 0.75Vdc to 5.5Vdc output; 16A Output Current, 100Ω Resistor between Sense and Output Pins visit GE Critical Power
EL6201CW-T7 Intersil Corporation SPECIALTY INTERFACE CIRCUIT, PDSO5, SOT-23, 5 PIN visit Intersil
EL6203CW-T13 Intersil Corporation SPECIALTY INTERFACE CIRCUIT, PDSO5, SOT-23, 5 PIN visit Intersil
EL6208CW-T7 Intersil Corporation SPECIALTY INTERFACE CIRCUIT, PDSO6, SOT-23, 6 PIN visit Intersil

CRC-16 pin

Catalog Datasheet MFG & Type PDF Document Tags

30291FA

Abstract: BOSCH 0 281 002 018 . M16C/29 Group 1. Overview 1.6 Pin Description Table 1.6.1 and 1.6.2 describes the available pins , M16C/29 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER REJ03B0072-0030Z Rev.0.30 2004.06.15 1 , CMOS process using a M16C/60 Series CPU core and is packaged in a 64-pin and 80-pin plastic molded QFP , of M16C/29 group 80-pin device. Table 1.2.2 lists performance outline of M16C/29 group 64-pin device. Table 1.2.1. Performance outline of M16C/29 group (80-pin device) Item Performance CPU Number of
Renesas Technology
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30291FA BOSCH 0 281 002 018 engine control module bosch M30290FCHP M30291MAT-XXXHP CRC-16 pin 16-BIT

EP2AGX125

Abstract: EP2AGX190 use by the CRC_ERROR pin. This is the 16-bit CRC that is embedded in every configuration data , Pin Description" on page 10­4 "Error Detection Block" on page 10­5 "Error Detection , engine generates 16 CRC check bits per frame and then stores them into the configuration random access memory (CRAM). The CRAM chain used for storing CRC check bits is 16-bits wide; its length is equal to , software. A single 16-bit CRC calculation is done on a per-frame basis. After it has finished the CRC
Altera
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EP2AGX125 EP2AGX190 EP2AGX260 EP2AGX45 EP2AGX65 AIIGX51010-3

crc 16 verilog

Abstract: EP4SE820 ability (16-bit CRC), which occurs during user mode to be used by the CRC_ERROR pin. If an error , Detection Pin Description" on page 11­5 "Error Detection Block" on page 11­6 "Error Detection , CRC engine generates 16 CRC check bits per frame and then stores them in CRAM. The CRAM chain used for storing the CRC check bits is 16 bits wide and its length is equal to the number of frames in the , Chapter 11: SEU Mitigation in Stratix IV Devices User Mode Error Detection 11­3 A single 16-bit CRC
Altera
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crc 16 verilog EP4SE820 EP4SE230 EP4SE360 EP4SGX180 EP4SGX290 SIV51011-3

implement 16-bit CRC in transmitter and receiver

Abstract: EP3SE50 (16-bit CRC) during user mode, for use by the CRC_ERROR pin. The second type , the configuration stage. A parallel CRC engine generates 16 CRC check bits per frame and then stores , bits is 16 bits in width and its length is equal to the frame length of the device. User Mode Error , process. You set the clock divide factor in the option setting in the Quartus II software. A single 16 , , the resulting 16-bit signature is hex 0000 if there are no detected CRAM bit errors in a frame by the
Altera
Original
implement 16-bit CRC in transmitter and receiver EP3SE50 2N50 SIII51015-1

EP3SE50

Abstract: implement 16-bit CRC in transmitter and receiver checking ability (16-bit CRC) during user mode, for use by the CRC_ERROR pin. If an error occurs , CRC engine generates 16 CRC check bits per frame and stores them into CRAM. The CRAM chain used for storing CRC check bits is 16 bits wide; its length is equal to the number of frames in the device , Stratix III Devices User Mode Error Detection 15­3 A single 16-bit CRC calculation is done on a per-frame basis. Once it has finished the CRC calculation for a frame, the resulting 16-bit signature is
Altera
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error detection codes EP3SL260

CRC16

Abstract: CRC-16 pin supply 1.6. I/O 1.7. Serial interface 1.8. Integrated protection 2. CONNECTION AND MECHANICAL DATA , PROTOCOL 7.1 Error check (CRC-16) 7.2 Master to one slave communication frame 7.3 Broadcast , protected against inverted polarity connection. PINS FUNCTIONS Pin Name In2,In4,In5 In1 In3 InEn , OUT1 (drive ok) = active if drive is OK. OUT2 (Motor Status) = active if motor is stopped. 1.6 , J1 Pin Nr. Clock and direction ( Standard mode ) Pin Name Serial mode 1 + AT Vdc
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CRC-16 CRC16 modbus RS485 A001 ST01 ST57-01C-

WD1100-04

Abstract: in NMOS silicon gate technology and is available in a 20 pin dual-in-line package. FEATURES · · · · · · GENERATES/CHECKS CRC SINGLE +5V SUPPLY LATCHED ERROR OUTPUTS X16 + X1 2 + X5 1(CCITT-16) AUTOMATIC RESET 20 PIN DIP PACKAGE DIN DO CK I S H FC LK NC Q NC C CW E C DOCE I CR C IZ 20 19 18 17 16 15 , complimentary output (pin 16) is set low. These output states will be maintained as long as DIN is held high and , CZ N c nz Vss C Figure 1. WD1100-04 Pin Connections Figure 2. WD1100-04 Block Diagram W
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OCR Scan
WD110004 WD1100 CCITT-16

R8069

Abstract: decoding (including reporting of bipolar violations). Package Options - 24-pin plastic DIP - 24-pin CERDIP - 28-pin PLCC The Bit, Channel and Frame timing signals are available to the system for both , Temperature Blank = 0*C to 70#C E = -40*C to +85*C Package P = 24-pin DIP S = 24-pin CERDIP J = 28-pin , listed by pin number in Figure 3 and shown graphically in Figure 4. INTERFACE SIGNALS DESCRIPTION , R8075 Table 1. R8075 Pin Assignments 24-Pin DIP 28-Pin PLCC 1 2 3 Symbol 1 2 3 4 5
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OCR Scan
R8069 R8070/R8070A R8070 PCM30 28-PIN 24-PIN

BR1220

Abstract: FIPS-197 (16-bit CRC) during user mode, for use by the CRC_ERROR pin. The second type , . A parallel CRC engine generates 16 CRC check bits per frame and then stores them into registers. The configuration random access memory (CRAM) chain used for storing CRC check bits is 16 bits in , process. You set the clock divide factor in the option setting in the Quartus II software. A single 16 , , the resulting 16-bit signature is hex 0000 if there are no detected CRAM bit errors in a frame by the
Altera
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BR1220 FIPS-197 BR2477a SIII51014-1

transponder chip

Abstract: marin transponder Safety (Incl. PIN Code) Laser ROM 3 x 16 bit Adder Write/Read Protection (OTP) Modulator , organised in 125 words of 16 bits, each word can be irreversibly protected against reading or/and writing , . Features · · · 2 kBits EEPROM organized in 125 words of 16 bits 3 words of 16 Bits Laser ROM for , · · · · · · · · · · · Programmable PIN coverage of the memory (0, 25, 50, 75 or 100 % , tags) PIN Code identification linked with counter of false attempts On chip arithmetic operation
EM Microelectronic-Marin
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EM4056 EM4056B6WW11E EM4056B6WP11 EM4056B6CI2LC EM4056B6CB2RC transponder chip marin transponder EM4056B D/438

CRC32C

Abstract: CRC-8 ccitt standard polynomial is given in the tool tip. The default is CRC-16. Polynomial Name Custom CRC-1 CRC , ) PSoC CreatorTM Component Datasheet ® Polynomial Name CRC-8 CRC-8-SAE CRC-10 CRC-12 CRC-15-CAN CRC-16-CCITT 8 8 7 4 6 3 4 2 2 Polynomial x +x +x +x +x +1 x +x +x +x +1 x x x x 10 12 15 16 Use General , , CRCCCITT USB +x +1 CRC-16 CRC-24-Radix64 CRC-32-IEEE802.3 CRC-32C CRC-32K CRC-64-ISO CRC-64-ECMA x 16 24 +x 15 23 +x +1 18 2 x +x +x +x+1 x +x +x 2 +x +x+1 32 28 32 26 +x +x 17
Cypress Semiconductor
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CRC32C CRC-8 ccitt crc 64 CRC32-C
Abstract: MFQ4 HP44 16 TX MFQ3 Mode name (see note 1) TX Sym bol This pin is unused , ultiplexer. Pin No. 17 18 FRS13RZ 19 20 MFD1 MFD2 21 22 MFD3 16 17 18 , timeslot 16. RX2 This pin is unused since the D input of the Tim eslot 16 Receiver is connected , tim eslot 16 is input on this pin. GLOBAL Digital ground,OV. (Note 2) FRS TZS MFD6 , output is high only during tim eslot 16. Symbol MFQ7 Pin No. 39 MFQ8 40 36 37 -
OCR Scan
DS3046-2 MV1403 V1403 CLA60000 FRS13 TXTS16
Abstract: generated from the incoming data stream on the D input pin. CCITT Recommendation G. 704 defines the 16 frame , ) Symbol Pin No. DP48 MFQ3 16 HP44 15 Mode name (see note 1) RX Pin name and description HDB3 Decoder , this input during timeslot 16. This pin is unused since the D input of the Timeslot 16 Receiver is , timeslot 16 is input on this pin. Digital ground,OV. (Note 2) MODE CLK STM P CRC 27 28 29 30 31 25 , pin during timeslot 16. This output is low at all other times. Timeslot Zero Receiver (RXTSZ Zarlink Semiconductor
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RXTS16

rx2 208

Abstract: generated from the incoming data stream on the D input pin. CCITT Recommendation G. 704 defines the 16 frame , ) Symbol Pin No. DP48 MFQ3 16 HP44 15 Mode name (see note 1) RX Pin name and description HDB3 Decoder , this input during timeslot 16. This pin is unused since the D input of the Timeslot 16 Receiver is , timeslot 16 is input on this pin. Digital ground,OV. (Note 2) MODE CLK STM P CRC 27 28 29 30 31 25 , pin during timeslot 16. This output is low at all other times. Timeslot Zero Receiver (RXTSZ
Zarlink Semiconductor
Original
rx2 208

cyclic redundancy check verilog source

Abstract: vhdl code CRC 32 page 8 "Software Support" on page 11 "Recovering from CRC Errors" on page 16 "Conclusion" on page 16 , the operation of the error detection CRC circuitry at the CRC_ERROR pin. Stratix II and Stratix II , register. Table 2 describes the CRC_ERROR pin. Tables 3 and 4 show the CRC_ERROR pin locations for the Stratix and Stratix GX device families. CRC_ERROR Pin-Outs Table 2. CRC_ERROR Pin Description Pin Name Description CRC_ERROR 4 Pin Type I/O, output Active high signal that indicates
Altera
Original
cyclic redundancy check verilog source vhdl code CRC 32 JTAG error detection code in vhdl AN25 EP1S60

HDB3

Abstract: HDB3 to nrz 24 _ 16 17 18 19 20 21 22 23 Pin name and description 11 MV1403 , This pin is unused since the D input of the Timeslot 16 Receiver is connected intermally to the , is high only during timeslot 16. MFQ7 MFQ8 Pin No. 39 40 36 37 Pin name and , bursts produced by this macrocell are output at 2.048MHz on this pin during timeslot 16. This output is , MFD6 LIA 15 34 TZS MFQ3 16 33 FRS MFQ4 17 32 MFD5 MFQ5 18
Zarlink Semiconductor
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FRS15 HDB3 HDB3 to nrz FRS Receiver HDB-3 nrz to hdb3

G703

Abstract: generated from the incoming data stream on the D input pin. CCITT Recommendation G. 704 defines the 16 frame , ) Symbol Pin No. DP48 MFQ3 16 HP44 15 Mode name (see note 1) RX Pin name and description HDB3 Decoder , this input during timeslot 16. This pin is unused since the D input of the Timeslot 16 Receiver is , timeslot 16 is input on this pin. Digital ground,OV. (Note 2) MODE CLK STM P CRC 27 28 29 30 31 25 , pin during timeslot 16. This output is low at all other times. Timeslot Zero Receiver (RXTSZ
Zarlink Semiconductor
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G703

704 mfd

Abstract: CLA60000 24 _ 16 17 18 19 20 21 22 23 Pin name and description 11 MV1403 , This pin is unused since the D input of the Timeslot 16 Receiver is connected intermally to the , is high only during timeslot 16. MFQ7 MFQ8 Pin No. 39 40 36 37 Pin name and , bursts produced by this macrocell are output at 2.048MHz on this pin during timeslot 16. This output is , 14 35 MFD6 LIA 15 34 TZS MFQ3 16 33 FRS MFQ4 17 32 MFD5
Zarlink Semiconductor
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704 mfd T16DS T16DH D-TXTS16

BT806

Abstract: bt8070 D 24-Pin Plastic DIP 16 INCHES MIN. MAX. 1.230 1.260 0.530 0.550 0.140 0.160 0.015 , Options ­ 24-Pin Plastic DIP ­ 28-Pin PLCC RPOS RNEG RX RPOS RNRZ RCLK RNEG RX , . The Bt8075 interface signals are listed by pin number Table 1. This table alsi details pin assignments. Interface signal definitions are given in Table 2. Graphic representation of the pin assignments , Transceiver 24 23 22 21 20 19 18 17 16 15 14 13 TMASYN RMASYN RSP1 TMAX TCLK VSS TSP2
Brooktree
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BT806 bt8070 Bt8069 BT8069B BROOKTREE bt8 l8075 8069B 8070/B 8070A 8075KP 8075KPJ L807501
Abstract: generated from the incoming data stream on the D input pin. CCITT Recommendation G. 704 defines the 16 frame , ) Symbol Pin No. DP48 MFQ3 16 HP44 15 Mode name (see note 1) RX Pin name and description HDB3 Decoder , this input during timeslot 16. This pin is unused since the D input of the Timeslot 16 Receiver is , timeslot 16 is input on this pin. Digital ground,OV. (Note 2) MODE CLK STM P CRC 27 28 29 30 31 25 , pin during timeslot 16. This output is low at all other times. Timeslot Zero Receiver (RXTSZ Zarlink Semiconductor
Original
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