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Part Manufacturer Description Datasheet BUY
SN54F280AJ Texas Instruments F/FAST SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, CDIP14 visit Texas Instruments
SN74AS280NSR Texas Instruments 9-Bit Parity Generators/Checkers 14-SO 0 to 70 visit Texas Instruments Buy
SN74AS280N-10 Texas Instruments AS SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, PDIP14 visit Texas Instruments
SNJ54F280BFK-00 Texas Instruments F/FAST SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, CQCC20 visit Texas Instruments
SN54AS286J-00 Texas Instruments AS SERIES, 9-BIT PARITY GENERATOR/CHECKER, TRUE OUTPUT, CDIP14 visit Texas Instruments
SN74AS280FN Texas Instruments AS SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, PQCC20 visit Texas Instruments

CRC 8 Generator/Checker

Catalog Datasheet MFG & Type PDF Document Tags

CRC-16-ANSI

Abstract: crc 16 verilog Check (CRC) generator and checker CRC-32, CRC-16-ANSI, and CRC-16-CCITT generator polynomials , checksum and uses a dedicated output to indicate if the checksum is correct. The CRC generator and checker , CRC checker -3 64-bit datapath 8 symbols per word CRC16-CCITT Optimize for speed 8 channels , /crcdemo_multichan.v(hd) A Verilog or VHDL example design incorporating a CRC generator, checker, and other , to the CRC checker. Bit-swap checksum Applies only to CRC Generator. Selecting this parameter
Altera
Original
CRC-16-ANSI crc 16 verilog crc verilog code 16 bit ccitt vhdl code CRC 32 CRC-16 ccitt crc 16 verilog ccitt UG-CRC01004-1

vhdl code for 8-bit parity checker

Abstract: vhdl code for 8 bit odd parity checker crc MegaCore Function Parameterized CRC Generator/Checker ® April 1999, ver. 2 Features , cyclic redundancy code (CRC) generator and checker Optimized for the FLEX® device architecture , crc MegaCore Function Parameterized CRC Generator/Checker Data Sheet Parameters Table 1 describes , Generator/Checker Data Sheet Ports Table 2 describes the input and output ports of the crc function , Parameterized CRC Generator/Checker Data Sheet Table 2. crc Ports (Part 2 of 2) Name run_nshift init
Altera
Original
vhdl code for 8-bit parity checker vhdl code for 8 bit odd parity checker vhdl code for parity checker CRC-16 and CRC-32 vhdl code CRC vhdl code for 8-bit odd parity checker 800-EPLD EPF10K10

H8005

Abstract: 04c11db7 crc MegaCore Function ® Parameterized CRC Generator/Checker Data Sheet August 1997, ver. 1 , data General Description The crc MegaCore function is a general-purpose CRC generator and checker , Corporation A-DS-CRC-01 1 crc MegaCore Function Parameterized CRC Generator/Checker Data Sheet AHDL , Function Parameterized CRC Generator/Checker Data Sheet Parameters Table 1 describes the parameters of , Parameterized CRC Generator/Checker Data Sheet Ports Table 2 describes the input and output ports of the crc
Altera
Original
H8005 04c11db7 vhdl code for 3 bit parity checker CRC-32 4F5344CD 340bc

CRC Generator/Checker

Abstract: CRC generator and checker crc MegaCore Function Parameterized CRC Generator/Checker Solution Brief 30 August 1997, ver , a general-purpose CRC generator and checker that validates data frames and ensures that data , MegaCore Function Parameterized CRC Generator/Checker CRCs are particularly effective for two reasons , input CRC-16/CCITT generator polynomial 318 8-bit wide input 896 32 >125 >125 1200 , Go to the crc MegaCore Function Parameterized CRC Generator/Checker Data Sheet for more information
Altera
Original
CRC Generator/Checker CRC generator and checker function generator generator function crc16 ccitt application of parity checker

2653 SIGNETICS

Abstract: X3.28 nak Generator Checker (PGC) Is a polynomial generator checker/character comparator circuit that complements a , December 12, 1986 SCN2653/SCN68653 Polynomial Generator Checker (PGC) Product Specification FEATURES â'¢ Parallel Block Check Character accumulation/checking: CRC-16, CRC-12, LRC-8 â'¢ BISYNC normal and , Signetics Microprocessor Products Product Specification Polynomial Generator Checker (PGC) SCN2653 , Product Specification Polynomial Generator Checker (PGC) SCN2653/SCN68653 Additional PGC applications
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OCR Scan
2653 SIGNETICS X3.28 nak SCN2661 300MIL CRC-12 CRC-16 SCN2653/68653

SCN2651

Abstract: 300MIL Microprocessor Products DESCRIPTION The Signetics SCN2653/68653 Polynomial Generator Checker (PGC) is a polynomial generator checker/character comparator circuit that complements a receiver , December 12, 1986 SCN2653/SCN68653 Polynomial Generator Checker (PGC) Product Specification FEATURES â'¢ Parallel Block Check Character accumulation/checking: CRC-16, CRC-12, LRC-8 â'¢ BISYNC normal and , Polynomial Generator Checker (PGC) SCN2653/SCN68653 ORDERING INFORMATION PACKAGES Vcc = 5V ± 5%, Ta = 0Â
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OCR Scan
SCN2651 SCN2652 SCN2653AC4I16 SCN2653AC4N16 SCN2653ACD16 SCN2663/SCN68653

CRC 9401

Abstract: N9401N Signetics 8X01 A/9401 CRC Generator/Checker Logic Products Product Specification FEATURES , The CRC Generator/Checker (8X01A or 9401) provides error-correction capabilities for digital systems , is automatic. FUNCTIONAL OPERATION 8X01A and 9401 The CRC Generator/Checker circuit provides a , Specification CRC Generator/Checker 8X01A/94CM DC ELECTRICAL CHARACTERISTICS FOR 8X01A VÇ^MINI - 4.75V, VÇC , Signetics Logic Products Product Specification CRC Generator/Checker 8X01A/9401 AC ELECTRICAL
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N8X01A N9401N CRC 9401 n940 N9401 1N3064

crc generator

Abstract: N8X01A Signetics 8X01A/9401 CRC Generator/Checker Product Specification Logic Products FEATURES , identical with 8X01 (8X01A only) VCc = 5V 14-Pin DIP DESCRIPTION The CRC Generator/Checker (8X01A or , Specification CRC Generator/Checker 8X01 A/9401 free, the calculated remainder should satisfy a , Products Product Specification CRC Generator/Checker 8X01 A/9401 DC ELECTRICAL CHARACTERISTICS , Products Product Specification CRC Generator/Checker 8X01A/9401 AC ELECTRICAL CHARACTERISTICS
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crc generator CD07440S
Abstract: 8X01A/9401 CRC Generator/Checker Product Specification Logic Products FEATURES · TTL Inputs , (8X01A only) · Vcc = SV · 14-Pln DIP DESCRIPTION The CRC Generator/Checker (8X01A or 9401) provides , Specification CRC Generator/Checker 8X01 A/9401 free, the calculated remainder should satisfy a , 3-121 Product Specification CRC Generator/Checker 8X01A/9401 DC ELECTRICAL CHARACTERISTICS , Specification CRC Generator/Checker 8X01A/9401 AC ELECTRICAL CHARACTERISTICS FOR 8X01A V cc-5 V , TA -
OCR Scan
00744M

X3.28 nak

Abstract: Checker (PGC) SCN2653/SCN68653 CRC-12: 01 1111 LC R -8 or C R C -16: No VRC o r o dd VRC: 0001 Even , three generator polynomials (CRC-16, CRC-12, and LRC-8) that can be selected to compute the BCC. This , Signetics SCN2653/SCN68653 Polynomial Generator Checker (PGC) Product Specification Microprocessor Products DESCRIPTION The Signetics SCN2653/68653 Polyno mial Generator Checker (PGC) Is a poly , (SSC). FEATURES · Parallel Block Check Character accumulation/checking: CRC-16, CRC-12, LRC-8 ·
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N9401N

Abstract: N9401 Logic Products 8X01 A/9401 CRC Generator/Checker Product Specification FEATURES â'¢ TTL , The CRC Generator/Checker (8X01A or 9401) provides error-correction capabilities for digital systems , CRC Generator/Checker 8X01 A/9401 free, the calculated remainder should satisfy a predetermined , degree less than 16 Is automatic. FUNCTIONAL OPERATION 8X01A and 9401 The CRC Generator/ Checker , Material Copyrighted By Its Respective Manufacturer Product Specification CRC Generator/Checker 8X01 A
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sx01 SX01A C007MM SK01A
Abstract: timeslot 16. Each 16 frame CRC multiframe is divided into two 8 frame submultiframes, denoted , CRC mode (EN=1), the CRC Generator macrocell performs its CRC procedure on this incoming data stream , of the Timeslot Zero Transmitter. The TZS input of the CRC generator is connected directly to the TZS , extract the international spare bits of the CRC multiframe. In non CRC mode, the Cyclic Redundancy Checker , Transmitter is connected internally to the Q output of the CRC Generator. Timeslot Zero Receiver (RXTSZ Zarlink Semiconductor
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MV1403 DS3046-2 CLA60000 TXTS16 RXTS16

rx2 208

Abstract: timeslot 16. Each 16 frame CRC multiframe is divided into two 8 frame submultiframes, denoted , CRC mode (EN=1), the CRC Generator macrocell performs its CRC procedure on this incoming data stream , of the Timeslot Zero Transmitter. The TZS input of the CRC generator is connected directly to the TZS , extract the international spare bits of the CRC multiframe. In non CRC mode, the Cyclic Redundancy Checker , Transmitter is connected internally to the Q output of the CRC Generator. Timeslot Zero Receiver (RXTSZ
Zarlink Semiconductor
Original
rx2 208

marking WR6

Abstract: IN SDLC PROTOCOL Internal TxD CRC Delay Register (8-Bits) MUX SDLC CRC RxD 1-Bit MUX CRC Checker , initialized by issuing the Reset Tx CRC Generator command in WR0, bit 6-7. 4-10 Sync Length 6 bits 8 , Insert (5-Bits) CRC SDLC CRC Generator RxD Transmit Clock RxD Delayed One Bit Figure , the selected clock rate. Synchronous data (except SDLC/HDLC) is shifted to the CRC generator as well as to the transmit multiplexer. SDLC/HDLC data is shifted to the CRC Generator and out through the
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marking WR6 IN SDLC PROTOCOL SDLC WR10 Z16C35ISCCTM

704 mfd

Abstract: CLA60000 multiframe structure in timeslot 16. Each 16 frame CRC multiframe is divided into two 8 frame submultiframes , =1), the CRC Generator macrocell performs its CRC procedure on this incoming data stream. In non-CRC mode , Timeslot Zero Transmitter. The TZS input of the CRC generator is connected directly to the TZS output of , . Figure 8: HDB3 decoder timing - macrocell decoding HDB3 data and detecting errors When in non CRC mode , CRC mode, the Cyclic Redundancy Checker's error outputs are disabled by the alarm gating circuitry
Zarlink Semiconductor
Original
FRS13 FRS15 704 mfd FRS13RZ T16DS T16DH D-TXTS16
Abstract: timeslot 16. Each 16 frame CRC multiframe is divided into two 8 frame submultiframes, denoted , CRC mode (EN=1), the CRC Generator macrocell performs its CRC procedure on this incoming data stream , of the Timeslot Zero Transmitter. The TZS input of the CRC generator is connected directly to the TZS , extract the international spare bits of the CRC multiframe. In non CRC mode, the Cyclic Redundancy Checker , Transmitter is connected internally to the Q output of the CRC Generator. Timeslot Zero Receiver (RXTSZ Zarlink Semiconductor
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Serial RapidIO

Abstract: physical layer interface /F RX CRC Checker RX Receive Pkt Ack Ctrl PMI Interface Phy Layer Management I/F , Generator TX USER Interface TX USR I/F TX Packet/ Control Assy 8 64 TX SERDES Interface Block 4 TD 32 TD_N TX Serial RapidIO I/F TX CRC Generator Soft IP Core FPSC , control symbols. The data packets are sent to the RX CRC Checker and the control symbols are sent to RX , Ack Ctrl blocks, which takes the appropriate actions. Finally the data from the RX CRC Checker is
Lattice Semiconductor
Original
ORT42G5 RIO-SERI-T42G5-N1 Serial RapidIO physical layer interface ORT82G5 RAPIDIO 8B/10B ORT82G5/ORT42G5 ORT82G5/ ORT42G5-2BM484

dock

Abstract: WD1100 Western Digital WD1100-04 CRC Generator/Checker DESCRIPTION The WD1100-04 CRC Generator/Checker is , falling edge shifts data bits into the CRC generator/checker. It also transfers the CRC check word to DOUT , CRCOK (pin 13) is set high. Accordingly the write modes) the CRC generator/checker is initialized by , INITIALIZE When this line is at a logic 0, the SKPCLK output line is held high and the CRC generator is held , against a known CRC word. Complimentary latched "CRCOK" outputs are provided to indicate CRC errors in
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WD1100 dock SA1000 CCITT-16 WD110CH
Abstract: timeslot 16. Each 16 frame CRC multiframe is divided into two 8 frame submultiframes, denoted , CRC mode (EN=1), the CRC Generator macrocell performs its CRC procedure on this incoming data stream , of the Timeslot Zero Transmitter. The TZS input of the CRC generator is connected directly to the TZS , extract the international spare bits of the CRC multiframe. In non CRC mode, the Cyclic Redundancy Checker , Transmitter is connected internally to the Q output of the CRC Generator. Timeslot Zero Receiver (RXTSZ Zarlink Semiconductor
Original
DS3046
Abstract: timeslot 16. Each 16 frame CRC multiframe is divided into two 8 frame submultiframes, denoted , CRC mode (EN=1), the CRC Generator macrocell performs its CRC procedure on this incoming data stream , of the Timeslot Zero Transmitter. The TZS input of the CRC generator is connected directly to the TZS , extract the international spare bits of the CRC multiframe. In non CRC mode, the Cyclic Redundancy Checker , Transmitter is connected internally to the Q output of the CRC Generator. Timeslot Zero Receiver (RXTSZ Zarlink Semiconductor
Original
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