NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: crc MegaCore Function Parameterized CRC Generator/Checker Solution Brief 30 August 1997, ver. , a general-purpose CRC generator and checker that validates data frames and ensures that data , MegaCore TM crc MegaCore Function Parameterized CRC Generator/Checker CRCs are particularly , input CRC-16/CCITT generator polynomial 318 8-bit wide input 896 32 >125 >125 1200 , to the crc MegaCore Function Parameterized CRC Generator/Checker Data Sheet for more information. ... | Original |
2 pages, |
CRC 8 Generator/Checker application of parity checker generator function function generator CRC-32 CRC-16 ccitt CRC generator and checker CRC-16 and CRC-32 CRC Generator/Checker datasheet abstract |
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| Abstract: crc MegaCore Function Parameterized CRC Generator/Checker ® April 1999, ver. 2 Features , cyclic redundancy code (CRC) generator and checker Optimized for the FLEX® device architecture , crc MegaCore Function Parameterized CRC Generator/Checker Data Sheet Parameters Table 1 describes , Generator/Checker Data Sheet Ports Table 2 describes the input and output ports of the crc function. , Generator/Checker Data Sheet Table 2. crc Ports (Part 2 of 2) Name run_nshift init[WIDTH-1.0 ... | Original |
8 pages, |
crc-16 implementation CRC-16 CRC-32 CRC-16 ccitt CBF43926 vhdl code CRC32 vhdl code CRC 32 04C11DB7 CRC Generator/Checker h8005 Cyclic Redundancy Check simulation CRC 8 Generator/Checker vhdl code CRC datasheet abstract |
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| Abstract: STATUS REGISTER IRQ DATA QUALITY REGISTER uCONTROLLER INTERFACE 8 VDD D0 D1 D2 D3 D4 D5 D6 D7 COMMAND REGISTER DATA BUS BUFFERS MODE REGISTER CONTROL REGISTER DATA BUFFER WR RD CS A0 A1 CRC GENERATOR/ CHECKER FEC GENERATOR/ CHECKER ADDRESS AND R/W DECODE FRAME SYNC DETECT INTERLEAVE/ DE-INTERLEAVE VBIAS VSS Tx Bits Rx Fb Rx Bits SCRAMBLE/ DE-SCRAMBLE DOC 1 Tx Rx XTAL Rx - Rx IN VBIAS ... | Original |
1 pages, |
CRC 8 Generator/Checker Clock Oscillator checker "Lowpass Filter" CRC Generator/Checker datasheet abstract |
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| Abstract: STATUS REGISTER IRQ DATA QUALITY REGISTER uCONTROLLER INTERFACE 8 VDD D0 D1 D2 D3 D4 D5 D6 D7 COMMAND REGISTER DATA BUS BUFFERS MODE REGISTER CONTROL REGISTER DATA BUFFER WR RD CS A0 A1 CRC GENERATOR/ CHECKER FEC GENERATOR/ CHECKER ADDRESS AND R/W DECODE FRAME SYNC DETECT INTERLEAVE/ DE-INTERLEAVE VBIAS VSS Tx Bits Rx Fb Rx Bits SCRAMBLE/ DE-SCRAMBLE DOC 1 Tx Rx XTAL Rx - Rx IN VBIAS ... | Original |
1 pages, |
CRC Generator/Checker CRC 8 Generator/Checker Clock Oscillator datasheet abstract |
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| Abstract: /PARALLEL CONVERTER WD1100-02 WD1100-02 MFM GENERATOR WD1100-12 WD1100-12 IMPROVED MFM GENERATOR WD1100-03 WD1100-03 AM DETECTOR WD1100-04 WD1100-04 CRC GENERATOR/CHECKER WD1100-05 WD1100-05 PAR/SERIAL CONVERTER WD1100-06 WD1100-06 ECC/CRC LOGIC WD1100-07 WD1100-07 HOST INTERFACE , WCLK â-¡ CRCOK â-¡ SKPCLK ^ DOUT WD1100-04 WD1100-04 CRC GENERATOR/CHECKER DO C D1C D2 â-¡ D3 [Z D4 [Z D5 [Z D6 [Z D7C , have been designed to read and convert an MFM data stream into 8-bit parallel bytes. During a write , and detected while CRC bytes can be appended and checked on the data stream. The WD1100 WD1100 is fabricated ... | OCR Scan |
2 pages, |
WD1100-12 WD1100-09 WD1100-07 WD1100-06 WD1100-05 WD1100-04 WD1100-03 WD1100-01 WD1100 WD1100-02 WD1100 abstract |
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| Abstract: Western Digital WD1100-04 WD1100-04 CRC Generator/Checker DESCRIPTION The WD1100-04 WD1100-04 CRC Generator/Checker is , the CRC generator/checker. It also transfers the CRC check word to DOUT in the write mode (DOCE = LOW , the write modes) the CRC generator/checker is initialized by complimentary output (pin 16) is set low. , logic 0, the SKPCLK output line is held high and the CRC generator is held preset to hex "FFFF." 9 N.C. , against a known CRC word. Complimentary latched "CRCOK" outputs are provided to indicate CRC errors in ... | OCR Scan |
4 pages, |
WD1100-04 WD1100 SA1000 WD1100-04 abstract |
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| Abstract: WESTERN DIGITAL COR.P ORATION WD1100-04 WD1100-04 CRC Generator/Checker o 0 1 o DESCRIPTION The WD1100-04 WD1100-04 CRC Generator / Checker is designed to generate a Cyclic Redundancy Checkword from a serial data stream, and to check a data stream against a known CRC word. Complimentary latched "CRCOK" outputs are , shifting data through the device (either in the read or write modes) the CRC generator/checker is , SHIFT CLOCK The falling edge shifts data bits into the CRC aenerator/checker. It also transfers the CRC ... | OCR Scan |
4 pages, |
WD1100 SA1000 WD1100-04 WD1100-04 abstract |
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| Abstract: Programmable Interrupt Controller Data Sheet crc MegaCore Function Parameterized CRC Generator/Checker Data , Controller Megafunction SB 30 crc MegaCore Function Parameterized CRC Generator/Checker SB 32 , Controlled Oscillator Megafunction SB 6 PCI Bus Target Megafunction SB 8 ADPCM Megafunction SB ... | Original |
4 pages, |
ieee floating point sb transistors a8255 CAN BUS megafunction generator function synchronizer megafunction iir filter applications function generator catalog 5 bit multiplier using adders datasheet abstract |
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| Abstract: Cyclic Redundancy Check (CRC) generator and checker CRC-32, CRC-16-ANSI, and CRC-16-CCITT generator , CRC Compiler Release Notes December 2006, Version 6.1 These release notes for the CRC , This CRC Compiler has the same system requirements as the Quartus II software. For system , from 1 bit to 256 bits Any CRC starting value Built-in support for the following: Inverting output , 1 Preliminary CRC Compiler Errata Fixed in This Release No errata were fixed for this ... | Original |
3 pages, |
CRC16-CCITT CRC generator and checker CRC-16 avalon vhdl CRC-16-CCIT CRC-32 crc 16 verilog ccitt CRC-16-CCITT CRC-16 ccitt CRC-16 and CRC-32 crc 16 verilog CRC-16-ANSI datasheet abstract |
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| Abstract: Low Power Hex TTL-to-ECL Translator PLCC Other 5 74F401 74F401 FAST CRC Generator/Checker , 9-Input Parity Checker/Generator DIP 5 74AC280 74AC280 FACT 9-Bit Parity Generator/Checker SOIC SOP 3.3 5 DM74AS280 DM74AS280 Bipolar-AS 9-Bit Parity Generator/Checker DIP SOIC 5 , 9-Bit Parity Generator/Checker With Bus-Driver Parity I/O Port SOIC 5 MM74C89 MM74C89 74C CMOS , Monostable Multivibrator DIP SOIC SOP 5 74F280 74F280 FAST 9-Bit Parity Generator/Checker DIP ... | Original |
6 pages, |
parity and crc bit adder low voltage function generator MM74C14 MM74C912 mm74c914 CMOS Multivibrator cmos function generator monostable ttl CD4046BC astable clock generator 4 bit full adder dip DIP CRYSTAL DM9602 DM96L02 DM9602 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| .vhd - - SMPTE 292M-1998 292M-1998 292M-1998 292M-1998 HD-SDI receiver CRC checker - - - - Author: John F. Snow ); - CRC output value end component; begin - - CRC generator modules - crc _out => y_calc_crc); - - trslncrc generator - - This code generates timing - - The crc_clr signal controls when the CRC generator's accumulation - register gets reset to ' then if trslncrc(5) = '1' then c_rx_crc(8 downto 0) www.datasheetarchive.com/download/91397821-996025ZC/xapp681.zip (hdsdi_rx_crc.vhd) |
Xilinx | 09/01/2004 | 89.65 Kb | ZIP | xapp681.zip |
| COP8 CRC include file. General about CRC CRC (cyclic redundency check) is widly used in applications ranging from floppy disk drivers to logic circuit testing (in the guise if 'signature analysis'). This program uses a 9 bit generator (msb 100110001 lsb) to generate a 8 bit CRC. To easely understand how our CRC generator works we have include a small test program (test.asm). www.datasheetarchive.com/files/national/software/misc/crc/readme.txt |
National | 15/10/1997 | 0.39 Kb | TXT | readme.txt |
| .v // // SMPTE 292M-1998 292M-1998 292M-1998 292M-1998 HD-SDI receiver CRC checker // // // // Author: John F. Snow :0] c_line_num_int; reg [6:0] y_line_num_int; // // CRC generator modules // hdsdi_crc ) ); // // trslncrc generator // // This code generates timing signals indicating where the CRC and LN words // are crc_clr signal controls when the CRC generator's accumulation register // gets reset to begin c_rx_crc[8:0] www.datasheetarchive.com/download/91397821-996025ZC/xapp681.zip (hdsdi_rx_crc.v) |
Xilinx | 09/01/2004 | 89.65 Kb | ZIP | xapp681.zip |
| Serial Data Polynomial Generator/Checker General Description Features Datasheet Package Serial Data Polynomial Generator Checker 177 Kbytes 9-Dec-97 View Online Download Receive Polynomial generator/checker is an expandable version of the 'F401. It provides an advanced tool for the input selects one-of-six generator polynomials. The list of polynomials includes CRC-16, CRC-CCITT and production N/A N/A 50+ $19.60 rail of 50 NSZSSXXYYA 54F402 54F402 54F402 54F402 LMQB /QL> 5962- 9059301M2A 9059301M2A 9059301M2A 9059301M2A 8-9 weeks 500 5962 www.datasheetarchive.com/files/national/54f402.html |
National | 25/09/2003 | 9.82 Kb | HTML | 54f402.html |
| signature" return: CRC arg1: CRC init value arg2: CRC generator polynomial arg3: pointer to " return: CRC arg1: CRC init value arg2: pointer to CRC table (specific to generator polynomial ; unsigned char msg; unsigned short temp; temp = *pmsg+ = (*pmsg+ > 15) crc long)(*pmsg+) www.datasheetarchive.com/download/46639413-922160ZC/slaa221.zip (crc_algs.c) |
Texas Instruments | 24/01/2005 | 234.56 Kb | ZIP | slaa221.zip |
| - shifted into the CRC generator, although the implementation given here is a - fully parallel CRC ); crc(8) ) xor c(2); crc(13) - - edh_crc16.vhd - - 16-bit SDI CRC Calculation - - - - Author: John F. Snow www.datasheetarchive.com/download/14784420-995965ZC/xapp299.zip (edh_crc16.vhd) |
Xilinx | 17/05/2002 | 200.97 Kb | ZIP | xapp299.zip |
| shifted into the CRC generator, although the implementation given here is a fully parallel CRC [11]; assign crc[7] = d[1] ^ c[1] ^ crc[12]; assign crc[8] = d[2] ^ c[2] ^ crc[13]; assign crc[9 ] = d[8] ^ c[8] ^ t1; assign crc[15] = d[9] ^ c[9] ^ crc[11]; endmodule //- // edh_crc16.v // // 16-bit SDI CRC Calculation // // // // Author: John F. Snow www.datasheetarchive.com/download/14784420-995965ZC/xapp299.zip (edh_crc16.v) |
Xilinx | 17/05/2002 | 200.97 Kb | ZIP | xapp299.zip |
| as - the first bit shifted into the CRC generator, although the implementation - given here is crc(17); newcrc(8) - - hdsdi_crc.vhd - - 18-bit HD-SDI CRC Calculation - - - - Author: John F. Snow www.datasheetarchive.com/download/58955026-996027ZC/xapp683.zip (hdsdi_crc.vhd) |
Xilinx | 15/03/2004 | 67.57 Kb | ZIP | xapp683.zip |
| as - the first bit shifted into the CRC generator, although the implementation - given here is crc(17); newcrc(8) - - hdsdi_crc.vhd - - 18-bit HD-SDI CRC Calculation - - - - Author: John F. Snow www.datasheetarchive.com/download/72452944-996024ZC/xapp680.zip (hdsdi_crc.vhd) |
Xilinx | 07/01/2004 | 92.02 Kb | ZIP | xapp680.zip |
| as - the first bit shifted into the CRC generator, although the implementation - given here is crc(17); newcrc(8) . - \ \ Filename: $RCSfile: hdsdi_crc.vhd,rcs $ - / / Date Last Modified: $Date: 2004-08-23 13 : hdsdi_crc.vhd,rcs $ - Revision 1.1 2004-08-23 13:23:19-06 jsnow - Comment changes only www.datasheetarchive.com/download/58948463-996028ZC/xapp684.zip (hdsdi_crc.vhd) |
Xilinx | 22/09/2004 | 2253.89 Kb | ZIP | xapp684.zip |