AEC-Q100 CR2032 CIP-51 Si4010-GT MSOP-10 Si4010-C2-GS SOIC-14 Si4010-C2-AT - Datasheet Archive

 

CRYSTAL-LESS SOC RF TRANSMITTER Single Coin-cell Battery Transmitter Supply voltage: 1.8 to 3.6 V Standby current < 10 nA

 

Si4010 CRYSTAL-LESS SOC RF TRANSMITTER Single Coin-cell Battery Transmitter Supply voltage: 1.8 to 3.6 V Standby current < 10 nA Crystal-less operation Temperature range ­40 to +85 °C Automotive quality option, AEC-Q100 AEC-Q100 10-pin MSOP/14-pin SOIC Pb free/RoHS compliant RF Transmitter Frequency range: 27-960 MHz +10 dBm output power, adjustable Automatic antenna tuning Symbol rate up to 100 kbps FSK/OOK modulation Manchester, NRZ, 4/5 encoder Analog Peripherals LDO regulator with POR circuit Integrated temperature sensor Battery voltage monitor High-Speed 8051 µC Core Pipeline instruction architecture 70% of instructions in 1 or 2 clocks Up to 24 MIPs with 24 MHz clock Memory 4 kB RAM/8kB NVM 128 bit EEPROM 256 byte of internal data RAM 256 byte of external data RAM (XREG) 12 kB ROM embedded functions 8 byte low leakage RAM Digital Peripherals 128 bit AES Accelerator 4/8 GPIO with wakeup functionality 1 LED driver Data serializer High-speed frequency counter RTC, Timers 2, 3 On-chip debugging - C2 Clock Sources High-speed crystal-less VCO Programmable low-power osc - LPOSC Ultra low-power sleep timer Optional crystal oscillator input Applications Garage and gate door openers Home automation and security Remote keyless entry VDD Si4010 LDO REGULATOR CR2032 CR2032 COIN CELL GND 1.8 ­ 3.6 V TXP DIVIDER PA LOOP ANTENNA TXM FSK VDD OOK INTEGRATED 8051 MCU LED GPIO PUSH BUTTONS 4/8 Rev. 0.6 9/10 I/O INTERFACE RAM/ ROM NVM 8 Kbyte Copyright © 2010 by Silicon Laboratories EEPROM 128-bit Si4010 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Si4010 2 Rev. 0.6 Si4010 TABLE O F C ONTENTS 1. System Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2. Test Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.1. Si4010 Used in a 5-Button RKE System with LED Indicator . . . . . . . . . . . . . . . . . . . 14 3.2. Si4010 with an External Crystal in a 4-Button RKE System with LED Indicator . . . . 14 4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1. MSOP, Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2. MSOP, Programming/Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3. SOIC Package, Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.4. SOIC Package, Programming/debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6. Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 6.1. 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2. 14-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7. PCB Land Pattern 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8. PCB Land Pattern 14-pin SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10. System Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.2. Setting Basic Si4010 Transmit Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.2.1. Package Type. 35 10.2.2. Output Power. 35 10.2.3. Modulation, Encoding, and Data Rate. 37 10.2.4. Output Frequency. 37 10.2.5. Battery Life Calculation. 38 10.3. Applications Programming Interface (API) Commands. 39 11. Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11.1. Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 12. Output Data Serializer (ODS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12.1. Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 12.2. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 12.3. Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 13. LC Oscillator (LCOSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 13.1. Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 14. Low Power Oscillator and System Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 14.1. Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 15. Crystal Oscillator (XO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 15.1. Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 16. Frequency Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 16.1. Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 17. Sleep Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 18. Bandgap and LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 19. Low Leakage HVRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 3 Rev. 0.6 Si4010 20. Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 21. CIP-51 CIP-51 Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 21.1. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 21.1.1. Instruction and CPU Timing. 62 21.2. CIP-51 CIP-51 Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 22. Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 22.1. Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 22.2. Internal Data Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 22.3. External Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 22.4. General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 22.5. Bit Addressable Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 22.6. Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 22.7. Special Function Registers (SFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 22.8. Registers Mapped to XDATA Address Space (XREG) . . . . . . . . . . . . . . . . . . . . . . 73 22.9. NVM (OTP) Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 22.10. MTP (EEPROM) Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 23. System Boot and NVM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 23.1. Startup Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 23.2. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 23.3. Chip Program Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 23.4. NVM Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 23.5. Device Boot Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 23.6. Error Handling During Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 23.7. CODE/XDATA RAM Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 23.8. Boot Status Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 23.9. Boot Routine Destination Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 23.10. NVM Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 23.11. Retest and Retest Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 23.12. Boot and Retest Protection Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 23.13. Chip Protection Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 24. On-Chip Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 24.1. Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 24.2. XREG Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 25. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 25.1. MCU Interrupt Sources and Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 25.2. Interrupt Priorities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 25.3. Interrupt Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 25.4. Interrupt Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 25.5. External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 26. Power Management Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 26.1. Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 26.2. Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 27. AES Hardware Accelerator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 27.1. AES SFR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 28. Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 28.1. Device Boot Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 4 Rev. 0.6 Si4010 28.2. External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 28.3. Software Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 29. Port Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 29.1. GPIO Pin Special Roles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 29.2. Pullup Roff Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 29.3. Matrix Mode Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 29.4. Pullup Roff and Matrix Mode Option Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 29.5. Special GPIO Modes Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 29.6. LED Driver on GPIO[5]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 30. Clock Output Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 30.1. Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 31. Control and System Setting Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 32. Real Time Clock Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 32.1. RTC Interrupt Flag Time Uniformity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 32.2. Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 33. Timers 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 33.1. Interrupt Flag Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 33.2. 16-bit Timer with Auto Reload (Wide Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 33.3. 16-bit Capture Mode (Wide Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 33.4. 8-bit Timer/Timer Mode (Split Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 33.5. 8-bit Capture/Capture Mode (Split Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 33.6. 8-bit Timer/Capture Mode (Split Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 34. C2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 34.1. C2 Pin Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 35. IDE Development Environment and Debugging Chain . . . . . . . . . . . . . . . . . . . . . . . . 155 35.1. Functionality Limitations While Using IDE Development Environment . . . . . . . . . 155 35.2. Chip Shutdown Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 35.3. LED Driver Usage while Using IDE Debugging Chain . . . . . . . . . . . . . . . . . . . . . . 156 35.4. LED Driver and Application Development Issues . . . . . . . . . . . . . . . . . . . . . . . . . 157 36. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Rev. 0.6 5 Si4010 L I S T OF F IGURES Figure 1.1. Si4010 Block Diagram .12 Figure 2.1. Test Block Diagram with 10-pin MSOP . 13 Figure 3.1. Si4010 Used in a 5-button RKE System with LED Indicator . 14 Figure 3.2. Si4010 with an External Crystal in a 4-button RKE System with LED Indicator 14 Figure 6.1. 10-pin MSOP Package . 20 Figure 6.2. 14-pin SOIC Package . 21 Figure 7.1. 10-Pin MSOP Recommended PCB Land Pattern . 22 Figure 8.1. 14-pin SOIC Recommended PCB Land Pattern . 24 Figure 10.1. Functional Block Diagram . 33 Figure 11.1. Simplified PA Block Diagram . 42 Figure 12.1. OOK Timing Example . 46 Figure 12.2. FSK Timing Example . 46 Figure 16.1. Frequency Counter Block Diagram . 56 Figure 21.1. CIP-51 CIP-51 Block Diagram . 61 Figure 22.1. Address Space Map after the Boot . 71 Figure 23.1. NVM Address Map .78 Figure 23.2. CODE/XDATA RAM Address Map . 80 Figure 23.3. Boot Routine Destination CPU Address Space for Copy from NVM . 84 Figure 29.1. Device Package and Port Assignments . 112 Figure 29.2. GPIO[3:1] Functional Diagram . 114 Figure 29.3. Other GPIO Functional Diagram .114 Figure 29.4. Push Button Organization in Matrix Mode . 117 Figure 29.5. GPIO[5] LED Driver Block Diagram . 121 Figure 30.1. Output Clock Generator Block Diagram . 127 Figure 32.1. RTC Timer Block Diagram . 132 Figure 33.1. Timer Interrupt Generation . 136 Figure 33.2. Timer 16-bit Mode Block Diagram (Wide Mode) . 137 Figure 33.3. Capture 16-bit Mode Block Diagram (Wide Mode) .138 Figure 33.4. Two 8-bit Timers in Timer/Timer Configuration (Split Mode) . 139 Figure 33.5. Two 8-bit Timers in Capture/Capture Configuration (Split Mode) . 140 Figure 33.6. Two 8-bit TImers in Timer/Capture Configuration (Split Mode) . 141 Figure 33.7. Two 8-bit Timers In Capture/Timer Configuration (Split Mode) . 142 Figure 34.1. 10-pin C2 USB Debugging Adapter Connection to Device . 152 Figure 34.2. 14-pin C2 ToolStick Connection to Device . 154 6 Rev. 0.6 List of Ta bles L I S T OF TABLES Table 4.1. Product Selection Guide . 15 Table 6.1. Package Dimensions . 20 Table 6.2. Package Dimensions . 21 Table 7.1. 10-Pin MSOP Dimensions . 23 Table 8.1. PCB Land Pattern Dimensions . 25 Table 9.1. Recommended Operating Conditions . 26 Table 9.2. Absolute Maximum Ratings1,2 . 26 Table 9.3. DC Characteristics . 27 Table 9.4. Si4010 RF Transmitter Characteristics .28 Table 9.5. Low Battery Detector Characteristics . 31 Table 9.6. Optional Crystal Oscillator Characteristics . 31 Table 9.7. EEPROM Characteristics .31 Table 9.8. Low Power Oscillator Characteristics . 32 Table 9.9. Sleep Timer Characteristics . 32 Table 21.1. CIP-51 CIP-51 Instruction Set Summary .63 Table 23.1. Boot XDATA Status Variables . 81 Table 23.2. Run Chip Retest Protection Flags: NVM Programmer . 86 Table 24.1. Special Function Register (SFR) Memory Map . 90 Table 24.2. Special Function Registers . 91 Table 24.3. XREG Register Memory Map in External Memory . 94 Table 24.4. XREG Registers . 95 Table 25.1. Interrupt Summary . 98 Table 29.1. 10­Pin Mode . 113 Table 29.2. 14­Pin Mode . 113 Table 29.3. GPIO Special Roles . 115 Table 29.4. GPIO Special Roles Control and Order . 120 Rev. 0.6 7 Si4010 L I S T OF XREG R EGISTERS XREG Definition 11.2. wPA_CAP . 44 XREG Definition 11.3. bPA_TRIM . 45 XREG Definition 14.1. bLPOSC_TRIM . 53 XREG Definition 15.1. bXO_CTRL . 55 XREG Definition 16.3. lFC_COUNT . 59 XREG Definition 22.1. abMTP_RDATA[16] . 74 8 Rev. 0.6 Si4010 L I S T OF S F R R EGISTERS SFR Definition 11.1. PA_LVL .44 SFR Definition 12.1. ODS_CTRL . 47 SFR Definition 12.2. ODS_TIMING .48 SFR Definition 12.3. ODS_DATA . 49 SFR Definition 12.4. ODS_RATEL . 49 SFR Definition 12.5. ODS_RATEH .50 SFR Definition 12.6. ODS_WARM1 . 50 SFR Definition 12.7. ODS_WARM2 . 51 SFR Definition 13.1. LC_FSK .52 SFR Definition 14.2. SYSGEN .54 SFR Definition 16.1. FC_CTRL . 58 SFR Definition 16.2. FC_INTERVAL . 59 SFR Definition 21.1. DPL . 67 SFR Definition 21.2. DPH . 67 SFR Definition 21.3. SP . 68 SFR Definition 21.4. ACC . 68 SFR Definition 21.5. B . 69 SFR Definition 21.6. PSW .70 SFR Definition 23.1. BOOT_BOOTSTAT . 82 SFR Definition 23.2. BOOT_FLAGS . 83 SFR Definition 23.3. PROT3_CTRL . 88 SFR Definition 23.4. PROT0_CTRL . 89 SFR Definition 25.1. IE . 99 SFR Definition 25.2. IP . 100 SFR Definition 25.3. EIE1 .101 SFR Definition 25.4. EIP1 .102 SFR Definition 25.5. INT_FLAGS . 103 SFR Definition 25.6. PORT_INTCFG . 105 SFR Definition 26.1. PCON . 107 SFR Definition 27.1. GFM_DATA . 109 SFR Definition 27.2. GFM_CONST .109 SFR Definition 27.3. SBOX_DATA . 110 SFR Definition 29.1. P0 . 122 SFR Definition 29.2. P0CON . 123 SFR Definition 29.3. P1 . 123 SFR Definition 29.4. P1CON . 124 SFR Definition 29.5. P2 . 124 SFR Definition 29.6. PORT_CTRL . 125 SFR Definition 29.7. PORT_SET . 126 SFR Definition 30.1. CLKOUT_SET . 128 SFR Definition 31.1. GPR_CTRL . 130 SFR Definition 31.2. GPR_DATA . 130 SFR Definition 31.3. RBIT_DATA . 131 9 Rev. 0.6 Si4010 SFR Definition 32.1. RTC_CTRL . 134 SFR Definition 33.1. TMR_CLKSEL . 143 SFR Definition 33.2. TMR2CTRL . 144 SFR Definition 33.3. TMR2RL . 146 SFR Definition 33.4. TMR2RH .146 SFR Definition 33.5. TMR2L . 147 SFR Definition 33.6. TMR2H . 147 SFR Definition 33.7. TMR3CTRL . 148 SFR Definition 33.8. TMR3RL . 150 SFR Definition 33.9. TMR3RH .150 SFR Definition 33.10. TMR3L . 151 SFR Definition 33.11. TMR3H . 151 10 Rev. 0.6 Si4010 1. System Overview The Si4010 is a fully integrated crystal-less CMOS SoC RF transmitter with an embedded CIP-51 CIP-51 8051 MCU designed for the sub 1 GHz ISM frequency bands. This chip is optimized for battery powered applications with operating voltages from 1.8 to 3.6 V and ultra-low current consumption with a standby current of less than 10 nA. The high power amplifier can supply up to +10 dBm output power with 19.5 dB of programmable range. Moreover, the SoC transmitter includes a patented antenna tuning circuit that automatically fine tunes the resonance frequency and impedance matching between the PA output and the connected antenna for optimum transmit efficiency and low harmonic content. FSK and OOK modulation is supported with symbol rates up to 100 kbps. Like all wireless devices, users are responsible for complying with applicable local regulatory requirements for radio transmissions. The embedded CIP-51 CIP-51 8051 MCU provides the core functionality of the Si4010. User software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings. A space of 8 kB of on-chip one-time programmable NVM memory is available to store the user program and can also store unique transmit IDs. In case of power outages due to battery removal, 128 bits of EEPROM is available for counter or other operations providing non-volatile storage capability. A library of useful software functions such as AES encryption, a patented 32-bit counter providing 1 M cycles of read/write endurance, and many other functions are included in the 12 kB of ROM to reduce user design time and code space. General purpose input/output pins with push button wake-on touch capability, a programmable system clock, and ultra low power timers are also available to further reduce current consumption. The Si4010 includes Silicon Laboratories' 2-wire C2 Debug and Programming interface. This debug logic supports memory inspection, viewing and modification of special function registers (SFR), setting break points, single stepping, and run and halt commands. All analog and digital peripherals are fully functional while debugging using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins. The device leverages Silicon Labs' patented and proven crystal-less oscillator technology and offers better than ±150 ppm carrier frequency stability over the temperature range of 0 to + 70 °C and ±250 ppm carrier frequency stability over the industrial range of ­40 to + 85 °C without the use of an external crystal or frequency reference. The internal MCU automatically calibrates the on-chip voltage controlled oscillator (LCOSC) which forms the output carrier frequency for process and temperature variations. An external 1pin crystal oscillator option is available for applications requiring tighter frequency tolerances. Digital integration reduces the amount of required external components compared to traditional offerings, resulting in a solution that only requires a printed circuit board (PCB) implementation area of approximately 25 by 50 mm (including battery, switches, and 25 mm2 antenna). The high integration of the Si4010 improves the system manufacturing reliability and quality and minimizes costs. This chip offers industry leading RF performance, high integration, flexibility, low BOM, small board area, and ease of design. No production alignment is necessary as all RF functions are integrated into the device. Rev. 0.6 11 Si4010 Si4010 CIP-51 CIP-51 8051 CONTROLLER CORE 256 BYTE IRAM 256 BYTE XREG MEMORY CONTROLLER NVM 8 KB RF ANALOG CORE EEPROM 128-bit HVRAM 8 Byte 4K BYTE RAM 12K BYTE ROM OOK ODS DIGITAL PERIPHERALS DIVIDER FSK INTC PA AUTO TUNE TXP LDO POR BANDGAP VDD TXM LCOSC RTC TMR 2,3 AES 128b ACCEL GPIO0/XTAL/VPP GPIO1 GPIO2 GPIO3 GPIO4/C2DAT GPIO5/C2CLK/LED GPIO6 14P SOIC GPIO7 Package Only GPIO8 GPIO9 SFR BUS LPOSC FREQ COUNTER SLP TMR C2 XTAL OSC PORT CONTR TEMP DEMOD TEMP SENSOR Figure 1.1. Si4010 Block Diagram 12 Rev. 0.6 VA VD GND Si4010 2. Test Circuit 2 TEST EQUIPMENT MATCHING NETWORK 3 4 5 GPIO0 GND TXM TXP VDD GPIO1 10 GPIO2 9 U1 GPIO3 8 Si4010-GT Si4010-GT GPIO4 7 LED 6 GP1 GP2 GP3 GP4 VDD 1 GP0 C1 1 uF TESTER INTERFACE GP5 Figure 2.1. Test Block Diagram with 10-Pin MSOP Rev. 0.6 13 Si4010 3. Typical Application Schematic 3.1. Si4010 Used in a 5-Button RKE System with LED Indicator CR2032 CR2032 COIN CELL 1.8 to 3.6 V D1 SW0 1 GPI0 2 GND 3 TXM 4 TXP 5 VDD C2 U1 Si4010-GT Si4010-GT C1 1uF GPIO1 10 GPIO2 9 GPIO3 8 GPIO4 7 LED 6 SW1 SW2 SW3 SW4 LOOP ANTENNA Figure 3.1. Si4010 Used in a 5-button RKE System with LED Indicator 3.2. Si4010 with an External Crystal in a 4-Button RKE System with LED Indicator CR2032 CR2032 COIN CELL 1.8 to 3.6 V D1 C3 X1 1 2 3 4 5 C2 LOOP ANTENNA C1 1uF GPI0 GND TXM TXP VDD GPIO1 GPIO2 U1 GPIO3 Si4010-GT Si4010-GT GPIO4 LED 10 9 8 7 6 SW1 SW2 SW3 SW4 Figure 3.2. Si4010 with an External Crystal in a 4-button RKE System with LED Indicator 14 Rev. 0.6 Si4010 4. Ordering Information HVRAM (Bytes) EEPROM (Bits) 128-bit AES Accelerator GPIO with Wakeup2 LED Driver Sleep Timer +10 dBm RF Transmitter LDO with POR Circuit Integrated Temperature Sensor Low Battery Detector Automotive Qualified Lead-free (RoHS Compliant) 8 128 Y 4 1 Y Y Y Y Y - Y MSOP-10 MSOP-10 Si4010-C2-GS Si4010-C2-GS 24 8k 4k Y 256 8 128 Y 8 1 Y Y Y Y Y - Y SOIC-14 SOIC-14 Si4010-C2-AT Si4010-C2-AT 24 8k 4k Y 256 8 128 Y 4 1 Y Y Y Y Y Y Y MSOP-10 MSOP-10 Si4010-C2-AS Si4010-C2-AS 24 8k 4k Y 256 8 128 Y 8 1 Y Y Y Y Y Y Y SOIC-14 SOIC-14 Package Internal Data RAM (Bytes) 256 RAM (Bytes) Y NVM (OTP) Memory (Bytes) 8k 4k MIPS (Peak) Si4010-C2-GT Si4010-C2-GT 24 Ordering Part Number1 Embedded ROM Functions Table 4.1. Product Selection Guide Notes: 1. Add an "(R)" at the end of the device part number to denote tape and reel option. 2. Assumes LED driver is used and no external crystal. Rev. 0.6 15 Si4010 5. Pin Definitions 5.1. MSOP, Application GPIO0/XTAL 1 10 GPIO1 GND 2 9 GPIO2 TXM 3 Si4010-GT Si4010-GT 8 GPIO3 TXP 4 7 GPIO4 VDD 5 6 LED Pin Number(s) 1 GPIO0/XTAL 2 GND 3, 4 TXM, TXP 5 VDD Power. 6 LED Dedicated LED driver. 7, 8, 9, 10 16 Name Description GPIO[4:1] General purpose input pin. Can be configured as an input pin for a crystal. Ground. Connect to ground plane on PCB. Transmitter differential outputs. General purpose input/output pins. Rev. 0.6 Si4010 5.2. MSOP, Programming/Debug Mode VPP/GPIO0/XTAL 1 10 GPIO1 GND 2 9 GPIO2 TXM 3 Si4010-GT Si4010-GT 8 GPIO3 TXP 4 7 C2DAT/GPIO4 VDD 5 6 C2CLK/LED Pin Number(s) Name Description 1 VPP +6.5 V required for NVM (OTP) Memory programming. 2 GND Ground. Connect to ground plane on PCB. 3 TXM Transmitter differential output. 4 TXP Transmitter differential output. 5 VDD Power. 6 C2CLK C2 clock interface. 7 C2DAT C2 data input/output pin. 8, 9, 10 GPIO[3:1] General purpose input/output pins. Rev. 0.6 17 Si4010 5.3. SOIC Package, Application GPIO9 1 14 GPIO8 GPIO0/XTAL 2 13 GPIO1 GND 3 12 GPIO2 TXM 4 Si4010-GS Si4010-GS 11 GPIO3 TXP 5 10 GPIO4 VDD 6 9 LED GPIO7 7 Pin Number(s) Name 8 GPIO6 Description 1 2 GPIO0/XTAL 3 GND 4,5 TXM, TXP 6 VDD 7,8 GPIO[7:6] 9 LED 10,11,12,13 GPIO[4:1] General purpose input/output pins 14 18 GPIO9 General purpose input/output pin GPIO8 General purpose input/output pin General purpose input pin. Can be configured as an input pin for a crystal Ground. Connect to ground plane on PCB Transmitter differential outputs Power General purpose input/output pins Dedicated LED driver Rev. 0.6 Si4010 5.4. SOIC Package, Programming/debug Mode GPIO9 1 14 GPIO8 VPP/GPIO0/XTAL 2 13 GPIO1 GND 3 12 GPIO2 TXM 4 Si4010-GS Si4010-GS 11 GPIO3 TXP 5 10 C2DAT/GPIO4 VDD 6 9 C2CLK/LED GPIO7 7 Pin Number(s) Name 8 GPIO6 Description 1 GPIO9 General purpose input/output pin 2 VPP +6.5 V required for NVM (OTP) Memory programming 3 GND Ground. Connect to ground plane on PCB 4,5 TXM, TXP 6 VDD 7,8 GPIO[7:6] 9 C2CLK C2 clock interface 10 C2DAT C2 data input/output pin 11,12,13 GPIO[4:1] General purpose input/output pins 14 GPIO8 General purpose input/output pin Transmitter differential outputs Power General purpose input/output pins Rev. 0.6 19 Si4010 6. Package Specifications 6.1. 10-Pin MSOP Figure 6.1 illustrates the package details for the Si4010, 10-pin MSOP package. Table 6.1 lists the values for the dimensions shown in the illustration. Figure 6.1. 10-Pin MSOP Package Table 6.1. Package Dimensions Symbol Millimeters Symbol Min A A1 A2 b c D E E1 Nom Max - 0.00 0.75 0.17 0.08 - - 0.85 - - 3.00 BSC 4.90 BSC 3.00 BSC 1.10 0.15 0.95 0.33 0.23 Millimeters Min e L L2 q aaa bbb ccc ddd 0.40 0° - - - - Nom 0.50 BSC 0.60 0.25 BSC - - - - - Max 0.80 8° 0.20 0.25 0.10 0.08 Notes: 1. All dimensions are shown in millimeters (mm). 2. Dimensioning and tolerancing per ASME Y14.5M-1994 5M-1994. 3. This drawing conforms to JEDEC Outline MO-187 MO-187, Variation "BA." 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 J-STD-020 specification for Small Body Components. 20 Rev. 0.6 Si4010 6.2. 14-pin SOIC Package Figure 6.2 illustrates the package details for the Si4010, 14-pin SOIC package. Table 6.2 lists the values for the dimensions shown in the illustration. Figure 6.2. 14-Pin SOIC Package Table 6.2. Package Dimensions Symbol A A1 b c D E E1 e Min Max Symbol - 1.75 0.10 0.25 0.33 0.51 0.17 0.25 8.65 BSC 6.00 BSC 3.90 BSC 1.27 BSC L L2 Q aaa bbb ccc ddd Min Max 0.40 1.27 0.25 BSC 0° 8° 0.10 0.20 0.10 0.25 Notes: 1. All dimensions are shown in millimeters (mm). 2. Dimensioning and tolerancing per ASME Y14.5M-1994 5M-1994. 3. This drawing conforms to JEDEC Outline MS012 MS012, variation AB." 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 J-STD-020 specification for Small Body Components. Rev. 0.6 21 Si4010 7. PCB Land Pattern 10-Pin MSOP Figure 7.1. 10-Pin MSOP Recommended PCB Land Pattern 22 Rev. 0.6 Si4010 Table 7.1. 10-Pin MSOP Dimensions Dimension MIN MAX C1 4.40 REF E 0.50 BSC G1 3.00 - X1 - 0.30 Y1 Z1 1.40 REF - 5.80 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ASME Y14.5M-1994 5M-1994. 3. This Land Pattern Design is based on the IPC-7351 IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05mm. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD020 J-STD020 specification for Small Body Components. Rev. 0.6 23 Si4010 8. PCB Land Pattern 14-pin SOIC Package Figure 8.1. 14-Pin SOIC Recommended PCB Land Pattern 24 Rev. 0.6 Si4010 Table 8.1. PCB Land Pattern Dimensions Dimension MIN MAX C1 5.30 5.40 E 1.27 BSC X1 0.50 0.60 Y1 1.45 1.55 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based on the IPC-7351 IPC-7351 guidelines. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD020 J-STD020 specification for Small Body Components. Rev. 0.6 25 Si4010 9. Electrical Characteristics Table 9.1. Recommended Operating Conditions Parameter Supply Voltage Symbol Digital Input Range Min - 3.6 V - 650 mV/ us 25 85 °C ­0.3 Digital Input Signals Unit ­40 TA Max 20 Initial Battery Insertion* Typ 1.8 VDD Supply Voltage Slew Rate Ambient Temperature Test Condition - VDD + 0.3 V *Note: Recommend bypass capacitor = 1 µF; slew rate measured 1 V < VDD ,< 1.7 V. Table 9.2. Absolute Maximum Ratings1,2 Parameter Supply Voltage Symbol Value Unit VDD ­0.5 to 3.9 V Current3 IIN 10 mA Input Voltage4 VIN ­0.3 to (VDD + 0.3) V Junction Temperature TOP ­40 to 90 C Storage Temperature TSTG ­55 to 125 C Input Notes: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond recommended operating conditions for extended periods may affect device reliability. 2. Handling and assembly of these devices should only be done at ESD-protected workstations. 3. All input pins besides VDD. 4. For GPIO pins configured as inputs. 26 Rev. 0.6 Si4010 Table 9.3. DC Characteristics (TA = 25° C, VDD = 3.3 V, RL = 550, unless otherwise noted) Parameter Symbol Min Typ Max Unit IVDD +10 dBm output, OOK, Manchester - 14.2 - mA +6.5 dBm output, OOK, Manchester Supply Current Test Condition - 11.3 - mA +10 dBm, FSK - 19.8 - mA +6.5 dBm output, FSK - 14.1 - mA Sleep Timer Mode IST Only sleep timer is enabled - 700 - nA Standby Supply Current ISB All GPIO floating or held high - 10 - nA VOUT > 200 mV - 0.68 - mA 48 55 62 k LED Sink Current ILED GPIO[0-9] Pull Up Resistance RPU High Level Input Voltage1 VIH Trip point at 0.45 x VDD 0.506 x VDD V Low Level Input Voltage1 VIL Trip point at 0.45 x VDD 0.42 x VDD V High Level Input Current1 IIH VIN = VDD - TBD - µA IIL VIN = 0 - TBD - µA VOH ISOURCE = TBD - TBD - V VOL ISINK = TBD - TBD - V 1 Low Level Input Current High Level Output Voltage Low Level Output Voltage 2 2 Notes: 1. For GPIO pins configured as inputs. 2. For GPIO pins configured as outputs. Rev. 0.6 27 Si4010 Table 9.4. Si4010 RF Transmitter Characteristics (TA = 25° C, VDD = 3.3 V, RL = 550, SOIC package unless otherwise noted) Parameter Frequency Range Symbol 1 Frequency Noise (rms) 2 Phase Noise @ 915 MHz Test Condition Min Typ Max Unit 27 - 960 MHz Allen deviation, measured across 1 ms interval - 0.3 - ppm FRF 10 kHz offset - ­70 - dBc/Hz 100 kHz offset - ­100 - dBc/Hz 1 MHz offset - ­105 - dBc/Hz - 5 - ms - 100 - MHz - 315 - MHz - 390 - MHz - 433.92 - MHz - 868 - MHz - 915 - MHz 0°C TA 70° C ­150 - +150 ppm ­40°C TA 85° C ­250 - +250 ppm FRF = 100 MHz 0°C TA 70° C ­15 - 15 kHz FRF = 100 MHz ­40°C TA 85° C ­25 - 25 kHz FRF = 315 MHz 0°C TA 70° C ­47.3 - 47.3 kHz FRF = 315 MHz ­40°C TA 85° C ­78.8 - 78.8 kHz FRF = 433.92 MHz 0°C TA 70° C ­65.1 - 65.1 kHz FRF = 433.92 MHz ­40°C TA 85° C ­108 - 108 kHz FRF = 868 MHz 0°C TA 70° C ­130 - 130 kHz FRF = 868 MHz ­40°C TA 85° C ­217 - 217 kHz FRF = 915 MHz 0°C TA 70° C ­137 - 137 kHz FRF = 915 MHz ­40°C TA 85° C ­229 - 229 kHz Frequency Tuning Time Selected Frequencies in Range of 27­960 MHz Carrier Frequency Accuracy Discrete frequencies Notes: 1. The frequency range is continuous over the specified range. 2. The frequency step size is limited by the frequency noise. 3. Optimum differential load is equal to 4 V/(11.5mA/2 * 4/PI) = 550 Therefore the antenna load resistance in parallel with the Si4010 differential output resistance should equal 50 4. Total NVM copy time = 2 ms + (NVM copy Boot Time per kB) x (NVM data in kB). 28 Rev. 0.6 Si4010 Table 9.4. Si4010 RF Transmitter Characteristics(Continued) (TA = 25° C, VDD = 3.3 V, RL = 550, SOIC package unless otherwise noted) Parameter Typ Max Unit ­10 - +10 ppm Maximum programmed Tx power, with optimum differential load, Vdd > 2.2 V - 10 - dBm - ­13 - dBm Power variation vs temp and supply, with optimum differential load, VDD > 2.2 V ­1.0 - 0.5 dB Power variation vs temp and supply, with optimum differential load, VDD > 1.8 V ­2.5 - 0.5 dB Transmit power step size from ­13 to 10 dBm - 0.25 - dB OOK mode 0.34 - 10.7 us OOK 0.1 - 50 kBaud FSK PA Edge Ramp Rate Programmable Range Data Rate Min Minimum programmed TX power, with optimum differential load, VDD > 2.2 V Frequency Error Contribution with External Crystal Transmit Power3 Symbol Test Condition 0.1 - 100 kBaud Notes: 1. The frequency range is continuous over the specified range. 2. The frequency step size is limited by the frequency noise. 3. Optimum differential load is equal to 4 V/(11.5mA/2 * 4/PI) = 550 Therefore the antenna load resistance in parallel with the Si4010 differential output resistance should equal 50 4. Total NVM copy time = 2 ms + (NVM copy Boot Time per kB) x (NVM data in kB). Rev. 0.6 29 Si4010 Table 9.4. Si4010 RF Transmitter Characteristics(Continued) (TA = 25° C, VDD = 3.3 V, RL = 550, SOIC package unless otherwise noted) Parameter Test Condition Min Typ Max Unit Max frequency deviation - 300 - ppm Deviation resolution FSK Deviation Symbol - 2 - ppm Deviation accuracy TBD ppm Max frequency deviation, 100 MHz - 30 - kHz Deviation resolution, 100 MHz - 200 - Hz Max frequency deviation, 315 MHz - 95 - kHz Deviation resolution, 315 MHz - 630 - Hz Max frequency deviation, 433.92 MHz - 130 - kHz Deviation resolution, 433.92 MHz - 868 - Hz Max frequency deviation, 868 MHz - 260 - kHz Deviation resolution, 868 MHz - 1740 - Hz Max frequency deviation, 915 MHz - 275 - kHz Deviation resolution, 915 MHz - 1830 - Hz 60 - - dB 2.4 - 12.5 pF - 3.6 - ms/ kB OOK Modulation depth Antenna Tuning Capacitive Range (Differential) 315 MHz NVM Copy Boot Time per kB4 Notes: 1. The frequency range is continuous over the specified range. 2. The frequency step size is limited by the frequency noise. 3. Optimum differential load is equal to 4 V/(11.5mA/2 * 4/PI) = 550 Therefore the antenna load resistance in parallel with the Si4010 differential output resistance should equal 50 4. Total NVM copy time = 2 ms + (NVM copy Boot Time per kB) x (NVM data in kB). 30 Rev. 0.6 Si4010 Table 9.5. Low Battery Detector Characteristics (TA = 25° C, VDD = 3.3 V, RL = 550, unless otherwise noted) Parameter Symbol Test Condition Min Typ Max Unit - 2 - % Test Condition Min Typ Max Unit Crystal Frequency Range GPI0 configured as crystal oscillator 10 - 13 MHz Input Capacitance (GPIO0) GPI0 configured as crystal oscillator - 5 - pF Crystal ESR GPI0 configured as crystal oscillator - - 50 Start-up Time Crystal oscillator only, 60 mH motional arm inductance - 9 - ms Battery Voltage Measurement Accuracy Table 9.6. Optional Crystal Oscillator Characteristics (TA = 25° C, VDD = 3.3 V, RL = 600, unless otherwise noted) Parameter Symbol Table 9.7. EEPROM Characteristics Parameter Program Time Conditions Min Typ Max Units Independent of number of bits changing values - 8 40 ms Maximum Count per Counter Using API 1000000 Write Endurance (per bit)* 50000 - cycles - cycles Note: *API uses coding technique to achieve write endurance of 1M cycles per bit. Rev. 0.6 31 Si4010 Table 9.8. Low Power Oscillator Characteristics VDD = 1.8 to 3.6 V; TA = ­40 to +85 °C unless otherwise specified. Use factory-calibrated settings. Parameter Programmable Frequency Range Conditions Frequency Accuracy Typ Max Units .1875 - 24 MHz ­1 Programmable divider in powers of 2 up to 128 Min - +1 % Table 9.9. Sleep Timer Characteristics VDD = 1.8 to 3.6 V; TA = ­40 to +85 °C unless otherwise specified. Use factory-calibrated settings. Parameter Conditions Time Accuracy 32 Using API to program timer Rev. 0.6 Typ Max Units - Maximum Programmable Time Min - 6800 s ­1.5 - 1.5 % Si4010 10. System Description Si4010 CIP-51 CIP-51 8051 CONTROLLER CORE 256 BYTE IRAM 256 BYTE XREG MEMORY CONTROLLER NVM 8 KB RF ANALOG CORE EEPROM 128-bit HVRAM 8 Byte 4K BYTE RAM 12K BYTE ROM OOK ODS DIGITAL PERIPHERALS DIVIDER FSK INTC PA AUTO TUNE TXP LDO POR BANDGAP VDD TXM LCOSC RTC TMR 2,3 AES 128b ACCEL GPIO0/XTAL/VPP GPIO1 GPIO2 GPIO3 GPIO4/C2DAT GPIO5/C2CLK/LED GPIO6 14P SOIC GPIO7 Package Only GPIO8 GPIO9 SFR BUS LPOSC FREQ COUNTER SLP TMR C2 XTAL OSC PORT CONTR TEMP DEMOD TEMP SENSOR VA VD GND Figure 10.1. Functional Block Diagram 10.1. Overview The Si4010 is a fully integrated crystal-less CMOS SoC RF transmitter with an embedded CIP-51 CIP-51 8051 MCU as the core processor of the system. The device is designed for low power battery applications with standby currents of less than 10 nA to optimize battery life. Upon power up, the device immediately enters standby mode. In this mode, all blocks are powered down except for the low leakage high-voltage RAM (HVRAM) which provides 8 bytes of memory that retains its state as long as the battery voltage is applied and above 1.8 V. The Si4010 is awakened from standby mode by a falling edge to ground on any one of the GPIO pins. In addition, the Si4010 has a low-power sleep timer for applications where the device is required to wake up and periodically check for events instead of being wakened by a GPIO falling edge. Upon wake up, the boot loader copies data from the one time programmable (OTP) NVM to CODE/XDATA RAM (4 kB) because the MCU can only operate with programs stored in RAM or ROM. The copy process occurs on each wake-up event and requires approximately 2 ms of fixed time plus 3.6 ms per kB of data or 16.4 ms to fill the full 4 kB of CODE/XDATA RAM. After the NVM boot copy process is completed, the MCU runs the user program in RAM and can also run functions from ROM that are called by the user program such as button service routines to facilitate button debouncing, button time stamps, etc. A complete list of all the API functions is given in Section 10.3 and a detailed description is given in application note "AN370 AN370: Si4010 Software Programming Guide." Rev. 0.6 33 Si4010 The Si4010 has three timing sources. The LCOSC is the most accurate timing source native to the chip. Each device is factory trimmed and programmed at Silicon Labs to produce a frequency accuracy of better than ±150 ppm over the temperature range of 0 to + 70 °C and ±250 ppm over the industrial range of ­40 to +85 °C. The LCOSC is fitted to a multiple-degree polynomial to compensate for temperature variations both from the on-chip power amplifier (PA) and also from the external environment. This LCOSC oscillates around 3.9 GHz and provides the clock (via the DIVIDER) used to modulate the PA for OOK and FSK transmission. The low power oscillator (LPOSC) is the second timing source and operates at 24 MHz. The LPOSC is always the source of clocking for the MCU and is turned off only in standby mode. The system clock is programmable allowing the MCU to operate with lower clock frequencies while waiting between packets to save power. The RTC and timers 2 and 3 are derived from the LPOSC. The last clock source is the crystal oscillator (XTALOSC). This crystal oscillator is unused in many customer applications and used only when a highly accurate carrier frequency is desired. When enabled, it is used before the beginning of a transmission to correct the frequency of the LCOSC and is then shutdown to save power. An internal frequency counter is implemented in hardware to allow for quick frequency ratio measurements to calibrate the different clock sources. The high efficiency PA is a CMOS open drain output driver capable of producing 4 Vpk differential output swing with a supply voltage of 2.2 V or higher. The PA output has 2.4 to 12.5 pF of differential variable capacitance that is automatically adjusted to resonate the antenna at the start of each packet transmission. This automatic adjustment is realized with a firmware algorithm in the ROM and some additional hardware in the PA. Maximum power can be transferred to the inductive antenna load when the antenna and output driver are at resonance and the real component of the load is equal to the optimum load resistance of Vpk/(4/Pi * Itail/2) where Vpk is the peak differential voltage and Itail is the tail current of the PA. At higher resistances the PA is voltage limited and at lower resistances the PA is current limited. The PA tail current is programmable from 810 uA up to 7.67 mA in 0.25 dB steps and there is a boost current bit that multiplies the tail current by 1.5 times allowing it to go up to 11.5 mA. With an antenna load resistance of about 550 an output power of +10 dBm is achievable. Edge rate control is also included for OOK mode to reduce harmonics that may otherwise violate government regulations. The on-chip temperature sensor (TEMP SENSOR) measures the internal temperature of the chip and temperature demodulator (TEMP DEMOD) converts the TEMP SENSORs' output into a binary number representing temperature and is used to compensate the frequency of the LCOSC when the temperature changes. Each device is frequency and temperature calibrated in the factory. The output data serializer (ODS) is responsible for synchronizing the output data to the required data rate and maintaining a steady data flow when data is available. This block produces the edge rate control for the PA in OOK mode and the frequency deviation in FSK mode. The block also schedules the power on/off times of the LCOSC, DIVIDER, and PA to conserve battery power during transmission. Power management is provided on chip with low-drop-out (LDO) regulators for the internal analog and digital supplies, VA and VD, respectively. The power-on reset (POR) circuit monitors the power applied to the chip and generates a reset signal to set the chip into a known state. The bandgap produces voltage and current references for the analog blocks in the chip and can be shut down when the analog blocks are not used. The embedded CIP-51 CIP-51 8051 MCU provides the core functionality of the Si4010. User software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings. 8K bytes of on-chip one-time programmable NVM memory is available to store the user program and can also store unique transmit IDs. 128 bits of EEPROM is available for counter or other operations providing nonvolatile storage capability in case of power outages due to battery removal. A library of useful software functions such as AES encryption, a patented 32-bit counter providing 1M cycles of read/write endurance, and many other functions are included in the 12 kB of ROM to reduce user design time and code space. General purpose input/output pins with push button wake-on touch capability are available to further reduce current consumption. 34 Rev. 0.6 Si4010 The Si4010 includes Silicon Laboratories' 2-wire C2 Debug and Programming interface. This debug logic supports inspection memory, viewing and modification of special function registers (SFR), setting break points, single stepping, and run and halt commands. All analog and digital peripherals are fully functional while debugging using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins. 10.2. Setting Basic Si4010 Transmit Parameters The basic transmit parameters such as output power, modulation type, data rate, and operating frequency are set by using applications programming interface (API) function commands. When using these functions certain parameters are determined by using a calculator spread sheet. The Si4010 development kit (part number 4010-DKKF 4010-DKKF 434) includes a calculator spread sheet that helps developers set the API function arguments to meet their desired design requirements. A summary of the calculator operations are given below and more detailed descriptions are given in the individual sections of this data sheet and in AN370 AN370: Si4010 Software Programming Guide. 10.2.1. Package Type The Si4010 has two package type options: 10-pin MSOP or 14-pin SOIC. The customer should choose the package type they are using to properly model the Si4010 RF behavior. 10.2.2. Output Power The output power of the Si4010 depends on many parameters including the antenna impedance, the output impedance of the PA, the nominal varactor setting, the battery supply voltage, and the bias current of the PA. The calculator spreadsheet can calculate the required antenna impedance needed to achieve the desired output power or it can estimate the output power given the antenna impedance. It has the following input parameters: Power Setup: Power Target (dBm): This is the desired output power in dBm. The spreadsheet will always try and hit this target. Choose One of the Following: Maximize Radiated Power or Minimize PA current while Maximizing Radiated Power. If only radiated power is to be maximized, the PA current is maximized and an antenna impedance is found that maximizes the possible radiated power. Usually, this tends to minimize the antenna impedance relative to the chip impedance. If the PA current is to be minimized while still maximizing radiated power, the solution tends to equalize the antenna and on-chip impedances. This increases the effective impedance of the system, which saves PA current at the expense of radiation efficiency (as more power will now be consumed on-chip). Frequency (MHz): The RF frequency of operation, range is 27 to 960 MHz. Nominal Cap Word: This is the nominal setting of the power amplifier varactor that is part of the antenna tuning circuit, range is 0 to 511. External Diff Cap (pF): This is an external capacitor placed across the TXP and TXM pins. Assuming this has a much larger quality factor than the on-chip varactor, there may be antenna efficiency advantages of using this external component. Q-Factor External Cap: This is the quality factor of the external capacitor. Typical values would be 250300. Antenna Setup: Alpha (bLevel/deg C): The sensitivity of the antenna resistance vs temperature change. If constant radiated power vs temperature is desired, this constant may be used to compensate the PA drive strength. See the API section on power control. Approx Efficiency (%): The approximate antenna efficiency used to estimate radiated power. Rev. 0.6 35 Si4010 Manual Impedance Entry: Determines if the antenna impedance is calculated to meet a desired output power or if the antenna impedance is entered and the spread sheet calculates the resulting impedance. The current drive is adjusted to meet the power target (if possible). Antenna Real(Z) (Ohms): The antenna resistance at the operating frequency. Antenna Imag(Z) (Ohms): The antenna reactance at the operating frequency. These parameters are discussed in more detail in the Power Amplifier section of the data sheet. Based on these input parameters the calculator will provide the following outputs: PA Design Values: Iout Target (mA): Theoretical output current that meets the power target. Attenuation Factor: Theoretical attenuation factor due to losses from the chip Actual Iout (mA): The actual output current delivered to the antenna that accounts for quantization effects and chip losses. Rdif at PA (Ohms): Theoretical optimum differential load resistance that includes chip, antenna, and external capacitance loading. Total Power (dBm): The estimated output power based on all loss mechanisms. Max Diff Vpk at PA (V): The calculated peak differential voltage swing. Antenna Targets: Real_Z (Ohms): The required resistance of the antenna at the frequency of operation to meet the desired output power. Imag_Z (Ohms): The required reactance of the antenna at the frequency of operation to meet the desired output power. Power dissipated in Antenna (dBm): The expected power delivered to the antenna. Expected Radiated Power (dBm): The expected radiated power of the device given the antenna efficiency Chip Impedance: Total Diff Cap due to Chip + External Load (pF): The equivalent differential capacitance seen looking into the package pins. It includes the on-chip varactor, the package and external differential capacitor (if used). Real_Z (Ohms): The resistance of the chip at the frequency of operation to meet the desired output power Imag_Z (Ohms): The reactance of the chip at the frequency of operation to meet the desired output power API: PA Setup: 36 bMaxDrv-value for this API parameter bLevel-value for this API parameter wCap-value for this API parameter fAlpha-value for this API parameter fBeta-value for this API parameter. The sensitivity of the antenna resistance vs capacitance change. If constant radiated power vs tuning capacitance change is desired this constant may be used to compensate the PA drive strength. See the API section on power control. The algorithm attempts to keep the PA output voltage multiplied by the PA capacitance constant due to fluctuations in the external component values of the loop antenna. Rev. 0.6 Si4010 10.2.3. Modulation, Encoding, and Data Rate The output data serializer (ODS) API function commands set the modulation type, encoding method, and data rate of the transmitter. The calculator has the following inputs: Serializer Setup: Bit (or Data) Rate (Kbits/s): This is the bit or data rate of the transmitter Encoding: The encoding methods supported are Manchester, NRZ+4b/5b, and NRZ encoding. Modulation: OOK or FSK. FSK Deviation (kHz): This is the FSK frequency deviation of the carrier frequency in response to a data signal. Manual Ramp Rate Entry: If Yes, used to set the ramp rate for turning on and off the PA, otherwise the ramp rate will be automatically calculated Target Ramp Rate (us): This parameter is the target ramp rate. Only used if the Manual Ramp Rate Entry is Yes The outputs of the calculator are the following: Serializer Control: Ramp Time (µs): The actual ramp time of turning on and off the PA. If Manual Rate Entry is Yes, this will represent the closest possible match to the user entry. If Manual Rate Entry is No, this is automatically calculated based on the target bit rate. The chosen rate insures the resulting spectrum will be FCC/ETSI compliant. Actual Symbol Rate (Ksym/s): The actual symbol rate produced by the chip after taking into account encoding and quantization effects due to the timers. Ramp Time/Symbol Rate: The ratio of the ramp time divided by the symbol rate. API: ODS Setup: bModulation Type-value for this API parameter bClkDiv-value for this API parameter bEdgeRate-value for this API parameter bGroupWidth-value for this API parameter wBitRate-value for this API parameter bDivWarmInt, bLcWarmInt, and bPaWarmInt-value for this API parameter API: FSK Controls: biFskDev-value for this API parameter Expected FSK Deviation (kHz): The expected FSK deviation with quantization error 10.2.4. Output Frequency The output frequency does not require the use of the calculator and is set by using the following API commands: vFCast_Setup() vFCast_Tune(desired frequency) Rev. 0.6 37 Si4010 10.2.5. Battery Life Calculation The calculator also estimates battery life of a system given the packet setup and number of button pushes per day. The inputs to the calculator are all of the above inputs plus the following: Packet Setup: Number of bits in Packet-Number of bits in the packet excluding the preamble bits Preamble bits-Number of bits in the preamble Time Prior to Transmit (ms)-The time required to boot the chip and send a packet out Number of Packets-The number of packets sent out per button press Time Between Packets (ms)-The time between repeating packets Button Pushes/Day-The number of button pushes per day The outputs of the calculator are the following: Battery Life: Avg Transmit Current (mA)-The average transmit current Peak Transmit Current (mA)-The peak transmit current Charge/Year (mAH)-The charge per year in mAH 220 mAH Battery Life (Years)-The estimated battery life of a 220 mAH battery 38 Rev. 0.6 Si4010 10.3. Applications Programming Interface (API) Commands The following is a list of API commands for the Si4010. For detailed descriptions of the API commands see the application note AN370 AN370: Si4010 Software Programming Guide. AES Module Functions: vAes_Cipher vAes_InvGenKey vAes_InvCipher Button Service Module Functions: vBsr_Setup wBsr_Pop wBsr_GetCurrentButton vBsr_InitPts bBsr_GetPtsItemCnt vBsr_Service bBsr_GetTimestamp Demodulator Temperature Sensor Module Functions: vDmdTs_Setup iDmdTs_GetData iDmdTs_GetLatestDmdSample iDmdTs_GetLatestTemp vDmdTs_ClearDmd vDmdTs_ClearDmdIntFlag vDmdTs_IsrCall bDmdTs_GetSamplesTaken vDmdTs_Enable vDmdTs_RunForTemp vDmdTs_ResetCounts Encoding Module Functions: vEnc_4b5bEncode vEnc_Set4b5bLastBit bEnc_ManchesterEncode Frequency Counter Module Functions: vFc_Setup vFc_StartCount vFc_PollDone lFc_GetCount lFc_StartPollGetCount Rev. 0.6 39 Si4010 Frequency Casting Module Functions: vFCast_Setup vFCast_XoSetup vFCast_Tune vFCast_FineTune vFCast_FskAdj HVRAM Module Functions: vHvram_Write bHvram_Read Multi-Time Programmable Module Functions: lMtp_GetDecCount vMtp_IncCount vMtp_SetDecCount bMtp_Write vMtp_Strobe pbMtp_Read Battery Measurement Module Functions: iMVdd_Measure Non-Volatile Memory Copy Module Functions: vNvm_SetAddr wNvm_GetAddr bNvm_CopyBlock vNvm_McEnableRead vNvm_McDisableRead Output Data Serializer Module Functions: vOds_Setup vOds_Enable vOds_WriteData Power Amplifier Module Functions: vPa_Setup vPa_Tune Single Transmission Loop Module Functions: vStl_EncodeSetup vStl_EncodeByte vStl_PreLoop vStl_SingleTxLoop vStl_PostLoop 40 Rev. 0.6 Si4010 System Module Functions: vSys_Setup vSys_BandGapLdo vSys_ForceLc wSys_GetRomId wSys_GetChipId bSys_GetRevId lSys_GetProdId wSys_GetKeilVer vSys_SetClkSys lSys_GetMasterTime vSys_IncMasterTime vSys_SetMasterTime vSys_LedIntensity vSys_LpOscAdj vSys_Shutdown bSys_GetBootStatus vSys_FirstPowerUp vSys_16BitDecLoop vSys_8BitDecLoop Sleep Timer Module Functions: lSleepTim_GetCount vSleepTim_SetCount bSleepTim_CheckDutyCycle vSleepTim_AddTxTimeToCounter lSleepTim_GetOneHourValue Rev. 0.6 41 Si4010 11. Power Amplifier TXP INPUT PA TXM Itail FEEDBACK (HW, SW) FREQUENCY TUNE, CONST PWR Figure 11.1. Simplified PA Block Diagram The CMOS power amplifier (PA) is a differential open drain amplifier capable of delivering +10 dBm of output power. Maximum power can be transferred to an inductive antenna load when the antenna and output driver of the PA are at resonance and the real component of the combined load is equal to the optimum load resistance of Vpk/(4/Pi x Itail/2) where Vpk is the peak differential voltage of the PA and Itail is the tail current of the PA. This optimum load resistance is the parallel combination of the PA output resistance and the differential antenna resistance. At higher resistances the PA is voltage limited and at lower resistances the PA is current limited. The PA tail current is programmable from 810 µA up to 7.67 mA (SFR register PA_LVL) in 0.25 dB steps and there is a boost current bit (XREG PA_TRIM.PA_MAX_DRV) that multiplies the tail current by 1.5 times allowing it to go up to 11.5mA. The maximum differential peak-to-peak voltage is 4 V when the supply is 2.2 to 3.6 V and drops linearly down to 3.4V when the supply is at 1.8V The calculator spreadsheet tool computes the required antenna impedance and API settings to achieve the user desired output power. Proper layout and matching techniques are all necessary to ensure optimal performance. Figure 9.1 shows a typical application schematic of the Si4010 for a differential loop antenna. Application note "AN369 AN369: Antenna Interface for the Si401x Transmitters" provides detailed information about designing the antenna interface for the Si401X transmitters. With proper filtering and layout techniques, the Si4010 can conform to US FCC part 15.231 and European EN 300 220 regulations. Edge rate control is also included for OOK mode to reduce harmonics that may otherwise violate government regulations. Edge shaping is accomplished by gradually turning on and off the driver transistors of the PA. The edge shaping parameters are controlled by the ODS block and is automatically determined by the calculator spread sheet based on the desired data rate and encoding method. Users must comply with local radio frequency transmission regulations. Off-chip capacitor tolerances, loop antenna manufacturing tolerances, and environmental variations can lead to impedance mismatch at the PA output causing reduced radiated power level. The Si4010 includes an automatic antenna tuning circuit to reduce the mismatch by adjusting the on-chip variable capacitor to resonate with the inductance of the antenna. The PA output has 2.4 to 12.5 pF of variable capacitance that is adjusted to tune the antenna to the correct frequency using a firmware assisted algorithm and on-chip hardware.The variable capacitance is adjusted at the start of each packet transmission during the preamble. The switching network in the capacitor array is compensated over process, voltage, and temperature 42 Rev. 0.6 Si4010 (PVT) to keep its quality factor (Q) nearly constant at 50 (at 434 MHz). The starting value of the 9-bit capacitor word (XREG PA_CAP) is chosen with the help of the calculator spreadsheet. In general, a high operating frequency requires a smaller capacitance and hence a low value capacitive word. The output resistance of the PA is a strong function of the capacitive word because the variable capacitor is implemented with a capacitor and a MOS switch. When more capacitance is turned on (higher capacitive word), more switches turn on and with a constant Q design, the output resistance of the PA decreases and has more loss. Thus another consideration for the nominal capacitive word besides the operating frequency is how the resistive loading of the varactor affects the optimum load resistance and the required antenna resistance. The calculator illustrates how the nominal value of the capacitive word affects the desired antenna resistance. In addition to the algorithm used to tune the antenna for resonance, a software control loop using the Power Amplifier Module API can keep the transmit radiated power constant due to changes in temperature and/or capacitance of the antenna. For example, if changes in the temperature of the transmitter and/or the capacitance of the antenna cause the impedance of the load (the parallel combination of the PA and antenna resistances) to decrease, this will cause a decrease in the output voltage of the PA and hence the radiated power. Both the operating temperature and the capacitor tuning word are monitored by the chip and may be used to increase the nominal drive current to bring the product of the output voltage and driver capacitance back to what it was prior to the environmental change. In order for this loop to operate correctly, the parameters Alpha and Beta need to be determined from measured antenna characteristics. Alpha represents the required change in bLevel (the nominal power level programmed through the API interface) given changes in temperature. Beta represents the required change in bLevel given changes in programmed driver capacitance. Remember that each LSB change in bLevel corresponds to a 0.25 dBm change in power. For example, if experimental measurement shows that the radiated power changes by 1 dBm over a 50 °C change in temperature, alpha would be set to 4/50=0.08. In this alpha equation, the 4 is derived from 1 dBm/0.25 dBm per step in bLevel. Thus, the units of alpha are (LSB steps in bLevel)/(change in temp). Beta can be measured by forcing the external antenna capacitance to change by some small amount and measuring the corresponding change in tuning capacitance and radiated power. For example, if the antenna capacitor is changed by 5%, it is seen that the resulting capacitor word changed by 30 LSBs and the power decreased by 2dBm. In this case, Beta would be calculated as 8/30=0.27 and has the units of (LSB steps in bLevel)/(LSB steps in capacitor word). These two parameters can be measured and entered as parameters to the API to provide accurate adjustments to the radiated power. In addition to these parameters, the differential peak voltage and current drive of the PA should not be maximized prior to using this loop so adjustments in the current drive, which affects the differential peak voltage, can be made by the feedback loop. If either the current or voltage is maximized prior to using the loop, the loop would not be able to further adjust the current or voltage and hence fail to operate properly. Rev. 0.6 43 Si4010 11.1. Register Description SFR Definition 11.1. PA_LVL Bit 7 6 5 4 3 2 1 0 Name PA_LVL_NSLICE[4:0] PA_LVL_BIAS[2:0] Type R/W R/W Reset 0 0 SFR Address = 0xCE Bit Name Function 7:3 PA_LVL_ NSLICE [4:0] Number of Slices Enabled in the PA Driver. +-This parameter determines the output current drive of the PA. The values entered into this register come from the Power Amplifier Module API. 2:0 PA_LVL_ BIAS [2:0] PA Level Bias. This parameter determines the bias current per slice of the PA. The values entered into this register come from the Power Amplifier Module API. XREG Definition 11.2. wPA_CAP Bit 8 7 6 5 4 3 0 0 0 0 PA_CAP[8:0] Type 1 0 Name 2 R/W Reset 0 0 0 0 0 XREG Address = 0x400C Bit Name Function PA Variable Capacitance. 8:0 44 PA_CAP [8:0] Linear control of the output capacitance of the PA. Range: 2.4­-12.5 pF (not exact values). The resonance frequency and impedance matching between the PA output and the connected antenna can be tuned by changing this value. This register is set by the Power Amplifier Module API. Rev. 0.6 Si4010 XREG Definition 11.3. bPA_TRIM Bit 7 6 5 4 3 2 1 0 Name PA_MAX_ DRV Reserved Reserved Reserved Reserved Type R/W Reset 0 XREG Address = 0x4012 Bit Name Function 7:5 Unused 4 PA_MAX_ DRV This parameter boost the bias current of the PA by 1.5 times up to 10.5 mA. The values entered into this register come from the Power Amplifier Module API. This bit should be set without changing the other bits. 3:0 Reserved Reserved. PA MAX Drive Bit. Rev. 0.6 45 Si4010 12. Output Data Serializer (ODS) 12.1. Description The ODS block is responsible for synchronizing the output data to the required data rate and maintaining a steady data flow during transmission. The serializer accomplishes the following functions: Controls the edge rate of the PA on/off transitions. Schedules PA, DIVIDER, LCOSC on/off power transitions for minimal power consumption. Controls the serial data rate. Provides handshake interface and a 1 byte pipeline to allow a software process to maintain steady dataflow. Modulates a 7 bit "frequency deviation" bus to the LC oscillator to allow for FSK operation. Provides test features to force on the power state of the LCOSC, DIVIDER, and PA; recirculating a fixed pattern; forcing the FSK offset frequency. The SFR and XREG settings of this block are determined from the desired modulation, data rate, and encoding method and are automatically set by the ODS API in conjunction with the calculator. Users are recommended to use the ODS API module functions for setting these registers. 12.2. Timing P A _ L V L _ N S L IC E [4 :0 ] S Y M B O L T IM E LC _EN A LC _W AR M U P D IV _ E N A D IV _ W A R M U P PA_EN A PA_W AR M U P E D G E T IM E Figure 12.1. OOK Timing Example P A _ L V L _ N S L IC E [4 :0 ] LC _EN A D IV _ E N A PA_ENA F S K _ S H IF T [6 :0 ] ( 46 CO f f Figure 12.2. FSK Timing Example Rev. 0.6 f O S) Si4010 12.3. Register Description SFR Definition 12.1. ODS_CTRL Bit 7 Name 6 ODS_SHIFT_CTRL [1:0] 5 4 3 2 1 0 FSK_FOR CE_DEV FSK_ MODE FORCE_ LC FORCE_ DIV FORCE_ PA ODS_EN Type R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 SFR Address = 0xA9 Bit Name Function ODS Output Control on Last Bit. 7:6 ODS_ SHIFT_ CTRL[1:0] 5 FSK_ FORCE_ DEV Controls behavior of serializer when data runs out. 00: The PA, DIVIDER, and LCOSC shutdown after last bit. 01: Reuse the last symbol group for transmission. 10: All 0s data. 11: All 1s data. Force FSK Deviation. 0: Normal operation. 1: Force the LCOSC to frequency deviate regardless of data pattern or FSK_MODE. Selects Modulation Mode. 4 3 FSK_MODE 0: OOK mode. 1: FSK mode. Force LCOSC On. FORCE_LC .0: Normal operation. 1: Force LSCOSC on. Force DIVIDER On. 2 FORC_DIV .0: Normal operation. 1: Force DIVIDER on. Force PA On. 1 FORCE_PA .0: Normal operation. 1: Force PA on. In addition, PA_LVL_NSLICE[4:0] in PA_LVL register is passed directly through the serializer, unchanged. Enable the Serializer. 0 ODS_EN 0: Disable the ODS. 1: Enable the ODS. Rev. 0.6 47 Si4010 SFR Definition 12.2. ODS_TIMING Bit 7 6 5 4 3 2 ODS_EDGE_TIME [1:0] 1 0 Name ODS_GROUP_WIDTH[2:0] ODS_CK_DIV[2:0] Type R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 SFR Address = 0xAA Bit Name Function Controls Symbol Group width, from 2­8 Symbols. 7:5 4:3 Set to 4 to transmit 5 symbol groups obtained from 4/5 encoding. Or set to 7 to send ODS_ GROUP_ 8 symbol group obtained from Manchester encoding of 4 bits. Note that ods_group_width can be changed dynamically prior to writing the ODS_DATA regisWIDTH[2:0] ter, should you want to (for example) add 2 more symbols to the end of a transmission which was previously using 8 symbol groups. ODS_ EDGE_ TIME [1:0] Controls PA Edge Time. Additional division factor in range 1-4 (ods_edge time+1). PA controlled edge rates are: 8*(ods_ck_div+1)*(ods_edge_time+1)/25 MHz. When clk_ods is in range of 38 MHz, edge rate can be selected from 1us to 10.7us. Study has indicated that in the worst case (20Kbps Manchester), edge rates somewhat higher than 4us are needed. Controls the Clock of the ODS. 2:0 48 ODS_CK_ DIV[2:0] Sets the division factor of the 24 MHz system clock to produce clk for the ODS module. Division factors are 1­8 (ods_ck_div+1). Generally should select factor which produces serializer clock in range of ~ 3-8 MHz Rev. 0.6 Si4010 SFR Definition 12.3. ODS_DATA Bit 7 6 5 4 3 Name 1 0 0 0 0 ODS_DATA[7:0] Type 2 R/W Reset 0 0 0 0 0 SFR Address = 0xAB Bit Name Function ODS Input Data. 7:0 Symbol group register. Side effect of writing is clearing of ODS_EMPTY flag. It generODS_DATA ates a single pulse for the ODS to notify the Tx ODS data SFR holding register been [7:0] written to and contains new data. The pulse is a registered write pulse, so it will be generated when the data is stable in the holding register. ODS data format is little endian. SFR Definition 12.4. ODS_RATEL Bit 7 6 5 4 3 2 1 0 ODS_RATEL[7:0] Name Type R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 SFR Address = 0xAC Bit Name 7:0 ODS_RATEL [7:0] Function Lower Byte of the 15-bit Wide ODS Data Rate Field. Symbol rate produced by the serializer is 24MHz/(ods_datarate*(ods_ck_div+1) Rev. 0.6 49 Si4010 SFR Definition 12.5. ODS_RATEH Bit 7 6 5 4 Name Reserved Type R R/W R/W R/W Reset 0 0 0 3 0 2 1 0 R/W R/W R/W R/W 0 0 0 0 1 0 ODS_RATEH[6:0] SFR Address = 0xAD Bit Name 7 Reserved ODS_ RATEH [6:0] 6:0 Function Read as 0. Write has no effect. Upper Bits of 15-bit ODS Data Rate Field. See the ODS_RATEL for description of the serializer data rates. SFR Definition 12.6. ODS_WARM1 Bit 7 6 5 4 3 ODS_WARM_DIV[3:0] Name 2 ODS_WARM_PA[3:0] Type R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 SFR Address = 0xAE Bit Name Function Sets Warm-Up Time for DIVIDER. 7:4 ODS_ WARM_ DIV[3:0] Sets the "warm up" interval for the DIVIDER, where it is biased up prior to transmission or on the transition from OOK Zero bit to OOK One bit. Interval is in 4 * clk_ods cycles resolution Interval = 4*ods_warm_pa*(ods_ck_div+1)/24 MHz When clk_ods is in range of 3-8 MHz, warm-up interval range is from 7.6 to 20 µs. Sets Warm-Up Time for PA. 3:0 50 ODS_ WARM_ PA[3:0] Sets the "warm up" interval for the PA, where it is biased up prior to transmission or on the transition from OOK Zero bit to OOK One bit. Interval is directly in clk_ods cycles. Interval = ods_warm_pa x (ods_ck_div+1)/24 MHz When clk_ods is in range of 3­8 MHz, warm-up interval range is from 1.9 to 5 µs. Rev. 0.6 Si4010 SFR Definition 12.7. ODS_WARM2 Bit 7 6 5 4 3 2 1 Name Reserved ODS_WARM_LC[3:0] Type R 0 R/W Reset 0 0 0 0 0 0 0 0 SFR Address = 0xAF Bit Name 7:4 Reserved Function Read as 0x0. Write has no effect. Sets Warm-Up Time for the LCOSC. 3:0 ODS_ WARM_ LC[3:0] Sets the "warm up" interval for the LC oscillator, where it is biased up prior to transmission or on the transition from OOK. Zero bit to OOK One bit. Interval is in 64*clk_ods cycles resolution Interval = 64 x ods_warm_pa x (ods_ck_div+1)/24 MHz When clk_ods is in range of 3-8 MHz, warm-up interval range is from 30 to 80 µs. Rev. 0.6 51 Si4010 13. LC Oscillator (LCOSC) The Si4010 VCO is a fully integrated CMOS LC oscillator that operates at approximately 3.9 GHz. This block in conjunction with a programmable frequency divider generates the transmit carrier frequency. The technology behind the VCO is based on the Silicon Laboratories Si500 crystal-less oscillator chip and forms the core of the Si4010s Si4010s' crystal-less operation. After this device is factory trimmed, the VCO frequency is the most accurate frequency on the chip and sets the chips transmit frequency stability unless an external crystal oscillator is used. The device achieves ±150 ppm frequency stability over the commercial temperature range of 0 to 70°C and ±250 ppm frequency stability over the industrial temperature range of ­40 to 85 °C. The transmit carrier frequency is set by using the API functions vFCast_Tune (desired carrier) and vFCast_Setup(). For FSK modulation, the frequency deviation is also a parameter to the freq_adjustment function. Users are recommended to use the API functions to set the corresponding SFR registers. 13.1. Register Description SFR Definition 13.1. LC_FSK Bit 7 6 Name Reserved FSK_DEVIATION[6:0] Type R/W R/W Reset 0 0 5 0 4 3 0 0 2 1 0 0 0 0 SFR Address = 0xE4 Bit Name 7 Reserved Function Do not write to this bit. FSK Deviation. FSK_ 6:0 DEVIATION These bits determine the FSK deviation. The values of these bits are calculated and [6:0] entered from the API vFCast_FskAdj. 52 Rev. 0.6 Si4010 14. Low Power Oscillator and System Clock Generator The source of all digital system clocks is derived from the low power oscillator (LPOSC) and system clock generator. The LPOSC produces a 24 MHz clock signal and is used by the system clock generator to produce the system clock. This system clock is applied to all digital blocks including the MCU and is programmable via the SYSGEN SFR register which is useful for power savings. Users are recommended to use the System Module Function API to set the registers. 14.1. Register Description XREG Definition 14.1. bLPOSC_TRIM Bit 7 6 5 4 3 Name 1 0 1 1 1 LPOSC_TRIM[7:0] Type 2 R/W Reset 1 1 1 1 1 XREG Address = 0x4002 Bit Name 7:0 LPOSC_ TRIM[7:0] Function Low Power Oscillator Trimming. ±16% range with 0.14 % resolution. Setting all the bits to low will maximize the frequency of operation. Rev. 0.6 53 Si4010 SFR Definition 14.2. SYSGEN Bit 7 6 5 4 RTC_ Name SYSGEN_ Re-served PWR_1ST SHUT_TIME TICKCLR DOWN 3 2 1 PORT_ HOLD 0 SYSGEN_DIV[2:0] R/W Type R/W R R W R/W Reset 0 0 - 0 0 0 0 0 SFR Address = 0xBE Bit Name Function System General Shutdown. 7 6 5 4 SYSGEN_ SHUTDOWN Reserved Setting this bit causes shutdown of MCU and most analog. Recovery from this is via falling edge on any GPIO, which results in a power up and a power on reset. This is THE bit that shuts down the power to nearly everything. 0: Normal operation 1: Shutdown. Do not use this bit directly. It is recommended to use the vSys_Shutdown() API call. Read as 0. Write has no effect. PWR_1ST_ Initial Powerup Indicator. TIME Read only register. It will get set when power up was caused by a battery insertion. RTC_ TICKCLR Real Time Clock Clear. 0: Normal operation 1: Clears the real time clock 5.12us counter. Port Hold. 3 PORT_ HOLD This bit needs to be set before shutting down, it delays any button pushes that occur between this bit setting and shutdown until the chip completes shutdown, to ensure the shutdown process cannot be interrupted. 0: Normal operation 1: Holds GPIO port values until shutdown is complete System Clock Generator Divider. 2:0 54 SYSGEN_ DIV[2:0] System clock divider control to generate the system clock. 000: 24 MHz; div = 1 001: 12 MHz; div = 2 010: 6.0 MHz; div = 4 011: 3.0 MHz; div = 8 100: 1.5 MHz; div = 16 101: 0.75 MHz; div = 32 110: 0.375 MHz; div = 64 111: 0.1875 MHz; div = 128 Rev. 0.6 Si4010 15. Crystal Oscillator (XO) The crystal oscillator produces an accurate clock reference for applications demanding a high-accuracy transmit carrier frequency. It uses a 1-pin crystal oscillator circuit (Colpitt's oscillator) and the output is connected to the frequency counter. 15.1. Register Description XREG Definition 15.1. bXO_CTRL Bit 7 6 5 4 Name Reserved Reserved Reserved Reserved 3 1 0 XO_TST[1:0] XO_LOW CAP XO_ENA R/W R/W R/W 0 0 Type Reset 0 0 0 0 2 0 0 XREG Address = 0x4016 Bit Name 7:4 Reserved Function Reserved. Measurement of the XO Regenerative Amplifier Bias Current. 3:2 XO_ TST[1:0] 0: No connection 1: Sense 2: Force 3: Sense and force XO Low Capacitance. 1 XO_ LOWCAP Bit should be set for crystals that require less than 14 pF of total capacitance. 0: Crystals with 14 pF or more of total capacitance. 1: Crystals with less than 14 pF of total capacitance. Enable XO. 0 XO_ENA Note that operation of the XO requires that the bandgap be enabled with the System Module Function API. The input XO_CKGOOD status bit is in the SFR SYSTEM register. 0: Crystal oscillator disabled. 1: Crystal oscillator enabled. Rev. 0.6 55 Si4010 16. Frequency Counter The frequency counter allows the measurement of the ratio of two selected clock sources: a low frequency clock which defines a counting interval, and a high frequency clock which is counted. The frequency counter consists of an interval counter, driven by one of the six clock sources. Programming of the interval counter determines how long the main counter will count one of the two high speed clocks, LC oscillator or DIVIDER output. FC_MODE FC_DIV_SEL FC_BUSY FC_DONE FC_CTRL New count trigger 0 1 Long word 4 byte result count read from XREG FC_COUNT (LWORD lFcCount) 3 Freq counter disabled GPIO[3] GPIO[0] Port Controller Xtal Oscillator clk_ref 0 1 clk_osc (24MHz) 2 clk_sys 3 clk_xo clk_int 4 RESERVED 5 SLEEP TIMER 5 FC_INTERVAL 7 FC_DONE Interval Counter Interrupt FC_BUSY FC_CTRL LC_OSC DIVIDER RESERVED FC_DIV_SEL FC_MODE Figure 16.1. Frequency Counter Block Diagram The block diagram of the frequency counter is in Figure 16.1. When the FC_MODE=0, the frequency counter is disabled. The only way to disable the frequency counter is to set the FC_MODE=0. The frequency counter stops counting immediately, so it can be restarted by setting FC_MODE to some functional mode immediately. If the frequency counter is enabled by setting FC_MODE to other than the 0 value, it enters the idle state. To start the counter, the interval counter has to be triggered by writing 1 to the FC_BUSY bit. By writing FC_BUSY=1, the FC_DONE bit gets cleared as well. The user can also clear the FC_DONE bit in software after reading the main FC_COUNT value. Once the interval counter is triggered, and after several clk_sys cycles synchronization delay it waits for the first rising edge of the clk_int clock, which is the output of the interval counter clock selector mux. It then enables the main frequency counter FC_COUNT clock. After the interval counter counts the interval specified by FC_INTERVAL SFR register, another rising edge of the clk_int stops the clocks to the main FC_COUNT counter. The interval counter edge to edge counting and main FC_COUNT clock enable is measured very accurately in between the clk_int rising edges. 56 Rev. 0.6 Si4010 When the interval counter is finished with the interval count, it clears the FC_BUSY=0 bit and after a few cycles of clk_sys synchronization delay it sets the FC_DONE=1 bit. Both interval counter and main FC_COUNT counter are stopped and the main FC_COUNT keeps the accumulated value until the frequency counter is disabled or triggered again. The 23 bit FC_COUNT value can be read as a 4 byte long word, lFcCount, from the XREG register in XDATA. When the counter is counting and FC_BUSY=1, then reading the FC_COUNT value returns the on the fly changing value of the FC_COUNT counter. The frequency counter is restartable. If 1 is written to FC_BUSY while the frequency counter is busy then the current FC_COUNT result is discarded, main FC_COUNT is reset, and the interval counter is triggered, waiting for the first rising edge of the clk_int clock. The count interval is chosen with the FC_INTERVAL SFR register. The number of interval count cycles (count cycles of the low frequency clock) = (2+FC_INTERVAL[0])*(2^FC_INTERVAL[5:1]). Note: FC_INTERVAL is not allowed to take on numbers higher than 43. If the number is higher than 43, then the interval counted is forced to 1. The output of the frequency counter is in the XREG FC_COUNT. The user is recommended to use the Frequency Counter Module Function API to set the following registers. Rev. 0.6 57 Si4010 16.1. Register Description SFR Definition 16.1. FC_CTRL Bit 7 6 Name FC_DONE FC_BUSY 5 4 3 2 1 FC_DIV_ SEL Reserved 0 FC_MODE[2:0] Type R/W R/W R/W R R/W Reset 0 0 0 0 0 SFR Address = 0x9B Bit Name Function Frequency Counter Done. 7 Counting done, interrupt generation level signal. Must be cleared by software ISR. It is also cleared if 1 is written to fc_busy, which denotes the start of the next count. Any FC_DONE value can be written here, so one can invoke interrupt just writing 1 here. 0: Frequency counter is counting 1: Frequency counter done counting, must be cleared by software ISR Frequency Counter Busy. 6 FC_BUSY Frequency counter is busy counting. Falling edge of the fc_busy signal sets the FC_DONE=1. Writing 1 to this bit triggers a new FC counting cycle. FC is restartable, so any Wr 1 to this bit restart