MC68377 MC68300 MC68000 CPU32X QADC64 J1850 MC68332 MC68332UM/AD CPU32 - Datasheet Archive

 

OVERVIEW 1.1 Introduction The MC68377 is a member of the MC68300 family of modular microcontrollers. This family includes a

 

SECTION 1 OVERVIEW 1.1 Introduction The MC68377 MC68377 is a member of the MC68300 MC68300 family of modular microcontrollers. This family includes a series of modules from which numerous microcontrollers (MCUs) are being assembled. These modules are connected on-chip via the inter-module bus (IMB). A short description of each module used in the MC68377 MC68377 appears in the following sections. 1.2 Module List The MC68377 MC68377 chip contains twelve modules. These modules are: 1. MC68000 MC68000 family central processing unit (CPU32X CPU32X) 2. Burst integration module (BIM) 3. 32-Kbyte (16-Kbyte x 16) fast access SRAM module (FASRAM) 4. Two time processor units (TPU3) 5. Dual-port RAM for TPU3 (DPTRAM) 6. Two queued serial modules (QSM) 7. 10-bit queued analog to digital converter module (QADC64 QADC64) 8. Analog multiplexer (AMUX) 9. Configurable timer module (CTM9) 10. CAN serial communication module (TouCAN) 11. J1850 J1850 serial communication module (DLCMD2) 12. Four 512-byte SRAM modules (SRAM) 1.3 Referenced Documents As a complement to the present document, the following Motorola documents provide an in-depth functional description of the MC68377 MC68377 modules: · MC68332 MC68332 User's Manual (MC68332UM/AD MC68332UM/AD) · CPU32 CPU32 Central Processor Unit Reference Manual (CPU32RM/AD CPU32RM/AD) · QSM Reference Manual (QSMRM/AD) · TPU documentation (TPULITPAK/D, including the TPURM/AD) · MC68336/376 MC68336/376 Reference Manual with TouCAN (MC68336/376RM/AD MC68336/376RM/AD) · Configurable Timer Module Reference Manual (CTMRM/AD) MC68377 MC68377 REFERENCE MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 1-1 1.4 Feature List The major features of the MC68377 MC68377 are: · Modular architecture: - Compatible with the current modular library of peripherals - Separate program bus (imb) and data bus (FAB - fast access bus) - Burst mode internal bus (IMB) and external bus for instruction fetches - Burst mode chip select for glueless connection to burst mode memories - Fast one clock access static RAM for data accesses (FASRAM) - Fully static implementation · 32-Bit 68000 family CPU (CPU32x): - Object code compatible with the CPU32 CPU32 - Greater than 2X performance increase over CPU32 CPU32 at same system frequency - Clock doubled (2X system clock) operation - Burst mode program fetches - Six word instruction prefetch queue - One-clock fast access data bus (FAB) - Virtual memory implementation - Loop mode of instruction execution - Improved exception handling for controller applications - Table lookup and interpolate instruction - High level language support - Hardware breakpoint signal, background debug mode · Burst integration module (BIM): - External asynchronous bus and synchronous burst mode bus support - Improved memory access timing - One burst mode chip select output (five pins) - Seven programmable asynchronous chip select outputs - Three modes of operation: master mode, single chip mode, and emulation mode - System protection logic with improved loss-of-oscillator protection - Automatic configuration from shadow registers - System clock based on 5.50-MHz crystal - Watchdog timer, clock monitor, and bus monitor · 32-Kbyte (16-Kbyte x 16) fast access SRAM (FASRAM): - Dynamic dual access on IMB and FAB - Separate standby power supply pin for 32 Kbytes of standby SRAM · Two serial I/O subsystems (queued serial module: QSM): - Enhanced SCI (UART): modulus baud rate generator, parity - Queued SPI: 80-byte RAM, up to 16 automatic transfers, continuous cycling, eight to 16 bits per transfer, LSB/MSB first - Dual function I/O port pins · 10-Bit queued analog to digital converter with internal analog multiplexer (QADC64/AMUX QADC64/AMUX): - 26 channels (with two 8-bit internal analog MUXs) - Four automatic channel selection and conversion modes MC68377 MC68377 REFERENCE MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 1-2 - Two channel scan queues of variable length - Queue pointers indicate current location for each queue - Automated queue modes initiated by software command, external edge trigger/level gate, or one periodic/interval timer assignable to both queue one and two - Sub-queues possible using pause mechanism - Queue complete and pause software interrupts available in both queues - 64 result registers and three result alignment formats - Programmable input sample time - 10-bit A/D converter with internal sample/hold - Typical conversion time is 10 µs (100-Kbyte samples/sec) full accuracy - Programmable frequency and duty cycle for A/D converter clock · Two time processor units (TPU3) (refer to Appendix C): - 16 channels - each is associated with a pin - Each channel can perform any time function - Each time function may be assigned to more than one channel - Each channel has an event register comprised of: 16-bit capture register, 16bit compare/match register, 16-bit comparator - Each channel can be programmed to perform match or capture operations with one, or both, of the two 16-bit free running timer count registers (TCR1 and TCR2) - TCR1 is clocked from the internal TPU3 system clock - TCR2 may be clocked or gated from the external T2CLK pin - All time primitives are microcoded - Four Kbytes of microstore program ROM space - All channels have eight 16-bit parameter registers - A hardware scheduler with three priority levels is included - Resolution is one system clock period - Modulus prescaler (DIV 2, 4, 6. 62, 64) · Six Kbytes dual port memory for TPU3 (DPTRAM): · Configurable timer module #9 (CTM9): - One bus interface unit submodule (BIUSM) - One counter prescaler submodule (CPSM) - One free-running counter submodule (FCSM) - Two modulus counter submodule (MCSM) - Four single action submodules (SASM) - Four double action submodules (DASM) - Four dedicated PWM submodules (PWMSM) · Data link controller module digital (DLCMD) - Requires a 22 MHz system clock for correct bit timing - GM class-two compatible / SAE J1850 J1850 compatible - 10.4 KBps VPW bit format - Handles all network protocol functions - Message buffering on transmit (11 bytes - full message) and on receive (20 bytes) - Hardware CRC generation and checking - Transmit and receive block mode support MC68377 MC68377 REFERENCE MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 1-3 · CAN 2.0B controller module (TouCANTM): - Full implementation of CAN protocol - version 2.0B. - Standard/extended data and remote frames (up to 109/127 bits long). - Programmable bit rate up to one Mbit/s, derived from system clock. - 16 Rx/Tx message buffers of 0-8 bytes data length, of which two buffers are configurable to work as Rx buffers with specific programmable masks. - Full implementation of CAN protocol - version 2.0B. - Standard/extended data and remote frames (up to 109/127 bits long). - Programmable bit rate up to one Mbit/s, derived from system clock. - 16 Rx/Tx message buffers of 0-8 bytes data length, of which two buffers are configurable to work as Rx buffers with specific programmable masks. · SRAM - Two Kbytes (4 x 512 bytes) static RAM (SRAM). · Package: 324-pin BGA · Technology: sub-micron HCMOS · Operating temperature: -40° C to 125° C · Operating frequency: 22.00-MHz maximum system clock at VDD = 3.3 V 5% · 3.3-V core voltage (3.3-V external interface with 5-V tolerant inputs). · 5-V general purpose digital I/O. 1.5 Functional Block Diagram A functional block diagram of the MC68377 MC68377 chip appears in Figure 1-1: MC68377 MC68377 REFERENCE MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 1-4 VWRITE VDS VDATA[15:0] VSIZE VADDR[14:0] VSTBY TP[15:0]B T2CLKB VDDDPTRAM TP[15:0]A T2CLKA CPWM[8:5] CTD[10:9]/[4:3] CTS[20B:14A] CTM2C CPU32X CPU32X PORT K FASRAM (16Kx16) IPIPE2 IPIPE1 IPIPE0 DSI DSCLK DBGENB D[15:8]/PG[7:0] D[7:0]/PH[7:0] PORT F TPU3B DPTRAM 6 Kbytes CTM9 TPU3A SRAMs 4x512 Bytes BKPT 32 Kbytes BCLK/PK[7] BWE/PK[6] BOE/PK[5] BAA/PK[4] LBA/PK[3] BREQ/PK[2] BTACK/PK[1] DTACK/PK[0] PORT G/H CONTROL Inter-Module Bus IRQX/BERR/PF[7] IRQ[6:5,3:1]/PF[6:5, IRQ4//PF[4] CS4/PF[0] FC[2:0]/CS[7:5]/ FREEZE CLKOUT/PE[4] SIZE/PE[3] AS/PE[2] DS/PE[1] R/W/PE[0] QSMA SCENB CSE1 AS QSMB R/W BIM NMI IRQ A[23:16] MISOB/D0B MOSIB/D1B SCKB/D2B PCS0B/SSB/D3B PCS[3:1]B/D[6:4]B TXDB/D7B RXDB D[15:0] MISOA/D0A MOSIA/D1A SCKA/D2A PCS0A/SSA/D3A PCS[3:1]A/D[6:/4]A TXDA/D7A RXDA *ANX[15:0] *PQA[7:0] *PQB[7:0] VSSA VDDA VRL VRH CNTX CNRX CL2TX CL2RX A[15:0] PORT A/B/C QADC64 QADC64 w/ AMUX TouCAN DLCMD CSE0 CLKOUT CONTROL PORT D PORT E QUOT CS3-CS1/PD[7:5] FREEZE/QOUT/PD[4]/CSEI BKPT/DSCLK/PD[3] IPIPE2/PD[2] IPIPE1/DSI/PD[1] IPIPE0/DSO/PD[0] A[23:16]/PC[7:0] A[15:8]/PA[7:0] A[7:0]/PB[7:0] RESET RSTOUT/CSE0 XTAL EXTAL VDDSYN VSSSYN EBR/TSC *See Table 8-1 for breakdown of pin functions. Figure 1-1 Block Diagram MC68377 MC68377 REFERENCE MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 1-5 Table 1-1 MC68377 MC68377 Pin Usage/Pin Definitions Module Pin Name Pins I/O 8 A[7:0]/PB[7:0] 8 A[23:16]/ PC[7:0] 8 Drive Stren. - 3.3 V 40 pf/80 pf 5V - sel2 sel3 3.3 V - 3.3 V 40 pf/80 pf 5V I/O Address[15:8] A[15:8]/PA[7:0] Output Voltage - sel2 sel3 3.3 V - 3.3 V 40 pf/80 pf sel3 Input Act Voltage Lvi Function I/O PortA[7:0] I/O Address[7:0] I/O PortB[7:0] I/O Address[23:16] 3.3 V - - 3.3 V 40 pf/80 pf 5V - sel2 - 3.3 V - - - 5V - sel - 3.3 V 5V - sel2 sel3 3.3 V L 3.3 V 3.3 V - - - 5V - sel2 - H 3.3 V O Quotient out - - 3.3 V - - 3.3 V 40 pf/80 pf 5V - sel2 3 L 3.3 V 1 1 AS/PE[2] 1 SIZE/PE[3] 1 CLKOUT/PE[4] 1 O BDM serial clock Emulation mode chip select[1] I/O PortD[7:5] 5V - sel2 - L 3.3 V 5V - sel2 TP Hyst/ Sync - A TP Hyst/ Sync - A TP Hyst/ Sync - A TP Hyst/ Sync U A TP Hyst/ Sync TP A TP Hyst/ Sync TP A1 TP Hyst/ Sync TP A1 TP Hyst/ Sync TP A1 TP Hyst/ Sync TP A1 TP Hyst/ Sync U/D4 A1 TP Hyst/ Sync - A sel 3.3 V L 3.3 V 40 pf/80 pf 5V - sel2 sel3 3.3 V L 3.3 V 40 pf/80 pf 5V - sel2 sel3 3.3 V - 3.3 V 40 pf/80 pf sel3 I/O PortE[0] I/O PortE[1] I/O PortE[2] I/O Transfer size 3 3 I/O PortE[3] 5V - sel2 O Clock output REFERENCE MANUAL A1 40 pf/80 pf I I/O Address strobe MC68377 MC68377 - sel BDM serial data input I/O Data strobe DS/PE[1] Hyst/ Sync 40 pf/80 pf I BDM serial output data I/O Read/write R/W/PE[0] TP sel3 - A1 40 pf/80 pf O Chip selects[3:1] CS[3:1]/PD[7:5] 1 - 40 pf/80 pf I/O PortD[4] FREEZE/ QUOT/CSE1/ PD[4] Hyst/ Sync sel3 O Freeze BIM 1 TP 40 pf/80 pf O I/O Break point BKPT/DSCLK/ PD[3] A1 40 pf/80 pf I/O PortD[1] - sel3 - Hyst/ Sync 40 pf/80 pf 3.3 V TP sel3 - Input Buffer 40 pf/80 pf I/O PortD[3] 1 3.3 V O Pipe tracking IPIPE2/PD[2] - I/O PortD[1] 1 - O Pipe tracking IPIPE1/DSI/ PD[1] - I/O PortD[0] 1 5V O Pipe tracking IPIPE0/DSO/ PD[0] I/O PortB[7:0] sel2 Pull OutUp/ put Down Type Driver - - 3.3 V 40 pf/80 pf I/O PortE[2] 5V - sel2 sel3 OVERVIEW Rev. 15 Oct 2000 MOTOROLA 1-6 Table 1-1 MC68377 MC68377 Pin Usage/Pin Definitions (Continued) Module Pin Name Pins I/O O Input Act Voltage Lvi Output Voltage Drive Stren. 1 40 pf/80 pf 5V - sel2 L 3.3 V 5V - sel3 3.3 V L 3.3 V 3 IRQ4/PF[4] 1 Interrupt request[3:1] 5V Interrupt request[4] I/O I/O Bus Error I/O 5 D[7:2,0]/ PH[7:2,0] 7 D[1]/PH[1] 1 DTACK/PK[0] 1 - sel2 L 3.3 V - sel2 3.3 V L 3.3 V L sel 2 3.3 V - sel 3.3 V - 3.3 V - 3.3 V - 3.3 V 3.3 V - 3.3 V U A TP Hyst/ Sync U/D5 A1 Hyst/ Sync U A1 TP Sync U/D5 A1 TP Sync U A1 TP Hyst/ Sync U/D4 A Hyst/ Sync U/D4 A TP Hyst/ Sync U/D4 A1 Hyst/ Sync U/D4 A1 Hyst/ Sync - A1 40 pf/80 pf 3.3 V 3.3 V I/O PortH[7:0] 5V - sel2 3.3 V - 3.3 V 40 pf/80 pf 5V - sel2 3.3 V 3.3 V - 3.3 V 40 pf/80 pf 5V - sel2 3.3 V 3.3 V L 3.3 V 40 pf/80 pf I/O PortH[1] I/O PortH[1] 1 Burst transfer acknowledge 1 sel L 3.3 V 40 pf/80 pf 5V Burst CS load burst address - sel2 3.3 V - L 3.3 V 40 pf/80 pf 5V Burst CS address advance I/O PortK[4] 3.3 V - 3.3 V I/O PortK[3] O 2 5V I/O PortK[2] O REFERENCE MANUAL Hyst/ Sync 40 pf/80 pf - I/O Burst request MC68377 MC68377 TP 40 pf/80 pf sel2 I/O Data bus[7:0] 1 A sel 5V I/O PortK[1] BAA/PK[4] - 3 sel2 I/O LBA/PK[3] Hyst/ Sync 40 pf/80 pf 2 I/O PortG[7:4,2] 1 A sel3 3.3 V Data bus[15:12,10] I/O Data bus[1] BREQ/PK[2] - 40 pf/80 pf I/O Data bus[1] BTACK/PK[1] Hyst/ Sync sel3 5V I/O PortG[3,1,0] BIM D[15:12,10]/ PG[7:4,] A 40 pf/80 pf 5V I/O Data bus[11,9,8] 3 3.3 V 3.3 V I/O PortF[7] D[11,9,8]/ PG[3:,1,0] L 5V I/O PortF[6:5] 1 - sel3 3.3 V Interrupt request[6:5] I/O Interrupt request IRQX/BERR/ PF[7] sel2 5V I/O PortF[4] 2 - 3.3 V I/O PortF[3:1] I/O IRQ[6:5]/ PF[6:5] Hyst/ Sync 40 pf/80 pf I/O PortF[0] I/O IRQ[3:1]/ PF[3:1] A1 40 pf/80 pf sel2 - sel3 - Hyst/ Sync TP 3.3 V TP TP L A1 TP - - 40 pf/80 pf O Chip selects[7:5] Hyst/ Sync TP 3.3 V TP TP - O Chip select[4] CS[4]/PF[0] 3 - Input Buffer TP Function code[2:0] I/O PE[7:5] FC[2:0]/ CS[7:5]/PE[7:5] Pull OutUp/ put Down Type Driver TP Function - sel2 - L 3.3 V 5V - OVERVIEW Rev. 15 Oct 2000 sel2 3.3 V 40 pf/80 pf 3.3 V MOTOROLA 1-7 Table 1-1 MC68377 MC68377 Pin Usage/Pin Definitions (Continued) Module Pin Name Pins I/O O BOE/PK[5] 1 Burst CS output enable BWE/PK[6] 1 Drive Stren. 3.3 V 40 pf/80 pf Burst CS write enable - sel2 - L 3.3 V RESET 1 RSTOUT/CSE0 1 XTAL EXTAL BIM Hyst/ Sync U/D4 A1 Hyst/ Sync - A1 TP Hyst/ Sync - A1 OD Hyst/ Sync U A TP - U A6 40 pf/80 pf 5V - sel2 O Burst CS clock 1 Pull OutUp/ put Down Type 3.3 V I/O PortK[6] BCLK/PK[7] Input Buffer TP L 5V I/O PortK[5] O - Output Voltage Driver TP Input Act Voltage Lvi Function - - 3.3 V 40 pf/80 pf 5V - sel2 3.3 V 3.3 V L 3.3 V 40 pf/80 pf I/O PortK[7] I/O Reset 3.3 V O Burst CS clock - L 3.3 V 40 pf/80 pf O PortK[7] - - 3.3 V 40 pf/80 pf 1 - Crystal - L - - - - - - 1 - - L - - - - - - - Hyst/ Sync U A Crystal external clock External bus request 3.3 V L - - I 1 EBR/TSC I Tri-state control 3.3 V L - - Total for Module = 77 pins VADDR[14:0] O Visibility address bus - - 3.3 V 40 pf/80 pf TP - D A VDATE[15:0] 16 O Visibility data bus - - 3.3 V 40 pf/80 pf TP - D A VWRITE 1 O Visibility bus write strobe - L 3.3 V 40 pf/80 pf TP - D A VDS 1 Visibility bus O data strobe - L 3.3 V 40 pf/80 pf TP - D A VSIZE 1 O Visibility bus operand size - - 3.3 V 40 pf/80 pf TP - D A VSTBY FASRAM 15 1 - Standby supply voltage 3.3 V - - - - - - - Total For Module = 35 Pins MC68377 MC68377 REFERENCE MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 1-8 Table 1-1 MC68377 MC68377 Pin Usage/Pin Definitions (Continued) Module Pin Name Pins I/O Input Act Voltage Lvi Function Output Voltage Drive Stren. Driver Input Buffer - - - - sel7 50 pf TP Hyst/ Sync - - - - sel7 50 pf TP Hyst/ Sync I AN56/ETRIG2/ AN56/ETRIG2/ PQA4 - I/O Port A digital I/O[2:0] 5V - Port A analog input[55] An - I/O Port A digital I/O[3] 5V - I AN55/ETRIG1/ AN55/ETRIG1/ QADC6 PQA3 4 An I AN[54:52]/ PQA[2:0] Port A analog inputs[54:52] Port A analog input[56] An - - - - - I Port A external trigger[2] 5V L/H - - - Hyst/ Sync Port A digital I/O[4] 5V - 50 pf TP Hyst/ Sync 3 1 1 I/O MC68377 MC68377 REFERENCE MANUAL Pull OutUp/ put Down Type OVERVIEW Rev. 15 Oct 2000 5 V/ 5 V/ 5 V/ sel7 - B - B - B MOTOROLA 1-9 Table 1-1 MC68377 MC68377 Pin Usage/Pin Definitions (Continued) Module Pin Name Pins I/O Input Act Voltage Lvi Function Output Voltage Drive Stren. Driver Input Buffer - - - - sel7 50 pf TP Hyst/ Sync I An - I/O Port A digital I/O[7:5] 5V - I Por tB analog input[0] An - - - - - I Port B analog input[W] An - - - - - I Port B digital input[0] 5V - - - - Hyst/ Sync I PortB analog input[1] An - - - - - I Port B analog input[X] An - - - - - I Port B digital input[1] 5V - - - - Hyst/ Sync I Port B analog input[2] An - - - - - I Port B analog input[Y] An - - - - - I Port B digital input[2] 5V - - - - Hyst/ Sync I Port B analog input[3] An - - - - - I Port B analog input[Z] An - - - - - I Port B digital input[3] 5V - - - - Hyst/ Sync I Port B analog inputs[51:48] An - - - - - I AN[59:57]/ PQA[7:5] Port A analog inputs[59:57] Port B digital inputs[7:4] 5V - - - - Hyst/ Sync 3 AN0/ANW/ PQB0 (For Test Purposes Only) 1 AN1/ANX/ PQB1 (For Test Purposes Only) 1 AN2/ANY/ PQB2 (For Test PurQADC6 poses Only) 4 1 AN3/ANZ/ PQB3 1 Pull OutUp/ put Down Type 5 V/ - B - B - B - B - B - B AN[51:48]/ PQB[7:4] 4 ANX[15:0] 16 I Mux'd analog inputs[15:0] An - - - - - B VRH 1 - Voltagle reference high 5V - - - - - - VRL 1 - Voltagle reference low - - - - - - - VDDA 1 - Analog supply 5V - - - - - - VSSA 1 - Analog ground - - - - - - - Total For Module = 36 Pins MC68377 MC68377 REFERENCE MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 1-10 Table 1-1 MC68377 MC68377 Pin Usage/Pin Definitions (Continued) Module Pin Name Pins I/O I/O MISOA/D0A 1 Output Voltage Drive Stren. - 5 V/50 ns 200 pf 50 pf Hyst Hyst/ Sync Input Act Voltage Lvi Function Master in/slave out 5V Driver TP8 Input Buffer Hyst/ Sync General purpose I/O I/O D0 5V - 5 V/ 600 ns Master out/slave in 5V - 5 V/50 ns 200 pf 5V - 5 V/ 600 ns 50 pf Peripheral chip select0 5V - 5 V/50 ns 200 pf Slave select 5V L - - Hys/ Sync I/O General purpose I/O D3 5V - 5 V/ 600 ns 50 pf I/O 1 Peripheral chip selects[3:1] 5V - 5 V/50 ns 200 pf Hyst/ Sync 50 pf 200 pf General purpose I/O I/O D1 I/O PCS0A/SSA/ QSMA D3A PCS[3:1]A/ D[6:4]A 1 3 I General purpose I/O I/O D[6:4] 5V - 5 V/ 600 ns SCI transmit date - - 5 V/50 ns O TxDA/D7A RxDA 1 1 - C - C Hyst I/O MOSIA/D1A Pull OutUp/ put Down Type General purpose I/O I/O D7 I SCI receive data 5V - 5 V/ 600 ns 5V - - TP8 Hyst 8 TP TP8 Hyst/ Sync C - - C - C Hyst - 8 TP 50 pf Hyst - Hyst Total For Module = 9 pins MC68377 MC68377 REFERENCE MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 1-11 Table 1-1 MC68377 MC68377 Pin Usage/Pin Definitions (Continued) Module Pin Name Pins I/O I/O MISOB/D0B 1 Output Voltage Drive Stren. - 5 V/50 ns 200 pf 50 pf Hyst Hyst/ Sync Input Act Voltage Lvi Function Master in/slave out 5V Driver TP8 Input Buffer Hyst/ Sync General purpose I/O I/O D0 5V - 5 V/ 600 ns Master out/slave in 5V - 5 V/50 ns 200 pf 5V - 5 V/ 600 ns 50 pf Peripheral chip select0 5V - 5 V/50 ns 200 pf Slave select 5V L - - Hys/ Sync I/O General purpose I/O D3 5V - 5 V/ 600 ns 50 pf I/O 1 Peripheral chip selects[3:1] 5V - 5 V/50 ns 200 pf Hyst/ Sync 50 pf 200 pf General purpose I/O I/O D1 I/O PCS0B/SSB/ QSMB D3B 1 PCS[3:1]B/ D[6:4]B 3 I General purpose I/O I/O D[6:4] 5V - 5 V/ 600 ns SCI transmit date - - 5 V/50 ns O TxDB/D7B 1 RxDB 1 - C - C Hyst I/O MOSIB/D1B Pull OutUp/ put Down Type General purpose I/O I/O D7 I SCI receive data 5V - 5 V/ 600 ns 5V - - TP8 Hyst 8 TP TP8 Hyst/ Sync C - - C - C Hyst - 8 TP 50 pf Hyst - Hyst Total For Module = 9 pins TP[15:0]A 16 I/O Timer channel 5V L/H T2CLKA 1 External clock input 5V L/H TPU3A I 5 V/ sel7 50 pf TP Hyst - C - - - Hyst U C sel7 50 pf TP Hyst - C Total For Module = 17 pins 5 V/ TP[15:0]B 16 I/O Timer channel 5V L/H T2CLKB 1 External clock input 5V L/H - - - Hyst U C TPU3B I Total For Module = 17 pins CTM2C 1 I External clock input 5V L/H - - - Hyst/ Sync - C CTD[4:3] 2 I/O DASM channels[4:3] 5V L/H 5 V/ sel7 50 fp TP Hyst/ Sync - C CTM9 CTM[8:5] 4 I/O PWMSM channels[8:5] 5V L/H 50 fp TP - - C CTD[10:9] 2 I/O DASM Channels[10:9] 5V L/H 50 fp TP Hyst/ Sync - C CTS[20B:14A] 8 I/O SASM channels[20:14] 5V L/H 50 fp TP Hyst/ Sync - C 5 V/ sel7 5 V/ sel7 5 V/ sel7 Total For Module = 17 pins MC68377 MC68377 REFERENCE MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 1-12 Table 1-1 MC68377 MC68377 Pin Usage/Pin Definitions (Continued) Module TouCAN Pin Name Pins I/O Input Act Voltage Lvi Function CNRX 1 I CAN receive CNTX 1 O CAN transmit Output Voltage Drive Stren. Driver Input Buffer Pull OutUp/ put Down Type 5V - - - - - - C 5V - 5 V/ 50ns 200 pf TP8 - - C 5V - - - - - - C Total For Module = 2 pins CL2RX 1 I Class 2 receive DLMCD CL2TX 1 O Class 2 transmit 5V - 5 V/50 ns 50 pf TP - - C CNRX 1 I 5V - - - - - - C CAN receive Total For Module = 2 pins MC68377 MC68377 REFERENCE MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 1-13 Table 1-1 MC68377 MC68377 Pin Usage/Pin Definitions (Continued) Module Pin Name Pins I/O Input Act Voltage Lvi Function Output Voltage Drive Stren. Driver Input Buffer Pull OutUp/ put Down Type VDDSYN 1 - Clock synthesizer power 3.3 V - - - - - - - VSSSYN POWER/ VDD3 GND VSS 1 - Clock synthesizer ground - - - - - - - - 73 - Supply voltage 3.3 V - - - - - - - 23 - Ground - - - - - - - - VDDS5 10 - Supply voltage 5V - - - - - - - VDDPTRAM 1 - DPTRAM supply 3.3 V - - - - - - - Power/Ground = 103 pins Total Number of Pins for MCU = 324 Pins Sync = Synchronized Hyst = Hysteresis OD = Open Drain TP = Totem Pole An = Analog NOTES: 1. Driver three-stated on EBR. 2. Either 5-V / 600-ns slew rate or 3.3-V no slew rate control based upon state of FASTIO bit in BIM MCR. 3. Either 50 pf or 40 pf/80 pf drive strength based upon state of FASTIO bit in BIM MCR. 4. Pullup or pulldown at RESET depending upon PCON register bit. Disabled after RESET. 5. Pullup or pulldown at RESET depending upon PCON register bit. Pullup after RESET. 6. Will not three-state on TSC (required by PLL test mode). 7. Either 5-V / 600-ns or 5-V / 50-ns slew rate based upon state of FASTIO bit in BIM MCR. 8. Module will configure signals for OD operation. MC68377 MC68377 REFERENCE MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 1-14 0xYF F000 QADC64 QADC64 1024 Bytes 0xYF F400 QSM(B) 512 Bytes 0xYF F600 DLCMD 16 Bytes SRAM(A) ARRAY 512 Bytes 0xYF F610 - RESERVED -0xYF F660 SRAM(A) 8 Bytes SRAM(B) SRAM(B) ARRAY 512 Bytes 8 Bytes 0xYF F668 SRAM(C) ARRAY 512 Bytes 0xYF F670 SRAM(C) 8 Bytes SRAM(D) 8 Bytes DPTRAM 64 Bytes FASRAM 32 Bytes 0xYF F678 0xYF F680 SRAM(D) ARRAY 512 Bytes 0xYF F6C0 0xYF F6E0 DPTRAM ARRAY 6 Kbytes - RESERVED -0xYF F700 CTM9 256 Bytes TPU3(B) 512 Bytes BIM 128 Bytes TouCAN 512 Bytes 384 QSM(A) 512 Bytes TPU3(A) 512 Bytes 0xYF F800 FASRAM ARRAY 32 Kbytes 0xYF FA00 0xYF FA80 0xYF FC00 0xYF FE00 0xYF FFFF Y = M111, where M is the MODMAP signal state on the IMB, which reflects the state of the MODMAP in the module configuration register of the burst integration module. ( Y= 0x7 or 0xF). Figure 1-2 MC68377 MC68377 Address Map MC68377 MC68377 REFERENCE MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 1-15 MC68377 MC68377 REFERENCE MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 1-16