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CPU/PR3010A

Catalog Datasheet MFG & Type PDF Document Tags

53C700

Abstract: PR3000A $-FEATURES 33MHz and 40MHz RISC PR3400 (Integrated PR3000A CPU/PR3010A FPA) Offer 28 and 32 VAXmips respectively , variety of other scientific applications. CPU/FPA/Cache/Buffers Subsystem ThePaceRunner/3400 board uses a PR3400 CPU daughter-board that provides the CPU/FPA, cache memory, write/read, and parity buffer , daughter-board are the following: PR3400 integrated CPU and FPA, 64KBytes of instruction cache, 64KBytes of data , 33 MHz. The board supports instruction streaming, that allows the PR3400 CPU/FPA to execute
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53C700 53c70 scsi manual CPU/PR3010A IEEE1014 PR3100A RS232 SCC2692 53C710

mips r3010

Abstract: PR3000A PaceMips" PR3010A FPA 32-BIT RISC CO-PROCESSOR (FLOATING POINT ACCELERATOR) ¿ s , PR3010A Co-Processor is a floating point accelerator that operates in conjunction with the PaceMips , Binary Ftoating Point Arithmetic." Like the PaceMips PR3000A, the PR3010A uses the LOAD/ STORE , PaceMips PR3010A -1.0 SIGNAL DESCRIPTIONS I/O o I I 0 0 0 I A , the FPA which indicates exception related status information. Signal to the CPU indicating a request
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mips r3010 R3010 mips processor R3010 MIL-STD-883C R3000A 160-P CA95112

PR3000A

Abstract: CPGA ,40 MQ 160 X Now 32-bit CPU 40 MHz Contact Marketing MQFP No D PR3010A 20,25,33 SR 84 X Now 32 , PR2000A' 16 PGC 145 X Now 32-bit CPU Use PR3000A for new designs CPGA No U PR2010A' 16 QJC 84 X Now 32-bit FPA UsePR3010A for new designs CQFPJ No U PR3000' 20,25,33 PGC 145 X Now 32-bit CPU Use PR3000A for new designs CPGA No u PR30001 20,25,33 QLC 172 X Now 32-bit CPU Use PR3000A for new designs CQFP No u PR30101 20,25,33 QJC 84 X Now 32-bit FPA Use PR3010A for new designs CQFPJ No u PR3010
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CPGA 84 pin cpu PR2000 PR301 CPU/FPA/PR3100A PCBM/3400- PR3400- VB004C VB016C

PR3000A

Abstract: CPGA ' PR3000A PR3000A PR3000A PR3000A PR3000A PR3010A PR3010A PR3010A PR3010A PR3010A PR3010A PR3020 PR3100P , '92 Now X X Now Now Now Now Now Now X X X X X X Q3'92 Q3'92 Q3'92 Q3'92 Q3'92 Q3'93 Now 32-bit CPU 32-bit FPA 32-bit CPU 32-bit CPU 32-bit FPA 32-bit FPA 32-bit FPA 32-bit 32-bit 32-bit 32-bit 32-bit 32-bit 32-bit 32-bit 32-bit 32-bit 32-bit 32-bit CPU CPU CPU CPU CPU CPU FPA FPA FPA FPA FPA FPA Use PR3000A , PR3010A for new designs Use PR301OA for new designs Use PR3010A for new designs For old existing designs
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PR2000A1 PR3400L PR3400N PR4000P2 PR4000S2 PR4000M2
Abstract: receive the synchronization clock from the CPU. 4/1/92 1-20 PaceMlp» PR3010A 2.0 ELECTRICAL , Pace Mips PR3010A FPA 32-BIT RISC CO-PROCESSOR (FLOATING POINT ACCELERATOR) FEATURES â  32 , DESCRIPTION The PaceMips PR3010A Co-Processor is manufactured using PACE III Technology which is Performance , PaceMips PR3010A Co-Processor is a floating point accelerator that operates in conjunction with the , Standard for Binary Ftoating Point Arithmetic.â'™' Like the PaceMips PR3000A, the PR3010A uses the LOAD -
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84 PIN CERAMIC QUAD FLAT PACK

Abstract: MPSC L01 PERFORMANCE SEMICONDUCTOR SOE PaceMipsâ"¢ PR3010A FPA TDbSST? 0001427 513 «PSC 32-BIT RISC , Produced with PACE III Technologyâ"¢ -:- DESCRIPTION The PaceMips PR3010A Co-Processor is a floating , ." Like the PaceMips PR3000A, the PR3010A usesthe LOAD/ STORE architecture to increase system performance , PaceMips PR3010A 1.0 SIGNAL DESCRIPTIONS Data(31:0) I/O A multiplexed 32-bit bus used for instruction and , indicates exception related status information. FpBusy 0 Signal to the CPU indicating a request for a
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84 PIN CERAMIC QUAD FLAT PACK MPSC L01 fpa g12 MIPS R3000A burndy R3000a Performance Semiconductor T-49-12-05
Abstract: PERFORMANCE SEMICONDUCTOR 50E D I ?QbSSR7 QQG1427 S 1 3 « P S C PaceMipsâ' PR3010A , facility. The PaceMips PR3010A Co-Processor is a floating point accelerator that operates in , PR3010A uses the LOAD/ STORE architecture to increase system performance. In a LOAD/STORE architecture , store instructions can access the main memoiy system. Included in the PR3010A there are sixteen 64 , v c T O R c o PR3010A r p o r a t i o 1 1 CO PRO CESSO RS Means Quality -
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Abstract: CPU & FPA INTERCONNECTION 1.4 PR3400L OPERATION The PR3400L contains the PR3000A and PR3010A , PR3400L is identical to the operation of the PR3000A CPU and PR3010A FPU (connected as described in , PaceMipsâ"¢ PR3400L CPU 32-BIT RISC PROCESSOR WITH FLOATING POINT ACCELERATOR FEATURES , ilitary product com pliant to MIL-STD-883C, Class B â  CPU and FPA in a m o n o lith ic VLSI package , ic Pin G rid Array â  Floating Point Accelerator (PaceM ips PR3010A): â'¢ C ontains sixteen 64 -
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256KB

PR3000A

Abstract: workstations. 1.2 CPU & FPA INTERCONNECTION The PR3400L contains the PR3000A and PR3010A integrated on a single , The operation of the PR3400L is identical to the operation of the PR3000A CPU and PR3010A FPU , PR3000A and PR3010A Interface Specifications. Connection CPU Exception CpSync Reset Run Table 1.2 , PaceMipsTM PR3400L CPU 32-BIT RISC PROCESSOR WITH FLOATING POINT ACCELERATOR X r- FEATURES CPU and FPA in a monolithic VLSI package 32-BIT RISC Processor (PaceMips PR3000A) that contains
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TAG L7

Abstract: fpu coprocessor single die. 1.2 CPU & FPA INTERCONNECTION The PR3400N contains the PR3000A and PR3010A integrated on a , CACHES The operation of the PR3400N is identical to the operation of the PR3000A CPU and PR3010A FPU , PaceMipsâ"¢ PR3400N CPU 32-BIT RISC PROCESSOR WITH FLOATING POINT ACCELERATOR - FEATURES â  CPU and FPA in a monolithic VLSI package â  32-BIT RISC Processor (PaceMips PR3000A) that contains , "¢ â  Single IxClock Input â'¢ Built-in delay line â  Floating Point Accelerator (PaceMips PR3010A
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TAG L7 fpu coprocessor PR31 mps 1136 TAG 93 PR3400N-

1AM7

Abstract: PR3400 die. 1.2 CPU & FPA INTERCONNECTION The PR3400N contains the PR3000A and PR3010A integrated on a single , operation of the PR3400N is identical to the operation of the PR3000A CPU and PR3010A FPU (connected as , PaceMips" PR3400N CPU 32-BIT RISC PROCESSOR WITH FLOATING POINT ACCELERATOR FEATURES CPU and FPA , line Floating Point Accelerator (PaceMips PR3010A): · Contains sixteen 64-bit floating point registers , these two pins - - * |a . PaceMips PR3400N Table 1.1 FPA & CPU
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1AM7
Abstract: SRAM parameters. 1.2 CPU & FPA INTERCONNECTION The PR3400 contains the PR3000A and PR3010A , operation of the PR3400 is identical to the operation of the PR3000A CPU and PR3010A FPU (connected as , PaceMips1 PR3400 " CPU 32-BIT RISC PROCESSOR WITH FLOATING POINT ACCELERATOR X r- FEATURES â  CPU and FPA in a monolithic VLSI package â  32-BIT RISC Processor (PaceMips PR3000A) that , (PaceMips PR3010A): â  Contains sixteen 64-bit floating point registers to support single and double -
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PR2000

Abstract: R2000 mips processor PERFORMANCE INTEGRATED MIPS MODULE PIMM" FEATURES: Single VLSI muttichip module contains: · PR3000A CPU · PR3010A FPA · PR3100A Write/Read and Parity Buffer · Four P4C92815 Bicameral latched cache RAMs 32 , (MMU) · orvchip cache control for instruction and data cache Floating Point Accelerator PR3010A , ) is a single VLSI package containing the PR3000A RISC processor, the PR3010A floating point , and capacitance on the most critical high speed signals, this packaging provides the CPU / FPA / cache
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R2000 mips processor ha 1166 x 00D15S1 PR300QA 960X1560
Abstract: processor that contains the following: - CPU (PR3000A based) - FPA (PR3010A based) - Write/Read Buffer , compatible with the PR3000A RISC CPU and PR3010A FPA (MIPS-1 ISA) â  Flexible, asynchronous system , of the PIPER is based on the PR3000A CPU and PR3010A FPA. The PIPER can be viewed as a single-chip implementation of an PR3000A/ PR3010A sub-system that includes a CPU/FPA core, 8/4 Kbytes of instruction cache , Core The CPU/FPA core is based on the PR3000A/PR3010A and supports the MIPS-1 ISA (instruction set -
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MIPS R3000A

Abstract: PR3000A /Timers Instruction set compatible with the PR3000A RISC CPU and PR3010A FPA (MIPS-1 ISA) 32-bit RISC , engine of the PIPER is based on the PR3000A CPU and PR3010A FPA. The PIPER can be viewed as a single-chip implementation of an PR3000A/ PR3010A sub-system that includes a CPU/FPA core, 8/4 Kbytes of instruction cache, 2 , PIPER are described below. 2.1 CPU/FPA Core The CPU/FPA core is based on the PR3000A/PR3010A and , of the FPA is identical to the PR3010A. The FPA operates as a co-processor (CP1) to the CPU and with
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Abstract: cache â  Instruction set compatible with the PR3000A RISC CPU and PR3010A FPA (MIPS-1 ISA) â , PIPER is based on the PR3000A CPU and PR3010A FPA. The PIPER can be viewed as a single-chip implementation of an PR3000A/ PR3010A sub-system that includes a CPU/FPA core, 8/4 Kbytes of instruction cache , . 2.1 CPU/FPA Core The CPU/FPA core is based on the PR3000A/PR3010A and supports the MIPS-1 ISA , architecture of the FPA is identical to the PR3010A. The FPA operates as a co-processor (CP1) to the CPU and -
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PR3400

Abstract: fpa g12 operation of the PR3400 is identical to the operation of the PR3000A CPU and PR3010A FPU (connected as , Pace Mips"PR3400 CPU 32-BIT RISC PROCESSOR WITH FLOATING POINT ACCELERATOR FEATURES CPU and FPA , (PaceMlps PR3010A): · Contains sixteen 64-bit floating point registers to support single and double , CPU & FPA ICk DCfc 5R3" DW F 1R3 m B icam eral CACH E P 4 C 215 j PERFORMANCE , system s from em bedded control to workstations. generation unit and (2) a programm able FPA/CPU
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tag 136 m2 IL-STD-883C

PR2000

Abstract: MIPS R3000A PR3000A CPU · PR3010A FPA · PR3100A Wrtte/Read and Parity Buffer · bus snooper to assist In , signals, this packaging provides the CPU / FPA / cache / Read / Write The Performance Integrated MIPS Module (PIMM) is a single VLSI package containing the PR3000A RISC processor, the PR3010A floating point , standard components. Please refer to the PR3000A, PR3010A, and P4C92815 data sheets for more detailed , from the CPU. Since only bytes, half-words, tri-bytes and words may be encoded in this manner
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117 AJG

Abstract: MIPS R2000 contains the following: - CPU (PR3000A based) - FPA (PR3010A based) - Write/Read Buffer - Instruction and Data Caches - 32-bit Counters/Timers â  Instruction set compatible with the PR3000A RISC CPU and PR3010A FPA (MIPS-1 ISA) â  32-bit RISC Processor - Thirty-two general 32-bit registers - , protection. 2.0 PIPER OPERATION The execution engine of the PIPER is based on the PR3000A CPU and PR3010A , processor. The PIPER includes a 32-bit RISC CPU, ANSI/IEEE 754-1985 compliant floating point accelerator
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117 AJG MIPS R2000 performance piper mips risc architecture gerry kane MIPS FPA 256KD

MPS 2112

Abstract: dd1555 contains: â'¢ PR3000A CPU â'¢ PR3010A FPA â'¢ PR3100A Write/Read and Parity Buffer â'¢ Four P4C92815 , speed signals, this packaging provides the CPU / FPA / cache / Read / Write SYSTEM APPLICATION , standard components. Please refer to the PR3000A, PR3010A, and P4C92815 data sheets for more detailed , the CPU to operate at full speed without stalling during writes. For each CPU write, the write buffer , , Acknowledge, LE, OutEn and R/W. When the current CPU write fills the 8-word FIFO, the PR3100A asserts the
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MPS 2112 dd1555 td70c MPS 1213 Integrated Circuit APS-C type 00G1574
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