NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Samples | Ordering |
| EPM3256AFC25610 | Altera Corporation | CPLD 256CELLS 161/O 10NS [256/FBGA] | 
|
|
|
| EPM3064ATC4410N | Altera Corporation | MAX 3000A ISP PLD, 3.3V, 3034, TQFP44; Logic IC family:Programmable PLD; Logic IC Base Number:3034; Logic IC function:Programmable ISP; Voltage, supply:3.3V; Case style:TQFP / 44; Base number:3034; Gates, No. of:1250; I/O lines, No. of:34; RoHS Compliant: Yes |
|
|
|
| EPM3032ATC4410N | Altera Corporation | MAX 3000A ISP PLD, 3.3V, 3032, TQFP44; Logic IC family:Programmable PLD; Logic IC Base Number:3032; Logic IC function:Programmable ISP; Voltage, supply:3.3V; Case style:TQFP / 44; Base number:3032; Gates, No. of:600; I/O lines, No. of:34; RoHS Compliant: Yes |
|
|
|
| EPM3256ATC14410 | Altera Corporation | IC,EPLD, ALTERA,3256A,144TQFP |
|
|
|
| EPM240F100I5 | Altera Corporation | MAX® II Instant-On, Non-Volatile CPLDs: The Lowest-Power, Lowest-Cost CPLDs Ever; 100 pin FBGA; -40 to 105°C |
|
|
| Part | Manufacturer | Description | Type | Ordering |
| CPLD-2 22V10 s in 24-pin Package | Atmel Corporation | ATF750C(L) , 20 FFs, 10 I-O Pins, standard & low power |
16 pages, |
Original | |
|
|||||
| CPLD-2 22V10 s in 24-pin Package | Atmel Corporation | ATF750LVC , 20 FFs, 10 I-O Pins, 3-volt & 3-volt low power |
14 pages, |
Original | |
|
|||||
| CPLD ATF15xx Family-Industry Compatible | Atmel Corporation | ATF1516AS(L) , 256 Macrocell, standard & low power w-ISP |
13 pages, |
Original | |
|
|||||
| CPLD ATF15xx Family-Industry Compatible | Atmel Corporation | ATF1508ASV(L) , 128 Macrcells with ISP, 3-volt and low power |
22 pages, |
Original | |
|
|||||
| CPLD ATF15xx Family-Industry Compatible | Atmel Corporation | ATF1500A (L) , 1500 gate electrically erasable CPLD, 44 pins |
17 pages, |
Original | |
|
|||||
| CPLD-Proprietary | Atmel Corporation | ATV2500B (BQ)(BQL) , 2500 gate high-speed CPLD, standard & low power, 40 & 44 pins |
21 pages, |
Original | |
|
|||||
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: CPLD 5 CPLD 10uA2 15 / CPLD ispMACH 4000ZE 4000ZE CPLDI/O (3)4000ZE 4000ZE( ) HighLow : 3 CPLD CPLD CPLD 6 CPLD CPLD 1% CPLD 1.8V CPLD1.65V30 65V30% Vcc CPLDispMACH 4000ZE 4000ZE Block Input Enable CPLDCPLD (4) CPLD 7 CPLD 4 CPLD 30MHz5 , 4000ZE 4000ZE CPLDI/O CPLD () CPLD CPLD CPLD( ) I/O/ 3 CPLD CPLD "typical""maximum" (2) TypicalCPLD 2 CPLD 5%10% CPLD20% CPLD( ) 4 CPLD Typical ... | Original |
11 pages, |
CPLD 4000ZE datasheet abstract |
|
|||
| Abstract: CPLD CPLDCPLD CPLD CPLD 1% CPLD 1.8 6 CPLD Lattice Semiconductor CPLD1.6530% - Vcc CPLDispMACH 4000ZE 4000ZE(Lattice "Power Guard") Block Input Enable CPLD CPLD(4)CPLD , CPLDI/O CPLD() CPLD CPLD CPLDCPLD( ) CPLDI/O/ 3 CPLD Lattice Semiconductor CPLD "" "" (2) CPLD 2 Â CPLD 5%10% CPLD20% CPLD() ? ? 4 CPLD , Semiconductor (CPLD)I/O CPLD CPLD I/O CPLD Â CPLD CPLD CPLD I/O CPLDI/OispMACH ... | Original |
10 pages, |
4000ZE datasheet abstract |
|
|||
| Abstract: CPLD 10 uA 2-15 / CPLDispMACH 4000ZE 4000ZE CPLDI/O3 4000ZE 4000ZE: 4 Practical Low Power CPLD Design , 1.8VCPLD1.65V30 65V30 -Vcc CPLDispMACH 4000ZE 4000ZE"Power Guard" CPLDCPLD 4 CPLD 5 Practical Low Power CPLD , 4000ZECPLD1 4000ZECPLD1 I / O GPS Lattice ispMACH 4000ZE 4000ZE CPLDI/O 2 Practical Low Power CPLD Design A , ·VCCOI / OVCC ·I/O CPLD - CPLD - "" """" - CPLD - - 8 CPLDPower Guard , CPLD 20098 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 ... | Original |
9 pages, |
4000ZE datasheet abstract |
|
|||
| Abstract: CPLD A Lattice Semiconductor White Paper 2009 8 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA Telephone: (503) 268-8000 www.latticesemi.com 1 CPLD A Lattice Semiconductor White Paper . , . , I/O CPLD . CPLD , BOM . , CPLD , . , I/O . CPLD - (Edge) , CPLD , , . , , I/O . I/O , ispMACH4000ZE(1) CPLD ... | Original |
10 pages, |
4000ZE datasheet abstract |
|
|||
| Abstract: ispMACH® 4000ZE 4000ZE CPLD 2008 4 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA (503) 268-8000 www.latticesemi.com 1 ispMACH 4000ZE 4000ZE CPLD , . 8 2 ispMACH 4000ZE 4000ZE CPLD CPLD ispMACH® 4000ZE 4000ZE CPLD ASIC ASSP ASIC ASSP CPLD PDA GPS CPLD ispMACH 4000ZE 4000ZE CPLD CPLD CPLD ispMACH 4000ZE 4000ZE ispMACH 4000ZE 4000ZE ispMACH 4000Z 4000Z Power Guard 3 ispMACH 4000ZE 4000ZE CPLD I/O CPLD ispMACH 4000ZE 4000ZE 1 I/O E ... | Original |
8 pages, |
ispMACH 4000Z 4000ZE 4064ZE 4000ZE abstract |
|
|||
| Abstract: Demonstration Screens CPLD Demo Using Foundation VHDL Tools CPLD DEMO Â 1 Foundation Project Manager Using VHDL CPLD DEMO Â 2 HDL Language Assistant Templates & Libraries CPLD DEMO Â 3 1. XC9500 XC9500 Fitter Tools Easy as 1.2.3 3. 2. CPLD DEMO Â 4 Fitter Report Shows You What You Need To Know Flexible P-Term Cascading CPLD DEMO Â 5 Timing Reports User-Customized Summaries CPLD DEMO Â 6 ... | Original |
6 pages, |
XC9500 datasheet abstract |
|
|||
| Abstract: E-blocksTM CPLD board An ideal platform for programming CPLDs and for CPLD projects EB020 EB020 matrix multimedia · Suitable for programming and developing CPLDs · Free development software  , 8 bit E-blocks ports · Expansion connectors This CPLD programming and development board is suitable for both learning how to program CPLDs as well as for developing CPLD based projects. The CPLD board is compatible with Altera CPLD/FPGA development software Quartus II web edition. This superb ... | Original |
1 pages, |
CPLD 7000 SERIES CPLD datasheet abstract |
|
|||
| Abstract: deis digitrl rnd cpld ucco dds rnrlog supply supply cu cl cn cl m cl id cl cl o o digitrl ground test point tpl f \ 1 c21 a vr 10uf » o o o o ucc = cpld rnd rll ' non-dds' digitrl udd = cpld ucco rnd dds digitrl uddr = the rnrlog supply for the dds (rudd) c25 10uf single su j14c-^_|_ supply r 1 I -î-"Ti decoupling for the ucc next to pins 40 rnd 87 on the cpld rnd pin 20 on hc244 ^d , s pin 87 0503 prckrge pin 28 dds pin 43 dds pin 24 cpld pin 49 cpld tn -h u f ^ --i -h . u ... | OCR Scan |
3 pages, |
cpld PHILIP HC244 50OHM 50OHM abstract |
|
|||
| Abstract: Interconnect: XC4000E/X XC4000E/X FPGA n CPLD  1 DRAM Controller: XC9500 XC9500 ISP CPLD Digital Signal Processing: XC4000XL XC4000XL FPGA Case Study #1 - DRAM Controller XC9500 XC9500 CPLD n n CPLD  2 Fast memory , Fast address decode  66 MHz CPLD  tPD < 7.5 ns n Design on PC n VHDL entry n Addr. Low price uProc JTAG Pins CPLD  3 Address Decode Wait State Mach Interface , User-reconfigurable design n 5 V In-System Programmable (ISP) CPLDs (memory space allocation) n ... | Original |
15 pages, |
XC4000XL foundation field bus XC9500 address generator logic vhdl code vhdl code for memory controller CPLD DRAM Controller XC4000E/X XC9500 abstract |
|
|||
| Abstract: CPLDs and FPGAs. This tool can be run stand-alone to support any Xilinx CPLD or FPGA application and , New WebPACKÂ Packs a CPLD Punch WebPACK is a collection of downloadable modules that give you the best possible CPLD development solution while offering complete EDA tool flexibility . by Dave Grace, CPLD Software Product Manager, Xilinx, dave.grace@xilinx.com X ilinx has taken the industry's best works in conjunction with other EDA tools, CPLD implementation tool suite, cou pled it ... | Original |
2 pages, |
XC9500 thesis cpld datasheet abstract |
|
|||
| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
|||||
| software patches ( HTML version of CPLD.LST) CPLD.LST 9535 08-09-96 CPLD Software Patch -08-96 See CPLD.LST | Uploaded by: Jeffrey Goldberg EZTAG_PC.ZIP 779592 08-08-96 See CPLD.LST | Uploaded by: Jeffrey Goldberg EZTAG_SN.TAR 1466368 08-08-96 See CPLD.LST | Uploaded by: Jeffrey Goldberg FITTERHP.TAR 131072 08-08-96 See CPLD.LST | Uploaded by: Jeffrey Goldberg FITTERPC www.datasheetarchive.com/files/xilinx/bbs/swhlp/cpld/index.htm |
Xilinx | 24/09/1996 | 2.21 Kb | HTM | index.htm |
| Xilinx Solutions Database : XABEL-CPLD, 9500: Controlling Global Net Utilization for 9500 designswith XABEL-CPLD Solutions Database XABEL-CPLD, 9500: Controlling Global Net Utilization for 9500 designswith XABEL-CPLD Product Family: Software - Product Line: Data I/O - Problem Title: - XABEL-CPLD, 9500: Controlling Global Net Utilization for 9500 designs with XABEL-CPLD Problem Description: - This file contains information on controlling www.datasheetarchive.com/files/xilinx/weblinx/techdocs/1036.htm |
Xilinx | 23/09/1996 | 1.45 Kb | HTM | 1036.htm |
| Xilinx CPLD Design Flow Xilinx CPLD Design Flow Â"Basic CPLD Design FlowÂ" figure shows the basic design flow for creating CPLD designs. Each step is described in the following design example. Figure 1.1 Basic CPLD Design Flow www.datasheetarchive.com/files/xilinx/docs/wcd00049/wcd049bc.htm |
Xilinx | 16/02/1999 | 1.49 Kb | HTM | wcd049bc.htm |
| Xilinx: CPLD Implementation Tools - Technical Information CPLD Implementation Tools Announcements Getting Started Top M1.5/i CPLD Solutions Top M1.4 CPLD Solutions CPLD Tips and Techniques Software Patches Contacting Xilinx Support www.datasheetarchive.com/files/xilinx/docs/rp00001/rp00109.htm |
Xilinx | 29/02/2000 | 3.41 Kb | HTM | rp00109.htm |
| */ /* Flash status bit enumerations */ typedef enum {CPLD_STS1, CPLD_STS2} CPLD_FLASH_STS_T; /* Possible } CPLD_LED_TYPE; /* CPLD GPIO data direction control */ typedef enum { CPLD_GPIO_OUTPUT, /* GPIO configured as output */ CPLD_GPIO_INPUT /* GPIO configured as input */ } CPLD_GPIO_DIR_T */ /* Initializes the CPLD driver */ void cpld_init(void); /* Enable or disable LAN power */ void cpld_enable_lan_power(BOOL _32 cpld_ts_int_pending(void); /* Return CPLD interrupt pending status */ BOOL_32 cpld_int_pending(void www.datasheetarchive.com/download/84634965-595970ZC/code.package.lh7a400.sdk7a400.zip (sdk7a400_cpld_driver.h) |
NXP | 06/09/2007 | 4239.75 Kb | ZIP | code.package.lh7a400.sdk7a400.zip |
| */ /* Initialize the CPLD interrupt interface */ void cpld_int_router_init(void); /* Enable or disable CPLD router interrupt */ void cpld_int_router_enable(BOOL_32 enable); /* CPLD interrupt router */ void cpld_int_router_isr(void); #ifdef _cplusplus } #endif #endif /* SDK7A400 SDK7A400 SDK7A400 SDK7A400_CPLD_INT_ROUTER_H */ /* * $Id: sdk7a400_cpld_int_router.h . */ #ifndef SDK7A400 SDK7A400 SDK7A400 SDK7A400_CPLD_INT_ROUTER_H #define SDK7A400 SDK7A400 SDK7A400 SDK7A400_CPLD_INT_ROUTER_H #ifdef _cplusplus extern "C www.datasheetarchive.com/download/84634965-595970ZC/code.package.lh7a400.sdk7a400.zip (sdk7a400_cpld_int_router.h) |
NXP | 06/09/2007 | 4239.75 Kb | ZIP | code.package.lh7a400.sdk7a400.zip |
| Xilinx Answer #3008 : CPLD: CPLD command-line does not support reading PART attribute from -> Answers Database CPLD: CPLD command-line does not support reading PART attribute from netlist. Record #3008 Product Family: Software Product Line: EPLD Core Problem Title: CPLD: CPLD command-line does not support reading PART attribute from netlist. Problem Description: Keywords: CPLD, PART, indesign Urgency: standard General description: The "cpld" command is www.datasheetarchive.com/files/xilinx/docs/wcd00009/wcd009d2-v1.htm |
Xilinx | 16/02/1999 | 3.95 Kb | HTM | wcd009d2-v1.htm |
| Xilinx Answer #3008 : CPLD: CPLD command-line does not support reading PART attribute from -> Answers Database CPLD: CPLD command-line does not support reading PART attribute from netlist. Record #3008 Product Family: Software Product Line: EPLD Core Problem Title: CPLD: CPLD command-line does not support reading PART attribute from netlist. Problem Description: Keywords: CPLD, PART, indesign Urgency: standard General description: The "cpld" command is www.datasheetarchive.com/files/xilinx/docs/wcd00009/wcd009a0.htm |
Xilinx | 17/07/1998 | 3.85 Kb | HTM | wcd009a0.htm |
| */ CPLD_GPIO_BITS_3 /* CPLD GPIO bit 3 */ } CPLD_GPIO_BITS_T; /* CPLD GPIO data direction control */ typedef enum {CPLD_GPIO_OUTPUT, CPLD_GPIO_INPUT} CPLD_GPIO_DIR_T */ /* Flash status bit enumerations */ typedef enum {CPLD_STS1, CPLD_STS2} CPLD_FLASH_STS_T; /* CPLD GPIO */ /* Initializes the CPLD driver */ void cpld_init(void); /* Enable or disable LAN power */ void cpld_enable_lan_power(BOOL */ void cpld_enable_led(BOOL_32 set); /* Set direction of CPLD GPIO data register */ void cpld_set_gpio_dir(CPLD_GPIO_BITS_T www.datasheetarchive.com/download/36663282-595971ZC/code.package.lh7a404.sdk7a404.zip (sdk7a404_cpld_driver.h) |
NXP | 06/09/2007 | 4752.97 Kb | ZIP | code.package.lh7a404.sdk7a404.zip |
| XC9500 XC9500 XC9500 XC9500 CPLDs Press Kit XC9500 XC9500 XC9500 XC9500 CPLDs Press Releases Xilinx Announces Newest Member of Industry's Fastest Growing CPLD Family - May 6, 1998 [ HTML | PDF ] Xilinx Announces Smallest Packaging Technology for CPLDs in Small Form CPLD Family - August 6, 1997 [ HTML | PDF ] White Paper www.datasheetarchive.com/files/xilinx/docs/rp00028/rp028dc.htm |
Xilinx | 29/02/2000 | 5.17 Kb | HTM | rp028dc.htm |