CP3UB17 CR16C DS131 CSP-48 LQFP-100 CP3UB17G38 CP3UB17K38 PG0/RXD/WUI10 - Datasheet Archive

 

CP3UB17 Reprogrammable Connectivity Processor with USB Interface 1.0 General Description The CP3UB17 connectivity processor

 

Sept. 2003 CP3UB17 CP3UB17 Reprogrammable Connectivity Processor with USB Interface 1.0 General Description The CP3UB17 CP3UB17 connectivity processor combines a powerful RISC core with on-chip SRAM and Flash memory for high computing bandwidth, hardware communications peripherals for high I/O bandwidth, and an external bus for system expandability. On-chip communications peripherals include: USB controller, ACCESS.bus, Microwire/Plus, SPI, UART, and Advanced Audio Interface (AAI). Additional on-chip peripherals include DMA controller, PCM/CSVD conversion module, Timing and Watchdog Unit, Versatile Timer Unit, MultiFunction Timer, and Multi-Input Wakeup. The CP3UB17 CP3UB17 is backed up by the software resources designers need for rapid time-to-market, including an operating system, peripheral drivers, reference designs, and an integrated development environment. National Semiconductor offers a complete and industryproven application development environment for CP3UB17 CP3UB17 applications, including the IAR Embedded Workbench, iSYSTEM winIDEA and iC3000 Active Emulator, Development Board, and Application Software. Block Diagram Clock Generator 12 MHz and 32 kHz Oscillator PLL and Clock Generator Power-on-Reset 256K Bytes Flash Program Memory CR16C CR16C CPU Core 8K Bytes Flash Data 10K Bytes Static RAM Serial Debug Interface CPU Core Bus Bus Interface Unit DMA Controller Peripheral Bus Controller Interrupt Control Unit Power Management CVSD/PCM Timing and Watchdog Unit Peripheral Bus USB GPIO Audio Interface Microwire/ SPI UART ACCESS .bus Versatile Timer Unit Muti-Function Timer Multi-Input Wake-Up DS131 DS131 TRI-STATE is a registered trademark of National Semiconductor Corporation. ©2003 National Semiconductor Corporation www.national.com CP3UB17 CP3UB17 Connectivity Processor with USB Interface PRELIMINARY CP3UB17 CP3UB17 Table of Contents 1.0 2.0 3.0 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 1 CPU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 3.20 4.0 6.0 Module Configuration Register (MCFG) . . . . . . . . . . . . 29 Module Status Register (MSTAT) . . . . . . . . . . . . . . . . . 29 Flash Memory Protection . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Organization . . . . . . . . . . . . . . . . . . . . . Flash Memory Operations. . . . . . . . . . . . . . . . . . . . . . . Information Block Words. . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Interface Registers . . . . . . . . . . . . . . . . 22.0 Channel Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software DMA Request . . . . . . . . . . . . . . . . . . . . . . . . Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Controller Register Set. . . . . . . . . . . . . . . . . . . . . 23.0 Non-Maskable Interrupts. . . . . . . . . . . . . . . . . . . . . . . . Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Controller Registers . . . . . . . . . . . . . . . . . . . . Maskable Interrupt Sources . . . . . . . . . . . . . . . . . . . . . Nested Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 46 46 48 49 External Crystal Network . . . . . . . . . . . . . . . . . . . . . . . Main Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slow Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auxiliary Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock and Reset Registers . . . . . . . . . . . . . . . . . . . . . . 51 51 52 52 52 52 52 52 53 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Save Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Registers . . . . . . . . . . . . . . . . . . . Switching Between Power Modes. . . . . . . . . . . . . . . . . 55 55 55 55 56 56 57 27.0 28.0 29.0 Multi-Input Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . 59 Multi-Input Wake-Up Registers . . . . . . . . . . . . . . . . . . . 59 Programming Procedures . . . . . . . . . . . . . . . . . . . . . . . 61 Input/Output Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . 62 14.1 14.2 Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Open-Drain Operation. . . . . . . . . . . . . . . . . . . . . . . . . . 65 www.national.com 2 Microwire Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . Microwire Interface Registers . . . . . . . . . . . . . . . . . . . 116 118 119 119 119 ACB Protocol Overview . . . . . . . . . . . . . . . . . . . . . . . . ACB Functional Description . . . . . . . . . . . . . . . . . . . . . ACCESS.bus Interface Registers . . . . . . . . . . . . . . . . Usage Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 124 126 130 TWM Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer T0 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Operation . . . . . . . . . . . . . . . . . . . . . . . . . . TWM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Programming Procedure. . . . . . . . . . . . . . . 131 131 132 132 134 Timer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 136 140 140 141 VTU Functional Description . . . . . . . . . . . . . . . . . . . . . 144 VTU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 172 26.1 26.2 26.3 26.4 26.5 26.6 26.7 26.8 26.9 26.10 26.11 26.12 26.13 26.14 26.15 Triple Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . 50 106 106 110 114 Versatile Timer Unit (VTU) . . . . . . . . . . . . . . . . . . . . 144 23.1 23.2 24.0 25.0 26.0 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . UART Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baud Rate Calculations . . . . . . . . . . . . . . . . . . . . . . . . Multi-Function Timer . . . . . . . . . . . . . . . . . . . . . . . . 135 22.1 22.2 22.3 22.4 22.5 40 40 41 42 42 42 101 101 102 102 102 102 102 103 103 Timing and Watchdog Module . . . . . . . . . . . . . . . . 131 21.1 21.2 21.3 21.4 21.5 30 30 31 32 34 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCM Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . CVSD Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCM to CVSD Conversion. . . . . . . . . . . . . . . . . . . . . . CVSD to PCM Conversion. . . . . . . . . . . . . . . . . . . . . . Interrupt Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CVSD/PCM Converter Registers . . . . . . . . . . . . . . . . . ACCESS.bus Interface . . . . . . . . . . . . . . . . . . . . . . . 122 20.1 20.2 20.3 20.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 13.1 13.2 14.0 Operating Environment . . . . . . . . . . . . . . . . . . . . . . . . . Bus Interface Unit (BIU) . . . . . . . . . . . . . . . . . . . . . . . . Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIU Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . Wait and Hold States . . . . . . . . . . . . . . . . . . . . . . . . . . 86 86 89 89 89 91 94 Microwire/SPI Interface . . . . . . . . . . . . . . . . . . . . . . 116 19.1 19.2 19.3 19.4 19.5 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 12.1 12.2 12.3 12.4 12.5 12.6 12.7 13.0 19.0 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 12.0 16 16 17 18 19 20 20 21.0 10.1 10.2 10.3 10.4 10.5 11.0 General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . Dedicated Address Registers . . . . . . . . . . . . . . . . . . . . Processor Status Register (PSR) . . . . . . . . . . . . . . . . . Configuration Register (CFG) . . . . . . . . . . . . . . . . . . . . Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Audio Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . Audio Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . Frame Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . Audio Interface Operation . . . . . . . . . . . . . . . . . . . . . . . Communication Options. . . . . . . . . . . . . . . . . . . . . . . . . Audio Interface Registers. . . . . . . . . . . . . . . . . . . . . . . . UART Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 18.1 18.2 18.3 18.4 System Configuration Registers . . . . . . . . . . . . . . . 29 9.1 9.2 9.3 9.4 9.5 9.6 10.0 18.0 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 66 68 70 85 CVSD/PCM Conversion Module . . . . . . . . . . . . . . . 101 17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8 17.9 20.0 8.1 8.2 8.3 8.4 8.5 9.0 17.0 Functional States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endpoint Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Controller Registers. . . . . . . . . . . . . . . . . . . . . . . . Transceiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Audio Interface . . . . . . . . . . . . . . . . . . . . . 86 16.1 16.2 16.3 16.4 16.5 16.6 16.7 25 25 26 26 28 7.1 7.2 8.0 16.0 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1 6.2 6.3 6.4 6.5 7.0 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 6 6 6 6 6 CPU Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 5.2 5.3 5.4 5.5 5.6 5.7 USB Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 15.1 15.2 15.3 15.4 Device Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 5.0 CR16C CR16C CPU Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Control Unit (ICU) . . . . . . . . . . . . . . . . . . . . . . . USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-Input Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . Triple Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-Function Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . Versatile Timer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing and Watchdog Module . . . . . . . . . . . . . . . . . . . . UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microwire/SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACCESS.bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . DMA CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Audio interface . . . . . . . . . . . . . . . . . . . . . . . . CVSD/PCM Conversion Module . . . . . . . . . . . . . . . . . . . Serial Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.0 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . USB Transceiver Electrical Characteristics . . . . . . . . . Flash Memory On-Chip Programming . . . . . . . . . . . . . Output Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . Clock and Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Port Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Audio Interface (AAI) Timing. . . . . . . . . . . . Microwire/SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . ACCESS.bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . USB Port AC Characteristics . . . . . . . . . . . . . . . . . . . . Multi-Function Timer (MFT) Timing . . . . . . . . . . . . . . . Versatile Timing Unit (VTU) Timing . . . . . . . . . . . . . . . External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 172 172 173 174 175 175 177 178 179 181 186 189 189 190 191 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 199 CPU Features CPU Features Flexible I/O Fully static RISC processor core, capable of operating from 0 to 24 MHz with zero wait/hold states Minimum 41.7 ns instruction cycle time with a 24-MHz internal clock frequency, based on a 12-MHz external input 30 independently vectored peripheral interrupts Up to 37 general-purpose I/O pins (shared with on-chip peripheral I/O pins) Programmable I/O pin characteristics: TRI-STATE output, push-pull output, weak pull-up input, high-impedance input Schmitt triggers on general purpose inputs Multi-Input Wakeup On-Chip Memory 256K bytes reprogrammable Flash program memory 8K bytes Flash data memory 10K bytes of static RAM data memory Addresses up to 8 Mbytes of external memory Extensive Power and Clock Management Support On-chip Phase Locked Loop Support for multiple clock options Dual clock and reset Power-down modes Broad Range of Hardware Communications Peripherals Full-speed USB node including seven Endpoint-FIFOs Power Supply conforming to USB 1.1 specification 2 ACCESS.bus serial bus (compatible with Philips I C bus) I/O port operation at 2.5V to 3.3V 8/16-bit SPI, Microwire/Plus serial interface Core logic operation at 2.5V Universal Asynchronous Receiver/Transmitter (UART) On-chip power-on reset Advanced Audio Interface (AAI) to connect to external 8/ Temperature Range 13-bit PCM Codecs as well as to ISDN-Controllers -40°C to +85°C (Industrial) through the IOM-2 interface (slave only) PCM/CVSD converter supporting one bidirectional audio Packages connection CSP-48 CSP-48, LQFP-100 LQFP-100 General-Purpose Hardware Peripherals Complete Development Environment Dual 16-bit Multi-Function Timer Pre-integrated hardware and software support for rapid Versatile Timer Unit with four subsystems (VTU) prototyping and production Four channel DMA controller Integrated environment Timing and Watchdog Unit Project manager Multi-file C source editor CP3UB17 CP3UB17 Connectivity Processor Selection Guide NSID Speed (MHz) Temp. Range Program Flash (kBytes) Data Flash (kBytes) SRAM (kBytes) External Address Lines I/Os Package Type CP3UB17G38 CP3UB17G38 24 -40° to +85°C 256 8 10 22 37 LQFP-100 LQFP-100 CP3UB17K38 CP3UB17K38 24 -40° to +85°C 256 8 10 0 21 CSP-48 CSP-48 3 www.national.com CP3UB17 CP3UB17 2.0 CP3UB17 CP3UB17 3.0 Device Overview The CP3UB17 CP3UB17 connectivity processor is a complete microcomputers with all system timing, interrupt logic, program memory, data memory, I/O ports included on-chip, making them well-suited to a wide range of embedded applications. The block diagram on page 1 shows the major on-chip components of the CP3UB17 CP3UB17. The I/O pin characteristics are fully programmable. Each pin can be configured to operate as a TRI-STATE output, pushpull output, weak pull-up input, or high-impedance input. For more information, please refer to the CR16C CR16C Programmer's Reference Manual (document number 424521772101, which may be downloaded from National's web site at http://www.national.com). possible memory access. To achieve fastest possible program execution, appropriate values must be programmed. These settings vary with the clock frequency and the type of off-chip device being accessed. 3.2 3.5 3.4 BUS INTERFACE UNIT The Bus Interface Unit (BIU) controls access to internal/external memory and I/O. It determines the configured param3.1 CR16C CR16C CPU CORE eters for bus access (such as the number of wait states for The CP3UB17 CP3UB17 implements the CR16C CR16C CPU core module. memory access) and issues the appropriate bus signals for The high performance of the CPU core results from the im- each requested access. plementation of a pipelined architecture with a two-bytes- The BIU uses a set of control registers to determine how per-cycle pipelined system bus. As a result, the CPU can many wait states and hold states are used when accessing support a peak execution rate of one instruction per clock Flash program memory, and the I/O area (Port B and Port cycle. C). At start-up, the configuration registers are set for slowest MEMORY The CP3UB17 CP3UB17 supports a uniform linear address space of up to 16 megabytes. Three types of on-chip memory occupy specific regions within this address space: INTERRUPT CONTROL UNIT (ICU) The ICU receives interrupt requests from internal and external sources and generates interrupts to the CPU. An interrupt is an event that temporarily stops the normal flow of program execution and causes a separate interrupt handler to be executed. After the interrupt is serviced, CPU execution continues with the next instruction in the program following the point of interruption. 256K bytes of Flash program memory 8K bytes of Flash data memory 10K bytes of static RAM Up to 8M bytes of external memory (100-pin devices ) Interrupts from the timers, UART, Microwire/SPI interface, and Multi-Input Wake-Up, are all maskable interrupts; they can be enabled or disabled by software. There are 32 of these maskable interrupts, assigned to 32 linear priority levels. The 256K bytes of Flash program memory are used to store the application program and real-time operating system. The Flash memory has security features to prevent unintentional programming and to prevent unauthorized access to the program code. This memory can be programmed with an external programming unit or with the device installed in the application system (in-system programming). The highest-priority interrupt is the Non-Maskable Interrupt (NMI), which is generated by a signal received on the NMI input pin. The 8K bytes of Flash data memory are used for non-volatile storage of data entered by the end-user, such as config- 3.6 USB uration settings. The USB node is a Universal Serial Bus (USB) Node conThe 10K bytes of static RAM are used for temporary storage troller compatible with USB Specification, 1.0 and 1.1. It inof data and for the program stack and interrupt stack. Read tegrates the required USB transceiver, the Serial Interface and write operations can be byte-wide or word-wide, de- Engine (SIE), and USB endpoint FIFOs. A total of seven pending on the instruction executed by the CPU. endpoint pipes are supported: one bidirectional pipe for the Up to 8M bytes of external memory can be added on an ex- mandatory control EP0 and an additional six pipes for uniditernal bus. The external bus is only available on devices in rectional endpoints to support USB interrupt, bulk, and isochronous data transfers. 100-pin packages. For Flash program and data memory, the device internally generates the necessary voltages for programming. No additional power supply is required. 3.3 3.7 The Multi-Input Wake-Up (MIWU) module can be used for either of two purposes: to provide inputs for waking up (exiting) from the Halt, Idle, or Power Save mode; or to provide general-purpose edge-triggered maskable interrupts from external sources. This 16-channel module generates four programmable interrupts to the CPU based on the signals received on its 16 input channels. Channels can be individually enabled or disabled, and programmed to respond to positive or negative edges. INPUT/OUTPUT PORTS The device has up to 37 software-configurable I/O pins, organized into five ports called Port B, Port C, Port G, Port H, and Port I. Each pin can be configured to operate as a general-purpose input or general-purpose output. In addition, many I/O pins can be configured to operate as inputs or outputs for on-chip peripheral modules such as the UART, timers, or Microwire/SPI interface. www.national.com MULTI-INPUT WAKE-UP 4 TRIPLE CLOCK AND RESET Dual Independent Timer mode-Generates system timing signals or counts occurrences of external events. Single Input Capture and Single Timer mode-Provides one external event counter and one system timer. The Triple Clock and Reset module generates a high-speed main System Clock from an external crystal network. It also provides the main system reset signal and a power-on reset function. 3.11 VERSATILE TIMER UNIT This module generates a slow System Clock (32.768 kHz) The Versatile Timer Unit (VTU) module contains four indefrom an optional external crystal network. The Slow Clock is pendent timer subsystems, each operating in either dual 8used for operating the device in power-save mode. The bit PWM configuration, as a single 16-bit PWM timer, or a 32.768 kHz external crystal network is optional, because 16-bit counter with two input capture channels. Each of the the low speed System Clock can be derived from the high- four timer subsystems offer an 8-bit clock prescaler to acspeed clock by a prescaler. commodate a wide range of frequencies. Also, two independent clocks divided down from the high 3.12 TIMING AND WATCHDOG MODULE speed clock are available on output pins. The Timing and Watchdog Module (TWM) contains a RealThe Triple Clock and Reset module provides the clock sigTime timer and a Watchdog unit. The Real-Time Clock Timnals required for the operation of the various CP3UB17 CP3UB17 oning function can be used to generate periodic real-time chip modules. From external crystal networks, it generates based system interrupts. The timer output is one of 16 inthe Main Clock, which can be scaled up to 24 MHz from an puts to the Multi-Input-Wake-Up module which can be used external 12 MHz input clock, and a 32.768 kHz secondary to exit from a power-saving mode. The Watchdog unit is deSystem Clock. The 12 MHz external clock is primarily used signed to detect the application program getting stuck in an as the reference frequency for the on-chip PLL. Also the infinite loop resulting in loss of program control or "runaway" clock for modules which require a fixed clock rate (e.g. the programs. When the watchdog triggers, it resets the device. PCM/CVSD transcoder) is generated through prescalers The TWM is clocked by the low-speed System Clock. from the 12 MHz clock. The PLL generates the input clock for the USB node and may be used to drive the high-speed 3.13 UART System Clock through a prescaler. Alternatively, the high The UART supports a wide range of programmable baud speed System Clock can be derived directly from the 12 rates and data formats, parity generation, and several error MHz Main Clock. detection schemes. The baud rate is generated on-chip, unIn addition, this module generates the device reset by using der software control. reset input signals coming from an external reset and variThe UART offers a wake-up condition from the power-save ous on-chip modules. mode using the Multi-Input Wake-Up module. 3.9 POWER MANAGEMENT 3.14 The Power Management Module (PMM) improves the efficiency of the device by changing the operating mode and power consumption to match the required level of activity. The Microwire/SPI (MWSPI) interface module supports synchronous serial communications with other devices that conform to Microwire or Serial Peripheral Interface (SPI) specifications. It supports 8-bit and 16-bit data transfers. The device can operate in any of four power modes: Active-The device operates at full speed using the highfrequency clock. All device functions are fully operational. Power Save-The device operates at reduced speed using the Slow Clock. The CPU and some modules can continue to operate at this low speed. Idle-The device is inactive except for the Power Management Module and Timing and Watchdog Module, which continue to operate using the Slow Clock. Halt-The device is inactive but still retains its internal state (RAM and register contents). 3.10 MICROWIRE/SPI The Microwire interface allows several devices to communicate over a single system consisting of four wires: serial in, serial out, shift clock, and slave enable. At any given time, the Microwire interface operates as the master or a slave. The Microwire interface supports the full set of slave select for multi-slave implementation. In master mode, the shift clock is generated on chip under software control. In slave mode, a wake-up out of powersave mode is triggered using the Multi-Input Wake-Up module. 3.15 MULTI-FUNCTION TIMER ACCESS.BUS INTERFACE The ACCESS.bus interface module (ACB) is a two-wire seThe Multi-Function Timer (MFT) module contains a pair of rial interface with the ACCESS.bus physical layer. It is also 16-bit timer/counter registers. Each timer/counter unit can compatible with Intel's System Management Bus (SMBus) be configured to operate in any of the following modes: and Philips' I2C bus. The ACB module can be configured as Processor-Independent Pulse Width Modulation (PWM) a bus master or slave, and can maintain bidirectional commode-Generates pulses of a specified width and duty munications with both multiple master and slave devices. cycle and provides a general-purpose timer/counter. The ACCESS.bus receiver can trigger a wake-up condition Dual Input Capture mode-Measures the elapsed time out of the low-power modes using the Multi-Input Wake-Up between occurrences of external event and provides a module. general-purpose timer/counter. 5 www.national.com CP3UB17 CP3UB17 3.8 CP3UB17 CP3UB17 3.16 DMA CONTROLLER 3.18 CVSD/PCM CONVERSION MODULE The CVSD/PCM module performs conversion between CVSD data and PCM data, in which the PCM data can be 8-bit µ-Law, 8-bit A-Law, or 13-bit to 16-bit Linear. The Direct Memory Access Controller (DMAC) can speed up data transfer between memory and I/O devices or between two memories, relative to data transfers performed directly by the CPU. A method called cycle-stealing allows the CPU and the DMAC to use the core bus in parallel. The DMAC implements four independent DMA channels. DMA requests from a primary and a secondary source are recognized for each DMA channel, as well as a software DMA request issued directly by the CPU. Table 1 shows the DMA channel assignment on the CP3UB17 CP3UB17 architecture. The following on-chip modules can assert a DMA request to the DMAC: 3.19 SERIAL DEBUG INTERFACE The Serial Debug Interface module (SDI module)provides a JTAG-based serial link to an external debugger, for example running on a PC. In addition, the SDI module integrates an on-chip debug module, which allows the user to set up to four hardware breakpoints on instruction execution and data transfer. The SDI module can act as a CPU bus master to access all memory mapped resources, such as RAM and peripherals. Therefore it also allows for fast program code download into the on-chip Flash program memory using the JTAG interface. CR16C CR16C (Software DMA request) USB UART Advanced Audio Interface PCM/CVSD Converter 3.20 DEVELOPMENT SUPPORT The CP3UB17 CP3UB17 is backed up by the software resources designers need for rapid time-to-market, including an operatTable 1 shows how the four DMA channels are assigned ing system, peripheral drivers, reference designs, and an integrated development environment. to the modules listed above. National Semiconductor offers a complete and industryTable 1 DMA Channel Assignment proven application development environment for CP3UB17 CP3UB17 applications, including the IAR Embedded Workbench, Primary/ Channel Peripheral Transaction iSYSTEM winIDEA and iC3000 Active Emulator, DevelopSecondary ment Board, and Application Software. See your National Semiconductor sales representative for current information Primary USB Read/Write on availability and features of emulation equipment and 0 Secondary UART Read evaluation boards. Primary UART Write Secondary Unused N/A Primary AAI Read Secondary CVSD/PCM Read Primary AAI Write Secondary CVSD/PCM Write 1 2 3 3.17 ADVANCED AUDIO INTERFACE The audio interface provides a serial synchronous, full-duplex interface to CODECs and similar serial devices. Transmit and receive paths operate asynchronously with respect to each other. Each path uses three signals for communication: shift clock, frame synchronization, and data. In case receive and transmit use separate shift clocks and frame sync signals, the interface operates in its asynchronous mode. Alternatively, the transmit and receive path can share the same shift clock and frame sync signals for synchronous mode operation. The interface can handle data words of either 8- or 16-bit length and data frames can consist of up to four slots. In the normal mode of operation, the interface only transfers one word at a periodic rate. In the network mode, the interface transfers multiple words at a periodic rate. The periodic rate is also called a data frame and each word within one frame is called a slot. The beginning of each new data frame is marked by the frame sync signal. www.national.com 6 CP3UB17 CP3UB17 4.0 Device Pinouts X2CKI X2CKO 32.768 kHz Crystal Power Supply PB[7:0] PC[7:0] A[21:0] SEL0 SEL1 SEL2 SELIO WR0 WR1 RD X1CKI X1CKO 12 MHz Crystal or Ext. Clock 2 4 6 AVCC AGND VCC IOVCC GND 8 D+ X1CKI 12 MHz Crystal or Ext. Clock 8 D- X1CKO UVCC 22 External Bus Interface 32.768 kHz Crystal/ X2CKI PI0 X2CKO PI1 AVCC Power Supply CP3UB17 CP3UB17 (LQFP-100 LQFP-100) 2 2 4 PI3 AGND RESET PI0 PI1 PI3 PI4 PI5 JTAG I/F to Debugger/ Programmer ACCESS.bus TMS TDI TDO TCK RDY SDA SCL Chip Reset VCC IOVCC GND PI5 CP3UB17 CP3UB17 (CSP-48 CSP-48) PI6/WUI9 PI7/TA PG0/RXD/WUI10 PG0/RXD/WUI10 PG1/TXD/WUI11 PG1/TXD/WUI11 PG2/RTS/WUI12 PG2/RTS/WUI12 PG3/CTS/WUI13 PG3/CTS/WUI13 PG1/TXD/WUI11 PG1/TXD/WUI11 GPIO PG2/RTS/WUI12 PG2/RTS/WUI12 USB Mode Selection D+ DUVCC UGND ENV0 ENV1 ENV2 MFT UART/ MIWU PG3/CTS/WUI13 PG3/CTS/WUI13 PH0/MSK/TIO1 MIWU PH2/MDODI/TIO3 TMS JTAG I/F to Debugger/ Programmer MFT PH4/SCK/TIO5 TCK PH5/SFS/TIO6 RDY UART/ MIWU MICROWIRE/ SPI/ VTU PH3/MWCS/TIO4 TDI TDO PH6/STD/TIO7 ENV0 PG5/SRFS/NMI AAI/ VTU PH7/SRD/TIO8 Mode Selection AAI/NMI ENV1 PI2/SRCLK PH0/MSK/TIO1 PH1/MDIDO/TIO2 PH2/MDODI/TIO3 PH3/MWCS/TIO4 MIWU PG0/RXD/WUI10 PG0/RXD/WUI10 RESET PH1/MDIDO/TIO2 PI6/WUI9 GPIO PI4 PI7/TA Chip Reset USB UGND AAI MICROWIRE/ SPI/ VTU PH4/SCK/TIO5 PH5/SFS/TIO6 PH6/STD/TIO7 PH7/SRD/TIO8 AAI/ VTU PG5/SRFS/NMI AAI/NMI PI2/SRCLK AAI DS139 DS139 Table 2 Pin Assignments for 100-Pin Package Pin Name Alternate Function(s) Pin Number Type A14 1 O A13 2 O A12 3 O A11 4 O A10 5 O PH6 STD/TIO7 6 GPIO PH7 SRD/TIO8 7 GPIO ENV1 8 I/O A9 9 O A8 10 O A7 11 O A6 12 O A5 13 O 7 www.national.com CP3UB17 CP3UB17 Table 2 Pin Assignments for 100-Pin Package Pin Name Alternate Function(s) Pin Number Type A4 14 O VCC 15 PWR X2CKI 16 I X2CKO 17 O GND 18 PWR AVCC 19 PWR AGND 20 PWR IOVCC 21 PWR X1CKO 22 O X1CKI 23 I GND 24 PWR A3 26 O A2 27 O A1 28 O A0 29 O PI0 30 GPIO PI1 31 GPIO PI2 SRCLK 32 GPIO PB0 D0 33 GPIO PB1 D1 34 GPIO PB2 D2 35 GPIO PB3 D3 36 GPIO PB4 D4 37 GPIO PB5 D5 38 GPIO PB6 D6 39 GPIO PB7 D7 40 GPIO GND 41 PWR IOVCC 42 PWR PI3 43 GPIO PI4 44 GPIO PI5 45 GPIO 46 GPIO PI6 WUI9 PI7 47 GPIO RXD/WUI10 RXD/WUI10 48 GPIO PG1 TXD/WUI11 TXD/WUI11 49 GPIO PC0 D8 50 GPIO PG2 RTS/WUI12 RTS/WUI12 51 GPIO PG3 CTS/WUI13 CTS/WUI13 52 GPIO PC1 D9 53 GPIO PC2 D10 54 GPIO PC3 D11 55 GPIO PC4 D12 56 GPIO PC5 www.national.com TA PG0 D13 57 GPIO 8 Pin Name Alternate Function(s) Pin Number Type PC6 D14 58 GPIO PC7 D15 59 GPIO PG5 SRFS/NMI 60 GPIO 61 I TMS TCK 62 I TDI 63 I GND 64 PWR IOVCC 65 PWR ENV2 66 I/O SEL0 67 O SCL 68 I/O SDA 69 I/O TDO 70 O D- 71 I/O D+ 72 I/O UVCC 73 PWR UGND 74 PWR RDY 75 O SEL1 76 O SEL2 77 O SELIO 78 O A21 79 O A20 80 O PH0 MSK/TIO1 81 GPIO PH1 MDIDO/TIO2 82 GPIO PH2 MDODI/TIO3 83 GPIO PH3 MWCS/TIO4 84 GPIO ENV0 85 I/O IOVCC 86 PWR GND 87 PWR VCC 88 PWR GND 89 PWR RESET 90 I RD 91 O WR0 92 O WR1 93 O A19 94 O A18 95 O A17 96 O A16 97 O A15 98 O 9 www.national.com CP3UB17 CP3UB17 Table 2 Pin Assignments for 100-Pin Package CP3UB17 CP3UB17 Table 2 Pin Assignments for 100-Pin Package Pin Name Alternate Function(s) Pin Number Type PH4 SCK/TIO5 99 GPIO PH5 SFS/TIO6 100 GPIO Note 1: The ENV0, ENV1, ENV2, TCK, TDI, and TMS pins each have a weak pull-up to keep the input from floating. Note 2: The RESET input has a weak pulldown. Note 3: These functions are always enabled, due to the direct low-impedance path to these pins. Table 3 Pin Assignments for 48-Pin Package Pin Name Alternate Function(s) Pin Number Type PH6 STD/TIO7 1 GPIO PH7 SRD/TIO8 2 GPIO ENV1 3 I/O VCC 4 PWR X2CKI 5 I X2CKO 6 O GND 7 PWR AVCC 8 PWR AGND 9 PWR IOVCC 10 PWR X1CKO 11 O X1CKI 12 I GND 13 PWR PI0 15 GPIO PI1 16 GPIO 17 GPIO PI3 18 GPIO PI4 19 GPIO PI5 20 GPIO PI2 SRCLK PI6 WUI9 21 GPIO PI7 TA 22 GPIO PG0 RXD/WUI10 RXD/WUI10 23 GPIO PG1 TXD/WUI11 TXD/WUI11 24 GPIO PG2 RTS/WUI12 RTS/WUI12 25 GPIO PG3 CTS/WUI13 CTS/WUI13 26 GPIO PG5 SRFS/NMI 27 GPIO TMS 28 I TCK 29 I TDI 30 I GND 31 PWR IOVCC 32 PWR TDO 33 O, GPIO D- 34 O, GPIO D+ I/O 36 PWR, I/O UGND www.national.com 35 UVCC 37 PWR, O 10 Alternate Function(s) Type 38 RDY Pin Number O PH0 MSK/TIO1 39 GPIO PH1 MDIDO/TIO2 40 GPIO PH2 MDODI/TIO3 41 GPIO PH3 MWCS/TIO4 42 GPIO ENV0 43 I/O VCC 44 PWR GND 45 PWR RESET 46 I PH4 SCK/TIO5 47 GPIO PH5 SFS/TIO6 48 GPIO Note 1: The ENV0 and ENV1, TCK, TDI and TMS pins each have a weak pull-up to keep the input from floating. Note 2: The RESET input has a weak pulldown. Note 3: These functions are always enabled, due to the direct low-impedance path to these pins. 11 www.national.com CP3UB17 CP3UB17 Pin Name CP3UB17 CP3UB17 4.1 PIN DESCRIPTION Some pins may be enabled as general-purpose I/O-port pins or as alternate functions associated with specific peripherals or interfaces. These pins may be individually con- figured as port pins, even when the associated peripheral or interface is enabled. Table 4 lists the device pins. Table 4 CP3UB17 CP3UB17 Pin Description for the 100-Pin LQFP Package Name Pins I/O Alternate Name Primary Function Alternate Function X1CKI 1 Input 12 MHz Oscillator Input None None X1CKO 1 Output 12 MHz Oscillator Output None None X2CKI 1 Input 32 kHz Oscillator Input None None X2CKO 1 Output 32 kHz Oscillator Output None None AVCC 1 Input PLL Analog Power Supply None None IOVCC 4 Input 2.5V - 3.3V I/O Power Supply None None VCC 2 Input 2.5V Core Logic Power Supply None None GND 6 Input Reference Ground None None AGND 1 Input PLL Analog Ground None None RESET 1 Input Chip general reset None None TMS 1 Input JTAG Test Mode Select (with internal weak pull-up) None None TDI 1 Input JTAG Test Data Input (with internal weak pull-up) None None TDO 1 Output JTAG Test Data Output None None TCK 1 Input JTAG Test Clock Input (with internal weak pull-up) None None RDY 1 Output NEXUS Ready Output None None RXD UART Receive Data Input PG0 1 I/O Generic I/O WUI10 WUI10 Multi-Input Wake-Up Channel 10 TXD UART Transmit Data Output WUI11 WUI11 Multi-Input Wake-Up Channel 11 RTS UART Ready-To-Send Output WUI12 WUI12 Multi-Input Wake-Up Channel 12 CTS UART Clear-To-Send Input WUI13 WUI13 Multi-Input Wake-Up Channel 13 SRFS AAI Receive Frame Sync NMI Non-Maskable Interrupt Input MSK SPI Shift Clock TIO1 Versatile Timer Channel 1 MDIDO SPI Master In Slave Out TIO2 Versatile Timer Channel 2 MDODI SPI Master Out Slave In TIO3 Versatile Timer Channel 3 PG1 PG2 PG3 PG5 PH0 PH1 PH2 1 1 1 1 1 1 1 www.national.com I/O I/O I/O I/O I/O I/O I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O 12 Pins I/O Alternate Name Primary Function Alternate Function MWCS I/O AAI Receive Data Input TIO8 1 Versatile Timer Channel 7 SRD PH7 I/O AAI Transmit Data Output TIO7 1 Versatile Timer Channel 6 STD PH6 I/O AAI Frame Synchronization TIO6 1 Versatile Timer Channel 5 SFS PH5 I/O AAI Clock TIO5 1 I/O Versatile Timer Channel 4 SCK PH4 1 SPI Slave Select Input TIO4 PH3 Versatile Timer Channel 8 Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O PI0 1 I/O Generic I/O None None PI1 1 I/O Generic I/O None None PI2 1 I/O Generic I/O SRCLK AAI Receive Clock PI3 1 I/O Generic I/O None None PI4 1 I/O Generic I/O None None PI5 1 I/O Generic I/O None None PI6 1 I/O Generic I/O WUI9 Multi-Input Wake-Up Channel 9 PI7 1 I/O Generic I/O TA Multi Function Timer Port A SDA 1 I/O ACCESS.bus Serial Data None None SCL 1 I/O ACCESS.bus Clock None None D+ 1 I/O USB D+ Upstream Port None None D- 1 I/O USB D- Upstream Port None None UVCC 1 Input 3.3V USB Transceiver Supply None None UGND 1 Input USB Transceiver Ground None None PB[7:0] 8 I/O Generic I/O D[7:0] External Data Bus Bit 0 to 7 PC[7:0] 8 I/O Generic I/O D[15:8] External Data Bus Bit 8 to 15 A[21:0] 22 Output External Address Bus Bit 0 to 21 None None SEL0 1 Output Chip Select for Zone 0 None None SEL1 1 Output Chip Select for Zone 1 None None SEL2 1 Output Chip Select for Zone 2 None None SELIO 1 Output Chip Select for Zone I/O Zone None None WR0 1 Output External Memory Write Low Byte None None WR1 1 Output External Memory Write High Byte None None RD 1 Output External Memory Read None None ENV0 1 I/O Special mode select input with internal pull-up during reset PLLCLK PLL Clock Output 13 www.national.com CP3UB17 CP3UB17 Name CP3UB17 CP3UB17 Name Pins I/O Alternate Name Primary Function Alternate Function ENV1 1 I/O Special mode select input with internal pull-up during reset CPUCLK CPU Clock Output ENV2 1 I/O Special mode select input with internal pull-up during reset SLOWCLK Slow Clock Output Table 5 CP3UB17 CP3UB17 Pin Description for the 48-Pin CSP Name Pins I/O Alternate Name Primary Function Alternate Function X1CKI 1 Input 12 MHz Oscillator Input None None X1CKO 1 Output 12 MHz Oscillator Output None None X2CKI 1 Input 32 kHz Oscillator Input None None X2CKO 1 Output 32 kHz Oscillator Output None None AVCC 1 Input PLL Analog Power Supply None None IOVCC 2 Input 2.5V - 3.3V I/O Power Supply None None VCC 2 Input 2.5V Core Logic Power Supply None None GND 4 Input Reference Ground None None AGND 1 Input PLL Analog Ground None None RESET 1 Input Chip general reset None None TMS 1 Input JTAG Test Mode Select (with internal weak pull-up) None None TDI 1 Input JTAG Test Data Input (with internal weak pull-up) None None TDO 1 Output JTAG Test Data Output None None TCK 1 Input JTAG Test Clock Input (with internal weak pull-up) None None RDY 1 Output NEXUS Ready Output None None RXD UART Receive Data Input PG0 1 I/O Generic I/O WUI10 WUI10 Multi-Input Wake-Up Channel 10 TXD UART Transmit Data Output WUI11 WUI11 Multi-Input Wake-Up Channel 11 RTS UART Ready-To-Send Output WUI12 WUI12 Multi-Input Wake-Up Channel 12 CTS UART Clear-To-Send Input WUI13 WUI13 Multi-Input Wake-Up Channel 13 SRFS AAI Receive Frame Sync NMI Non-Maskable Interrupt Input MSK SPI Shift Clock TIO1 Versatile Timer Channel 1 MDIDO SPI Master In Slave Out TIO2 Versatile Timer Channel 2 PG1 PG2 PG3 PG5 PH0 PH1 1 1 1 1 1 1 www.national.com I/O I/O I/O I/O I/O I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O 14 Pins I/O Alternate Name Primary Function Alternate Function MDODI I/O AAI Receive Data Input TIO8 1 Versatile Timer Channel 7 SRD PH7 I/O AAI Transmit Data Output TIO7 1 Versatile Timer Channel 6 STD PH6 I/O AAI Frame Synchronization TIO6 1 Versatile Timer Channel 5 SFS PH5 I/O AAI Clock TIO5 1 Versatile Timer Channel 4 SCK PH4 I/O SPI Slave Select Input TIO4 1 I/O Versatile Timer Channel 3 MWCS PH3 1 SPI Master Out Slave In TIO3 PH2 Versatile Timer Channel 8 Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O PI0 1 I/O Generic I/O None None PI1 1 I/O Generic I/O None None PI2 1 I/O Generic I/O SRCLK AAI Receive Clock PI3 1 I/O Generic I/O None None PI4 1 I/O Generic I/O None None PI5 1 I/O Generic I/O None None PI6 1 I/O Generic I/O WUI9 Multi-Input Wake-Up Channel 9 PI7 1 I/O Generic I/O TA Multi Function Timer Port A D+ 1 I/O USB D+ Upstream Port None None D- 1 I/O USB D- Upstream Port None None UVCC 1 Input 3.3V USB Transceiver Supply None None UGND 1 Input USB Transceiver Ground None None SDA 1 I/O ACCESS.bus Serial Data None None SCL 1 I/O ACCESS.bus Clock None None ENV0 1 I/O Special mode select input with internal pull-up during reset PLLCLK PLL Clock Output ENV1 1 I/O Special mode select input with internal pull-up during reset CPUCLK CPU Clock Output 15 www.national.com CP3UB17 CP3UB17 Name CP3UB17 CP3UB17 5.0 CPU Architecture The CP3UB17 CP3UB17 uses the CR16C CR16C third-generation 16-bit When the CFG.SR bit is clear, register pairs are grouped CompactRISC processor core. The CPU implements a Rein the manner used by native CR16C CR16C software: (R1,R0), duced Instruction Set Computer (RISC) architecture that al(R2,R1) . (R11,R10), (R12_L, R11), R12, R13, RA, SP. lows an effective execution rate of up to one instruction per R12, R13, RA, and SP are 32-bit registers for holding adclock cycle. For a detailed description of the CPU16C CPU16C archidresses greater than 16 bits. tecture, see the CompactRISC CR16C CR16C Programmer's Ref- With the recommended calling convention for the architecerence Manual which is available on the National ture, some of these registers are assigned special hardware Semiconductor web site (http://www.nsc.com). and software functions. Registers R0 to R13 are for generalThe CR16C CR16C CPU core includes these internal registers: purpose use, such as holding variables, addresses, or index values. The SP register holds a pointer to the program runGeneral-purpose registers (R0-R13 R0-R13, RA, and SP) Dedicated address registers (PC, ISP, USP, and INT- time stack. The RA register holds a subroutine return address. The R12 and R13 registers are available to hold base BASE) addresses used in the index addressing mode. Processor Status Register (PSR) Configuration Register (CFG) The R0-R11 R0-R11, PSR, and CFG registers are 16 bits wide. The R12, R13, RA, SP, ISP and USP registers are 32 bits wide. The PC register is 24 bits wide. Figure 1 shows the CPU registers. Dedicated Address Registers 15 0 23 31 PC ISPH ISPL USPH USPL INTBASEH INTBASEL If a general-purpose register is specified by an operation that is 8 bits long, only the lower byte of the register is used; the upper part is not referenced or modified. Similarly, for word operations on register pairs, only the lower word is used. The upper word is not referenced or modified. 5.2 General-Purpose Registers 15 0 DEDICATED ADDRESS REGISTERS Configuration Register 15 0 CFG 31 The CR16C CR16C has four dedicated address registers to implement specific functions: the PC, ISP, USP, and INTBASE registers. RA SP Processor Status Register 15 0 PSR R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 5.2.2 5.2.1 Program Counter (PC) Register The 24-bit value in the PC register points to the first byte of the instruction currently being executed. CR16C CR16C instructions are aligned to even addresses, therefore the least significant bit of the PC is always 0. At reset, the PC is initialized to 0 or an optional predetermined value. When a warm reset occurs, value of the PC prior to reset is saved in the (R1,R0) general-purpose register pair. Interrupt Stack Pointer (ISP) The 32-bit ISP register points to the top of the interrupt stack. This stack is used by hardware to service exceptions (interrupts and traps). The stack pointer may be accessed Figure 1. CPU Registers as the ISP register for initialization. The interrupt stack can Some register bits are designated as "reserved." Software be located anywhere in the CPU address space. The ISP must write a zero to these bit locations when it writes to the cannot be used for any purpose other than the interrupt register. Read operations from reserved bit locations return stack, which is used for automatic storage of the CPU registers when an exception occurs and restoration of these undefined values. registers when the exception handler returns. The interrupt 5.1 GENERAL-PURPOSE REGISTERS stack grows downward in memory. The least significant bit The CompactRISC CPU features 16 general-purpose regis- and the 8 most significant bits of the ISP register are always ters. These registers are used individually as 16-bit oper- 0. ands or as register pairs for operations on addresses 5.2.3 User Stack Pointer (USP) greater than 16 bits. The USP register points to the top of the user-mode proGeneral-purpose registers are defined as R0 through gram stack. Separate stacks are available for user and suR13, RA, and SP. pervisor modes, to support protection mechanisms for Registers are grouped into pairs based on the setting of multitasking software. The processor mode is controlled by the Short Register bit in the Configuration Register the U bit in the PSR register (which is called PSR.U in the (CFG.SR). When the CFG.SR bit is set, the grouping of shorthand convention). Stack grow downward in memory. If register pairs is upward-compatible with the architecture the USP register points to an illegal address (any address of the earlier CR16A/B CR16A/B CPU cores: (R1,R0), (R2,R1) . greater than 0x00FF_FFFF) and the USP is used for stack (R11,R10), (R12_L, R11), (R13_L, R12_L), (R14_L, access, an IAD trap is taken. R13_L) and SP. (R14_L, R13_L) is the same as (RA,ERA). DS004 DS004 www.national.com 16 Interrupt Base Register (INTBASE) N The INTBASE register holds the address of the dispatch table for exceptions. The dispatch table can be located anywhere in the CPU address space. When loading the INTBASE register, bits 31 to 24 and bit 0 must written with 0. 5.3 PROCESSOR STATUS REGISTER (PSR) E The PSR provides state information and controls operating modes for the CPU. The format of the PSR is shown below. 15 12 11 10 9 Reserved C T L U F Z I P E 8 7 6 5 4 3 2 0 N Z F 0 U L 1 0 T C The Carry bit indicates whether a carry or borrow occurred after addition or subtraction. 0 ­ No carry or borrow occurred. 1 ­ Carry or borrow occurred. The Trace bit enables execution tracing, in which a Trace trap (TRC) is taken after every instruction. Tracing is automatically disabled during the execution of an exception handler. 0 ­ Tracing disabled. 1 ­ Tracing enabled. The Low bit indicates the result of the last comparison operation, with the operands interpreted as unsigned integers. 0 ­ Second operand greater than or equal to first operand. 1 ­ Second operand less than first operand. The User Mode bit controls whether the CPU is in user or supervisor mode. In supervisor mode, the SP register is used for stack operations. In user mode, the USP register is used instead. User mode is entered by executing the Jump USR instruction. When an exception is taken, the exception handler automatically begins execution in supervisor mode. The USP register is accessible using the Load Processor Register (LPR/LPRD) instruction in supervisor mode. In user mode, an attempt to access the USP register generates a UND trap. 0 ­ CPU is executing in supervisor mode. 1 ­ CPU is executing in user mode. The Flag bit is a general condition flag for signalling exception conditions or distinguishing the results of an instruction, among other thing uses. For example, integer arithmetic instructions use the F bit to indicate an overflow condition after an addition or subtraction operation. The Zero bit is used by comparison operations. In a comparison of integers, the Z bit is set if the two operands are equal. If the operands are unequal, the Z bit is cleared. 0 ­ Source and destination operands unequal. 1 ­ Source and destination operands equal. P I The Negative bit indicates the result of the last comparison operation, with the operands interpreted as signed integers. 0 ­ Second operand greater than or equal to first operand. 1 ­ Second operand less than first operand. The Local Maskable Interrupt Enable bit enables or disables maskable interrupts. If this bit and the Global Maskable Interrupt Enable (I) bit are both set, all interrupts are enabled. If either of these bits is clear, only the nonmaskable interrupt is enabled. The E bit is set by the Enable Interrupts (EI) instruction and cleared by the Disable Interrupts (DI) instruction. 0 ­ Maskable interrupts disabled. 1 ­ Maskable interrupts enabled. The Trace Trap Pending bit is used together with the Trace (T) bit to prevent a Trace (TRC) trap from occurring more than once for one instruction. At the beginning of the execution of an instruction, the state of the T bit is copied into the P bit. If the P bit remains set at the end of the instruction execution, the TRC trap is taken. 0 ­ No trace trap pending. 1 ­ Trace trap pending. The Global Maskable Interrupt Enable bit is used to enable or disable maskable interrupts. If this bit and the Local Maskable Interrupt Enable (E) bit are both set, all maskable interrupts are taken. If either bit is clear, only the non-maskable interrupt is taken. Unlike the E bit, the I bit is automatically cleared when an interrupt occurs and automatically set upon completion of an interrupt handler. 0 ­ Maskable interrupts disabled. 1 ­ Maskable interrupts enabled. Bits Z, C, L, N, and F of the PSR are referenced from assembly language by the condition code in conditional branch instructions. A conditional branch instruction may cause a branch in program execution, based on the value of one or more of these PSR bits. For example, one of the Bcond instructions, BEQ (Branch EQual), causes a branch if the PSR.Z bit is set. On reset, bits 0 through 11 of the PSR are cleared, except for the PSR.E bit, which is set. On warm reset, the values of each bit before reset are copied into the R2 general-purpose register. Bits 4 and 8 of the PSR have a constant value of 0. Bits 12 through 15 are reserved. In general, status bits are modified only by specific instructions. Otherwise, status bits maintain their values throughout instructions which do not implicitly affect them. 17 www.national.com CP3UB17 CP3UB17 5.2.4 CP3UB17 CP3UB17 5.4 CONFIGURATION REGISTER (CFG) The CFG register is used to enable or disable various operating modes and to control optional on-chip caches. Because the CP3UB17 CP3UB17 does not have cache memory, the cache control bits in the CFG register are reserved. All CFG bits are cleared on reset. 15 10 9 Reserved ED SR 8 7 6 SR ED 0 0 5 2 Reserved 1 0 0 0 The Extended Dispatch bit selects whether the size of an entry in the interrupt dispatch table (IDT) is 16 or 32 bits. Each entry holds the address of the appropriate exception handler. When the IDT has 16-bit entries, and all exception handlers must reside in the first 128K of the address space. The location of the IDT is held in the INTBASE register, which is not affected by the state of the ED bit. 0 ­ Interrupt dispatch table has 16-bit entries. 1 ­ Interrupt dispatch table has 32-bit entries. The Short Register bit enables a compatibility mode for the CR16B CR16B large model. In the CR16C CR16C core, registers R12, R13, and RA are extended to 32 bits. In the CR16B CR16B large model, only the lower 16 bits of these registers are used, and these "short registers" are paired together for 32-bit operations. In this mode, the (RA, R13) register pair is used as the extended RA register, and address displacements relative to a single register are supported with offsets of 0 and 14 bits in place of the index addressing with these displacements. 0 ­ 32-bit registers are used. 1 ­ 16-bit registers are used (CR16B CR16B mode). www.national.com 18 ADDRESSING MODES The CR16C CR16C CPU core implements a load/store architecture, in which arithmetic and logical instructions operate on register operands. Memory operands are made accessible in registers using load and store instructions. For efficient implementation of I/O-intensive embedded applications, the architecture also provides a set of bit operations that operate on memory operands. The load and store instructions support these addressing modes: register/pair, immediate, relative, absolute, and index addressing. When register pairs are used, the lower bits are in the lower index register and the upper bits are in the higher index register. When the CFG.SR bit is clear, the 32bit registers R12, R13, RA, and SP are also treated as register pairs. Index Mode References to register pairs in assembly language use parentheses. With a register pair, the lower numbered register pair must be on the right. For example, jump (r5, r4) For relative mode operands, the memory address is calculated by adding the value of a register pair and a displacement to the base address. The displacement can be a 14 or 20-bit unsigned value, which is encoded in the instruction. For absolute mode operands, the memory address is calculated by adding a 20-bit absolute address encoded in the instruction to the base address. load $4(r4,r3), (r6,r5) load $5(r12), (r13) The instruction set supports the following addressing modes: In register/pair mode, the operand is held in a general-purpose register, or in a general-purpose register pair. For example, the following instruction adds the contents of the low byte of register r1 to the contents of the low byte of r2, and places the result in the low byte register r2. The high byte of register r2 is not modified. ADDB R1, R2 Immediate In immediate mode, the operand is a conMode stant value which is encoded in the instruction. For example, the following instruction multiplies the value of r4 by 4 and places the result in r4. MULW $4, R4 Relative Mode In relative mode, the operand is addressed using a relative value (displacement) encoded in the instruction. This displacement is relative to the current Program Counter (PC), a general-purpose register, or a register pair. In another example, the operand resides in memory. Its address is obtained by adding a displacement encoded in the instruction to the contents of register r5. The address calculation does not modify the contents of register r5. LOADW 12(R5), R6 The following example calculates the address of a source operand by adding a displacement of 4 to the contents of a register pair (r5, r4) and loads this operand into the register pair (r7, r6). r7 receives the high word of the operand, and r6 receives the low word. LOADD 4(r5, r4), (r7, r6) In index mode, the operand address is calculated with a base address held in either R12 or R13. The CFG.SR bit must be clear to use this mode. Register/Pair Mode In the following example, the operand address is the sum of the displacement 4, the contents of the register pair (r5,r4), and the base address held in register r12. The word at this address is loaded into register r6. LOADW [r12]4(r5, r4), r6 Absolute Mode In absolute mode, the operand is located in memory, and its address is encoded in the instruction (normally 20 or 24 bits). For example, the following instruction loads the byte at address 4000 into the lower 8 bits of register r6. LOADB 4000, r6 For additional information on the addressing modes, see the CompactRISC CR16C CR16C Programmer's Reference Manual. In branch instructions, the displacement is always relative to the current value of the PC Register. For example, the following instruction causes an unconditional branch to an address 10 ahead of the current PC. BR *+10 19 www.national.com CP3UB17 CP3UB17 5.5 CP3UB17 CP3UB17 5.6 STACKS 5.7 A stack is a last-in, first-out data structure for dynamic storage of data and addresses. A stack consists of a block of memory used to hold the data and a pointer to the top of the stack. As more data is pushed onto a stack, the stack grows downward in memory. The CR16C CR16C supports two types of stacks: the interrupt stack and program stacks. INSTRUCTION SET Table 6 lists the operand specifiers for the instruction set, and Table 7 is a summary of all instructions. For each instruction, the table shows the mnemonic and a brief description of the operation performed. In the mnemonic column, the lower-case letter "i" is used to indicate the type of integer that the instruction operates on, either "B" for byte or "W" for word. For example, the notation 5.6.1 Interrupt Stack ADDi for the "add" instruction means that there are two The processor uses the interrupt stack to save and restore forms of this instruction, ADDB and ADDW, which operate the program state during the exception handling. Hardware on bytes and words, respectively. automatically pushes this data onto the interrupt stack before entering an exception handler. When the exception Similarly, the lower-case string "cond" is used to indicate the handler returns, hardware restores the processor state with type of condition tested by the instruction. For example, the data popped from the interrupt stack. The interrupt stack notation Jcond represents a class of conditional jump instructions: JEQ for Jump on Equal, JNE for Jump on Not pointer is held in the ISP register. Equal, etc. For detailed information on all instructions, see 5.6.2 Program Stack the CompactRISC CR16C CR16C Programmer's Reference ManuThe program stack is normally used by software to save and al. restore register values on subroutine entry and exit, hold loTable 6 Key to Operand Specifiers cal and temporary variables, and hold parameters passed between the calling routine and the subroutine. The only Operand Specifier Description hardware mechanisms which operate on the program stack are the PUSH, POP, and POPRET instructions. abs Absolute address 5.6.3 User and Supervisor Stack Pointers Immediate operand (numeric suffix indicates number of bits) Iposition Bit position in memory Rbase Base register (relative mode) Rdest Destination register Rindex Index register RPbase, RPbasex Base register pair (relative mode) RPdest Destination register pair RPlink Link register pair Bit position in register 16-bit processor register 32-bit processor register RPsrc Source register pair RPtarget Target register pair Rsrc, Rsrc1, Rsrc2 20 imm Rprocd www.national.com Displacement (numeric suffix indicates number of bits) Rproc When the PSR.U bit is set, the processor is in user mode, and the USP register is used as the program stack pointer. User mode can only be entered using the JUSR instruction, which performs a jump and sets the PSR.U bit. User mode is exited when an exception is taken and re-entered when the exception handler returns. In user mode, the LPRD instruction cannot be used to change the state of processor registers (such as the PSR). disp Rposition To support multitasking operating systems, support is provided for two program stack pointers: a user stack pointer and a supervisor stack pointer. When the PSR.U bit is clear, the SP register is used for all program stack operations. This is the default mode when the user/supervisor protection mechanism is not used, and it is the supervisor mode when protection is used. Source register CP3UB17 CP3UB17 Table 7 Instruction Set Summary Mnemonic Operands Description MOVi Rsrc/imm, Rdest Move MOVXB Rsrc, Rdest Move with sign extension MOVZB Rsrc, Rdest Move with zero extension MOVXW Rsrc, RPdest Move with sign extension MOVZW Rsrc, RPdest Move with zero extension MOVD imm, RPdest Move immediate to register-pair RPsrc, RPdest Move between register-pairs ADD[U]i Rsrc/imm, Rdest Add ADDCi Rsrc/imm, Rdest Add with carry ADDD RPsrc/imm, RPdest Add with RP or immediate. MACQWa Rsrc1, Rsrc2, RPdest Multiply signed Q15: RPdest := RPdest + (Rsrc1 × Rsrc2) MACSWa Rsrc1, Rsrc2, RPdest Multiply signed and add result: RPdest := RPdest + (Rsrc1 × Rsrc2) MACUWa Rsrc1, Rsrc2, RPdest Multiply unsigned and add result: RPdest := RPdest + (Rsrc1 × Rsrc2) MULi Rsrc/imm, Rdest Multiply: Rdest(8) := Rdest(8) × Rsrc(8)/imm Rdest(16) := Rdest(16) × Rsrc(16)/imm MULSB Rsrc, Rdest Multiply: Rdest(16) := Rdest(8) × Rsrc(8) MULSW Rsrc, RPdest Multiply: RPdest := RPdest(16) × Rsrc(16) MULUW Rsrc, RPdest Multiply: RPdest := RPdest(16) × Rsrc(16); SUBi Rsrc/imm, Rdest Subtract: (Rdest := Rdest - Rsrc/imm) SUBD RPsrc/imm, RPdest Subtract: (RPdest := RPdest - RPsrc/imm) SUBCi Rsrc/imm, Rdest Subtract with carry: (Rdest := Rdest - Rsrc/imm) CMPi Rsrc/imm, Rdest Compare Rdest - Rsrc/imm CMPD RPsrc/imm, RPdest Compare RPdest - RPsrc/imm BEQ0i Rsrc, disp Compare Rsrc to 0 and branch if EQUAL BNE0i Rsrc, disp Compare Rsrc to 0 and branch if NOT EQUAL ANDi Rsrc/imm, Rdest Logical AND: Rdest := Rdest & Rsrc/imm ANDD RPsrc/imm, RPdest Logical AND: RPdest := RPsrc & RPsrc/imm ORi Rsrc/imm, Rdest Logical OR: Rdest := Rdest | Rsrc/imm ORD RPsrc/imm, RPdest Logical OR: Rdest := RPdest | RPsrc/imm Scond Rdest Save condition code as boolean XORi Rsrc/imm, Rdest Logical exclusive OR: Rdest := Rdest ^ Rsrc/imm XORD RPsrc/imm, RPdest Logical exclusive OR: Rdest := RPdest ^ RPsrc/imm ASHUi Rsrc/imm, Rdest Arithmetic left/right shift 21 www.national.com CP3UB17 CP3UB17 Table 7 Instruction Set Summary Mnemonic Operands Description ASHUD Rsrc/imm, RPdest Arithmetic left/right shift LSHi Rsrc/imm, Rdest Logical left/right shift LSHD Rsrc/imm, RPdest Logical left/right shift SBITi Iposition, disp(Rbase) Set a bit in memory (Because this instruction treats the destination as a readmodify-write operand, it not be used to set bits in writeonly registers.) Iposition, disp(RPbase) Iposition, (Rindex)disp(RPbasex) Iposition, abs Iposition, (Rindex)abs CBITi Iposition, disp(Rbase) Clear a bit in memory Iposition, disp(RPbase) Iposition, (Rindex)disp(RPbasex) Iposition, abs Iposition, (Rindex)abs TBIT TBITi Rposition/imm, Rsrc Test a bit in a register Test a bit in memory Iposition, disp(Rbase) Iposition, disp(RPbase) Iposition, (Rindex)disp(RPbasex) Iposition, abs Iposition, (Rindex)abs LPR Rsrc, Rproc Load processor register LPRD RPsrc, Rprocd Load double processor register SPR Rproc, Rdest Store processor register SPRD Rprocd, RPdest Store 32-bit processor register Bcond disp9 Conditional branch disp17 disp24 BAL RPlink, disp24 Branch and link BR disp9 Branch disp17 disp24 EXCP vector Trap (vector) Jcond RPtarget Conditional Jump to a large address JAL RA, RPtarget, Jump and link to a large address RPlink, RPtarget JUMP RPtarget Jump JUSR RPtarget Jump and set PSR.U www.national.com 22 CP3UB17 CP3UB17 Table 7 Instruction Set Summary Mnemonic Operands Description RETX Return from exception PUSH imm, Rsrc, RA Push "imm" number of registers on user stack, starting with Rsrc and possibly including RA POP imm, Rdest, RA Restore "imm" number of registers from user stack, starting with Rdest and possibly including RA POPRET imm, Rdest, RA Restore registers (similar to POP) and JUMP RA LOADi disp(Rbase), Rdest Load (register relative) abs, Rdest Load (absolute) (Rindex)abs, Rdest Load (absolute index relative) (Rindex)disp(RPbasex), Rdest Load (register relative index) disp(RPbase), Rdest Load (register pair relative) disp(Rbase), Rdest Load (register relative) abs, Rdest Load (absolute) (Rindex)abs, Rdest Load (absolute index relative) (Rindex)disp(RPbasex), Rdest Load (register pair relative index) disp(RPbase), Rdest Load (register pair relative) Rsrc, disp(Rbase) Store (register relative) Rsrc, disp(RPbase) Store (register pair relative) Rsrc, abs Store (absolute) Rsrc, (Rindex)disp(RPbasex) Store (register pair relative index) Rsrc, (Rindex)abs Store (absolute index) RPsrc, disp(Rbase) Store (register relative) RPsrc, disp(RPbase) Store (register pair relative) RPsrc, abs Store (absolute) RPsrc, (Rindex)disp(RPbasex) Store (register pair index relative) RPsrc, (Rindex)abs Store (absolute index relative) imm4, disp(Rbase) Store unsigned 4-bit immediate value extended to operand length in memory LOADD STORi STORD STOR IMM imm4, disp(RPbase) imm4, (Rindex)disp(RPbasex) imm4, abs imm4, (Rindex)abs LOADM imm3 Load 1 to 8 registers (R2-R5, R8-R11 R8-R11) from memory starting at (R0) LOADMP imm3 Load 1 to 8 registers (R2-R5, R8-R11 R8-R11) from memory starting at (R1, R0) STORM STORM imm3 Store 1 to 8 registers (R2-R5, R8-R11 R8-R11) to memory starting at (R2) 23 www.national.com CP3UB17 CP3UB17 Table 7 Instruction Set Summary Mnemonic STORMP Operands Description imm3 Store 1 to 8 registers (R2-R5, R8-R11 R8-R11) to memory starting at (R7,R6) DI Disable maskable interrupts EI Enable maskable interrupts EIWAIT Enable maskable interrupts and wait for interrupt NOP No operation WAIT Wait for interrupt www.national.com 24 Memory The CP3UB17 CP3UB17 supports a uniform 16M-byte linear address are reserved and must not be read or written. The BIU space. Table 8 lists the types of memory and peripherals zones are regions of the address space that share the same that occupy this memory space. Unlisted address ranges control bits in the Bus Interface Unit (BIU). Table 8 CP3UB17 CP3UB17 Memory Map Start Address End Address Size in Bytes 00 0000h 03 FFFFh 256K On-chip Flash Program Memory, including Boot Memory 04 0000h 0D FFFFh 640K Reserved 0E 0000h 0E 1FFFh 8K On-chip Flash Data Memory 0E 2000h 0E 7FFFh 24K Reserved 0E 8000h 0E 91FFh 4.5K Reserved 0E 9200h 0E BFFFh 11.5K Reserved 0E C000h 0E E7FFh 10K System RAM 0E E800h 0E EBFFh 1K Reserved 0E EC00h 0E EFFFh 1K Reserved 0E F000h 0E F13Fh 320 Reserved 0E F140h 0E F17Fh 64 Reserved 0E F180h 0E F1FFh 128 Reserved 0E F200h 0F FFFFh 67.5K Reserved 10 0000h 3F FFFFh 3072K 3072K Reserved 40 0000h 7F FFFFh 4096K 4096K External Memory Zone 1 Static Zone 1 80 0000h FE FFFFh 8128K 8128K External Memory Zone 2 Static Zone 2 FF 0000h FF FAFFh 64256 BIU Peripherals FF FB00h FF FBFFh 256 I/O Expansion I/O Zone FF FC00h FF FFFFh 1K Peripherals and Other I/O Ports N/A 6.1 Description The operating environment controls whether external memory is supported and whether the reset vector jumps to a code space intended to support In-System Programming (ISP). Up to 8M of external memory space is available. The operating mode of the device is controlled by the states on the ENV2:0 pins at reset, as shown in Table 9. Table 9 Operating Environment Selection Operating Environment x10 Internal ROM enabled (IRE) or ISP mode 011 External ROM enabled (ERE) mode 000 When ENV2:0 = 111, IRE mode is selected unless the EMPTY bits in the Protection word indicate that the program flash memory is empty (unprogrammed), in which case ISP mode is selected. See Section 8.4.2 for more details. The ENV2 pin is only available on the 100-pin packages, therefore it is not possible to enter the ERE or DEV environments on the 48-pin versions of the CP3UB17 CP3UB17. In the DEV environment, the on-chip flash memory is disabled, and the corresponding region of the address space is mapped to external memory. 6.2 In-System-Programming (ISP) mode 111 Static Zone 0 (mapped internally in IRE and ERE mode; mapped to the external bus in DEV mode) N/A OPERATING ENVIRONMENT ENV2:0 BIU Zone Development (DEV) mode Internal pullups on the ENV2:0 pins select IRE mode or ISP mode if these pins are allowed to float. BUS INTERFACE UNIT (BIU) The BIU controls the interface between the CPU core bus and those on-chip modules which are mapped into BIU zones. These on-chip modules are the flash program memory and the I/O zone. The BIU controls the configured parameters for bus access (such as the number of wait states for memory access) and issues the appropriate bus signals for the requested access. 25 www.national.com CP3UB17 CP3UB17 6.0 CP3UB17 CP3UB17 6.3 BUS CYCLES 6.4.1 BIU Configuration Register (BCFG) The BCFG register is a byte-wide, read/write register that selects early-write or late-write bus cycles. At reset, the register is initialized to 07h. The register format is shown below. There are four types of data transfer bus cycles: Normal read Fast read Early write Late write 7 The type of data cycle used in a particular transaction depends on the type of CPU operation (a write or a read), the type of memory or I/O being accessed, and the access type programmed into the BIU control registers (early/late write EWR or normal/fast read). For read operations, a basic normal read takes two clock cycles, and a fast-read bus cycle takes one clock cycle. Normal read bus cycles are enabled by default after reset. 3 Reserved 2 1 0 1 1 EWR The Early Write bit controls write cycle timing. 0 ­ Late-write operation (2 clock cycles to write). 1 ­ Early-write operation. At reset, the BCFG register is initialized to 07h, which seFor write operations, a basic late-write bus cycle takes two lects early-write operation. However, late-write operation is clock cycles, and a basic early-write bus cycle takes three required for normal device operation, so software must clock cycles. Early-write bus cycles are enabled by default change the register value to 06h. Bits 1 and 2 of this register after reset. However, late-write bus cycles are needed for must always be set when writing to this register. ordinary write operations, so this configuration must be 6.4.2 I/O Zone Configuration Register (IOCFG) changed by software (see Section 6.4.1). The IOCFG register is a word-wide, read/write register that In certain cases, one or more additional clock cycles are controls the timing and bus characteristics of accesses to added to a bus access cycle. There are two types of addi- the 256-byte I/O Zone memory space (FF FB00h to FF tional clock cycles for ordinary memory accesses, called in- FBFFh). The registers associated with Port B and Port C reternal wait cycles (TIW) and hold (Thold) cycles. side in the I/O memory array. At reset, the register is initialA wait cycle is inserted in a bus cycle just after the memory ized to 069Fh. The register format is shown below. address has been placed on the address bus. This gives the accessed memory more time to respond to the transaction 7 6 5 4 3 2 0 request. BW Reserved HOLD WAIT A hold cycle is inserted at the end of a bus cycle. This holds the data on the data bus for an extended number of clock cycles. 15 10 9 8 6.4 BIU CONTROL REGISTERS Reserved The BIU has a set of control registers that determine how many wait cycles and hold cycles are to be used for accessing memory. During initialization of the system, these regis- WAIT ters should be programmed with appropriate values so that the minimum allowable number of cycles is used. This number varies with the clock frequency. There are five BIU control registers, as listed in Table 10. These registers control the bus cycle configuration used for HOLD accessing the various on-chip memory types. Table 10 Bus Control Registers Name Address Description BCFG FF F900h BIU Configuration Register IOCFG FF F902h I/O Zone Configuration Register SZCFG0 FF F904h Static Zone 0 Configuration Register SZCFG1 FF F906h Static Zone 1 Configuration Register SZCFG2 FF F908h Static Zone 2 Configuration Register BW www.national.com IPST 26 IPST Res. The Memory Wait Cycles field specifies the number of TIW (internal wait state) clock cycles added for each memory access, ranging from 000 binary for no additional TIW wait cycles to 111 binary for seven additional TIW wait cycles. The Memory Hold Cycles field specifies the number of Thold clock cycles used for each memory access, ranging from 00b for no Thold cycles to 11b for three Thold clock cycles. The Bus Width bit defines the bus width of the IO Zone. 0 ­ 8-bit bus width. 1 ­ 16-bit bus width (default) The Post Idle bit controls whether an idle cycle follows the current bus cycle, when the next bus cycle accesses a different zone. No idle cycles are required for on-chip accesses. 0 ­ No idle cycle (recommended). 1 ­ Idle cycle. Static Zone 0 Configuration Register (SZCFG0) IPRE The Preliminary Idle bit controls whether an idle cycle is inserted prior to the current bus cycle, when the new bus cycle accesses a different zone. No idle cycles are required for onchip accesses. 0 ­ No idle cycle (recommended). 1 ­ Idle cycle inserted. The SZCFG0 register is a word-wide, read/write register that controls the timing and bus characteristics of Zone 0 memory accesses. Zone 0 is used for the on-chip flash memory (including the boot area, program memory, and data memory). At reset, the register is initialized to 069Fh. The register format is shown below. 7 6 5 BW WBR RBE 15 4 3 2 HOLD 12 11 9 Static Zone 1 Configuration Register (SZCFG1) The SZCFG1 register is a word-wide, read/write register that controls the timing and bus characteristics for off-chip accesses selected with the SEL1 output signal. 0 WAIT 10 6.4.4 At reset, the register is initialized to 069Fh. The register format is shown below. 8 WAIT HOLD RBE WBR BW FRE IPST FRE IPRE IPST 7 Res. The Memory Wait field specifies the number of TIW (internal wait state) clock cycles added for each memory access, ranging from 000b for no additional TIW wait cycles to 111b for seven additional TIW wait cycles. These bits are ignored if the SZCFG0.FRE bit is set. The Memory Hold field specifies the number of Thold clock cycles used for each memory access, ranging from 00b for no Thold cycles to 11b for three Thold clock cycles. These bits are ignored if the SZCFG0.FRE bit is set. The Read Burst Enable enables burst cycles on 16-bit reads from 8-bit bus width regions of the address space. Because the flash program memory is required to be 16-bit bus width, the RBE bit is a don't care bit. This bit is ignored when the SZCFG0.FRE bit is set. 0 ­ Burst read disabled. 1 ­ Burst read enabled. The Wait on Burst Read bit controls if a wait state is added on burst read transaction. This bit is ignored, when SZCFG0.FRE bit is set or when SZCFG0.RBE is clear. 0 ­ No TBW on burst read cycles. 1 ­ One TBW on burst read cycles. The Bus Width bit controls the bus width of the zone. The flash program memory must be configured for 16-bit bus width. 0 ­ 8-bit bus width. 1 ­ 16-bit bus width (required). The Fast Read Enable bit controls whether fast read bus cycles are used. A fast read operation takes one clock cycle. A normal read operation takes at least two clock cycles. 0 ­ Normal read cycles. 1 ­ Fast read cycles. The Post Idle bit controls whether an idle cycle follows the current bus cycle, when the next bus cycle accesses a different zone. No idle cycles are required for on-chip accesses. 0 ­ No idle cycle (recommended). 1 ­ Idle cycle inserted. 6 5 BW Reserved WBR RBE 15 HOLD RBE WBR BW FRE 27 3 2 HOLD 12 Reserved WAIT 4 11 FRE 0 WAIT 10 9 IPRE IPST 8 Res. The Memory Wait field specifies the number of TIW (internal wait state) clock cycles added for each memory access, ranging from 000b for no additional TIW wait cycles to 111b for seven additional TIW wait cycles. These bits are ignored if the SZCFG1.FRE bit is set. The Memory Hold field specifies the number of Thold clock cycles used for each memory access, ranging from 00b for no Thold cycles to 11b for three Thold clock cycles. These bits are ignored if the SZCFG1.FRE bit is set. The Read Burst Enable enables burst cycles on 16-bit reads from 8-bit bus width regions of the address space. This bit is ignored when the SZCFG1.FRE bit is set or the SZCFG1.BW is clear. 0 ­ Burst read disabled. 1 ­ Burst read enabled. The Wait on Burst Read bit controls if a wait state is added on burst read transaction. This bit is ignored, when SZCFG1.FRE bit is set or when SZCFG1.RBE is clear. 0 ­ No TBW on burst read cycles. 1 ­ One TBW on burst read cycles. The Bus Width bit controls the bus width of the zone. 0 ­ 8-bit bus width. 1 ­ 16-bit bus width. The Fast Read Enable bit controls whether fast read bus cycles are used. A fast read operation takes one clock cycle. A normal read operation takes at least two clock cycles. 0 ­ Normal read cycles. 1 ­ Fast read cycles. www.national.com CP3UB17 CP3UB17 6.4.3 CP3UB17 CP3UB17 IPST IPRE 6.4.5 The Post Idle bit controls whether an idle cycle FRE follows the current bus cycle, when the next bus cycle accesses a different zone. 0 ­ No idle cycle. 1 ­ Idle cycle inserted. The Preliminary Idle bit controls whether an idle cycle is inserted prior to the current bus IPST cycle, when the new bus cycle accesses a different zone. 0 ­ No idle cycle. 1 ­ Idle cycle inserted. IPRE Static Zone 2 Configuration Register (SZCFG2) The SZCFG2 register is a word-wide, read/write register that controls the timing and bus characteristics for off-chip accesses selected with the SEL2 output signal. At reset, the register is initialized to 069Fh. The register format is shown below. 7 6 5 BW WBR RBE 15 HOLD RBE WBR BW 3 2 HOLD 12 Reserved WAIT 4 0 10 9 IPRE IPST 6.5.1 8 FRE WAIT AND HOLD STATES The number of wait cycles and hold cycles inserted into a bus cycle depends on whether it is a read or write operation, the type of memory or I/O being accessed, and the control register settings. WAIT 11 6.5 The Fast Read Enable bit controls whether fast read bus cycles are used. A fast read operation takes one clock cycle. A normal read operation takes at least two clock cycles. 0 ­ Normal read cycles. 1 ­ Fast read cycles. The Post Idle bit controls whether an idle cycle follows the current bus cycle, when the next bus cycle accesses a different zone. 0 ­ No idle cycle. 1 ­ Idle cycle inserted. The Preliminary Idle bit controls whether an idle cycle is inserted prior to the current bus cycle, when the new bus cycle accesses a different zone. 0 ­ No idle cycle. 1 ­ Idle cycle inserted. Res. The Memory Wait field specifies the number of TIW (internal wait state) clock cycles added for each memory access, ranging from 000b for no additional TIW wait cycles to 111b for seven additional TIW wait cycles. These bits are ignored if the SZCFG2.FRE bit is set. The Memory Hold field specifies the number of Thold clock cycles used for each memory access, ranging from 00b for no Thold cycles to 11b for three Thold clock cycles. These bits are ignored if the SZCFG2.FRE bit is set. The Read Burst Enable enables burst cycles on 16-bit reads from 8-bit bus width regions of the address space. This bit is ignored when the SZCFG2.FRE bit is set or the SZCFG2.BW is clear. 0 ­ Burst read disabled. 1 ­ Burst read enabled. The Wait on Burst Read bit controls if a wait state is added on burst read transaction. This bit is ignored, when SZCFG2.FRE bit is set or when SZCFG2.RBE is clear. 0 ­ No TBW on burst read cycles. 1 ­ One TBW on burst read cycles. The Bus Width bit controls the bus width of the zone. 0 ­ 8-bit bus width. 1 ­ 16-bit bus width. Flash Program/Data Memory When the CPU accesses the Flash program and data memory (address ranges 000000h­03FFFFh and 0E0000h­ 0E1FFFh), the number of added wait and hold cycles depends on the type of access and the BIU register settings. In fast-read mode (SZCFG0.FRE=1), a read operation is a single cycle access. This limits the maximum CPU operating frequency to 24 MHz. For a read operation in normal-read mode (SZCFG0.FRE=0), the number of inserted wait cycles is specified in the SZCFG0.WAIT field. The total number of wait cycles is the value in the WAIT field plus 1, so it can range from 1 to 8. The number of inserted hold cycles is specified in the SCCFG0.HOLD field, which can range from 0 to 3. For a write operation in fast read mode (SZCFG0.FRE=1), the number of inserted wait cycles is 1. No hold cycles are used. For a write operation normal read mode (SZCFG0.FRE=0), the number of wait cycles is equal to the value written to the SZCFG0.WAIT field plus 1 (in the late write mode) or 2 (in the early write mode). The number of inserted hold cycles is equal to the value written to the SCCFG0.HOLD field, which can range from 0 to 3. 6.5.2 RAM Memory Read and write accesses to on-chip RAM is performed within a single cycle, without regard to the BIU settings. The RAM address is in the range of 0E 8000h­0E 91FFh and 0E C000h­0E EBFFh. 6.5.3 Access to Peripherals When the CPU accesses on-chip peripherals in the range of 0E F000h­0E F1FFh and FF 0000h­FF FBFFh, one wait cycle and one preliminary idle cycle is used. No hold cycles are used. The IOCFG register determines the access timing for the address range FF FB00h­FF FBFFh. www.national.com 28 System Configuration Registers The system configuration registers control and provide status for certain aspects of device setup and operation, such as indicating the states sampled from the ENV[2:0] inputs. The system configuration registers are listed in Table 11. Table 11 System Configuration Registers Name Description MCFG FF F910h Module Configuration Register MSTAT 7.1 Address FF F914h Module Status Register MODULE CONFIGURATION REGISTER (MCFG) MISC_IO_SPEED The MISC_IO_SPEED bit controls the slew rate of the output drivers for the ENV[2:0], RDY, RFDATA, and TDO pins. To minimize noise, the slow slew rate is recommended. 0 ­ Fast slew rate. 1 ­ Slow slew rate. MEM_IO_SPEED The MEM_IO_SPEED bit controls the slew rate of the output drivers for the A[21:0], RD, SEL[2:1], and WR[1:0] pins. Memory speeds for the CP3UB17 CP3UB17 are characterized with fast slew rate. Slow slew rate reduces the available memory access time by 5 ns. 0 ­ Fast slew rate. 1 ­ Slow slew rate. 7.2 The MCFG register is a byte-wide, read/write register that selects the clock output features of the device. MODULE STATUS REGISTER (MSTAT) The MSTAT register is a byte-wide, read-only register that indicates the general status of the device. The MSTAT register format is shown below. The register must be written in active mode only, not in power save, HALT, or IDLE mode. However, the register contents are preserved during all power modes. 7 5 4 3 2 1 0 Reserved DPGMBUSY PGMBUSY OENV2 OENV1 OENV0 The MCFG register format is shown below. The Operating Environment bits hold the states sampled from the ENV[2:0] input pins MEM_IO MISC_IO USB SCLK MCLK PLLCLK EXI Res. at reset. These states are controlled by exter_SPEED _SPEED _ENABLE OE OE OE OE nal hardware at reset and are held constant in the register until the next reset. PGMBUSY The Flash Programming Busy bit is automatiEXIOE The EXIOE bit controls whether the external cally set when either the program memory or bus is enabled in the IRE environment for imthe data memory is being programmed or plementing the I/O Zone (FF FB00h­FF erased. It is clear when neither of the memoFBFFh). ries is busy. When this bit is set, software must 0 ­ External bus disabled. not attempt to program or erase either of 1 ­ External bus enabled. these two memories. This bit is a copy of the PLLCLKOE The PLLCLKOE bit controls whether the PLL FMBUSY bit in the FMSTAT register. clock is driven on the ENV0/PLLCLK pin. 0 ­ Flash memory is not busy. 0 ­ ENV0/PLLCLK pin is high impedance. 1 ­ Flash memory is busy. 1 ­ PLL clock driven on ENV0/PLLCLK. DPGMBUSY The Data Flash Programming Busy indicates MCLKOE The MCLKOE bit controls whether the Main that the flash data memory is being erased or Clock is driven on the ENV1/CPUCLK pin. a pipelined programming sequence is current0 ­ ENV1/CPUCLK pin is high impedance. ly ongoing. Software must not attempt to per1 ­ Main Clock is driven on ENV1/CPUCLK. form any write access to the flash program SCLKOE The SCLKOE bit controls whether the Slow memory at this time, without also polling the Clock is driven on the ENV2/SLOWCLK pin. FSMSTAT.FMFULL bit in the flash memory in0 ­ ENV2/SLOWCLK pin is high impedance. terface. The DPGMBUSY bit is a copy of the 1 ­ Slow Clock driven on ENV2/SLOWCLK. FMBUSY bit in the FSMSTAT register. USB_ENABLE The USB_ENABLE bit can be used to force 0 ­ Flash data memory is not busy. an external USB transceiver into its low-power 1 ­ Flash data memory is busy. mode. The power mode is dependent on the USB controller status, the USB_ENABLE bit in the Function Word (see Section 8.4.1), and the USB_ENABLE bit in the MCFG register. 0 ­ External USB transceiver forced into lowpower mode. 1 ­ Transceiver power mode dependent on USB controller status and programming of the Function Word. (This is the state of the USB_ENABLE bit after reset.) 7 6 5 4 3 2 1 0 OENV[2:0] 29 www.national.com CP3UB17 CP3UB17 7.0 CP3UB17 CP3UB17 8.0 Flash Memory The flash memory consists of the flash program memory and the flash data memory. The flash program memory is further divided into the Boot Area and the Code Area. default (after reset) all bits in the FM0WER, FM1WER, and FSM0WER registers are cleared, which disables write access by the CPU to all sections. Write access to a section is A special protection scheme is applied to the lower portion enabled by setting the corresponding write enable bit. After of the flash program memory, called the Boot Area. The completing a programming or erase operation, software Boot Area always starts at address 0 and ranges up to a should clear all write enable bits to protect the flash program programmable end address. The maximum boot area ad- memory against any unintended writes. dress which can be selected is 00 1BFFh. The intended use 8.1.2 Global Protection of this area is to hold In-System-Programming (ISP) rouThe WRPROT field in the Protection Word controls global tines or essential application routines. The Boot Area is alwrite protection. The Protection Word is located in a special ways protected against CPU write access, to avoid flash memory outside of the CPU address space. If a majorunintended modifications. ity of the bits in the 3-bit WRPROT field are clear, write proThe Code Area is intended to hold the application code and tection is enabled. Enabling this mode prevents the CPU constant data. The Code Area begins with the next byte af- from writing to flash memory. ter the Boot Area. Table 12 summarizes the properties of The RDPROT field in the Protection Word controls global the regions of flash memory mapped into the CPU address read protection. If a majority of the bits in the 3-bit RDPROT space. field are clear, read protection is enabled. Enabling this Table 12 Flash Memory Areas mode prevents reading by an external debugger through the serial debug interface or by an external flash programmer. Read Area Address Range Write Access CPU read access is not affected by the RDPROT bits. Access 8.2 Boot Area Code Area Data Area 0­BOOTAREA - 1 BOOTAREA­03 FFFFh 0E 0000h­0E 1FFFh Yes Write access only if section write enable bit is set and global write protection is disabled. Yes Each of the flash memories are divided into main blocks and information blocks. The main blocks hold the code or data used by application software. The information blocks hold factory parameters, protection settings, and other devicespecific data. The main blocks are mapped into the CPU address space. The information blocks are accessed indirectly through a register-based interface. Separate sets of registers are provided for accessing flash program memory (FM registers) and flash data memory (FSM registers). The flash program memory consists of two main blocks and two data blocks, as shown in Table 13. The flash data memory consists of one main block and one information block. No Yes FLASH MEMORY ORGANIZATION Write access only if section write enable bit is set and global write protection is disabled. Table 13 Flash Memory Blocks Function 00 0000h­01 FFFFh (CPU address space) Flash Program Memory Information Block 0 000h­07Fh (address register) Function Word, Factory Parameters Main Block 1 02 0000h­03 FFFFh (CPU address space) Flash Program Memory Information Block 1 080h­0FFh (address register) Protection Word, User Data Main Block 2 0E 0000h­0E 1FFFh (CPU address space) Flash Data Memory FLASH MEMORY PROTECTION The memory protection mechanisms provide both global and section-level protection. Section-level protection against CPU writes is applied to individual 8K-byte sections of the flash program memory and 512-byte sections of the flash data memory. Section-level protection is controlled through read/write registers mapped into the CPU address space. Global write protection is applied at the device level, to disable flash memory writes by the CPU. Global write protection is controlled by the encoding of bits stored in the flash memory array. 8.1.1 Address Range Main Block 0 8.1 Name Section-Level Protection Information 000h­07Fh User Data (address register) Block 2 Each bit in the Flash Memory Write Enable (FM0WER and FM1WER) registers enables or disables write access to a corresponding section of flash program memory. Write ac- 8.2.1 Main Block 0 and 1 cess to the flash data memory is controlled by the bits in the Main Block 0 and Main Block 1 hold the 256K-byte program Flash Slave Memory Write Enable (FSM0WER) register. By space, which consists of the Boot Area and Code Area. www.national.com 30 8.2.2 Information Block 0 Information Block 0 contains 128 bytes, of which one 16-bit word has a dedicated function, called the Function Word. The Function Word resides at address 07Eh. It controls the power mode of an external USB transceiver. The remaining Information Block 0 locations are used to hold factory parameters. 8.2.5 Information Block 2 Information Block 2 contains 128 bytes, which can be used to store user data. The CPU can always read Information Block 2. The CPU can write Information Block 2 only when global write protection is disabled. Erasing Information Block 2 also erases Main Block 2. 8.3 FLASH MEMORY OPERATIONS Flash memory programming (erasing and writing) can be performed on the flash data memory while the CPU is executing out of flash program memory. Although the CPU can execute out of flash data memory, it cannot erase or write the flash program memory while executing from flash data Software only has read access to Information Block 0 memory. To erase or write the flash program memory, the through a register-based interface. The Function Word and CPU must be executing from the on-chip static RAM or offthe factory parameters are protected against CPU writes. chip memory. Table 14 shows the structure of Information Block 0. An erase operation is required before programming. An Table 14 Information Block 0 erase operation sets all of the bits in the erased region. A programming operation clears selected bits. Address Read The programming mechanism is pipelined, so that a new Name Write Access Range Access write request can be loaded while a previous request is in Function Word Other (Used for Factory Parameters) progress. When the FMFULL bit in the FMSTAT or FSMSTAT register is clear, the pipeline is ready to receive a new