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DS25CP152QSQX/NOPB Texas Instruments Automotive 3.125 Gbps LVDS 2x2 Crosspoint Switch 16-WQFN -40 to 85 visit Texas Instruments
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CP15 Datasheet

Part Manufacturer Description PDF Type
CP15 Protek Devices 15.0V peak pulse power:200Watts standard capacitance TVS array Original
CP15 Protek Devices Subminiature Monolithic TVS Array Original
CP150 Teledyne LeCroy Test Leads - Oscilloscope Probes, Test and Measurement, PROBE CURRENT 150 AMP DC/AC Original
CP150 Electronic Devices 75mA Iout, 20kV Vrrm General Purpose Silicon Rectifier Scan
CP150 N/A Shortform Semicon, Diode, and SCR Datasheets Scan
CP1500 PanJit Semiconductors HIGH CURRENT SILICON BRIDGE RECTIFIER(VOLTAGE - 50 to 1000 Volts CURRENT - 15 Amperes) Original
CP1500 PanJit Semiconductors High current silicon bridge rectifier. Max recurrent peak reverse voltage 50V. Max average forward current for resistive load at Tc=55degC 15A. Original
CP1501 PanJit Semiconductors HIGH CURRENT SILICON BRIDGE RECTIFIER(VOLTAGE - 50 to 1000 Volts CURRENT - 15 Amperes) Original
CP1501 PanJit Semiconductors High current silicon bridge rectifier. Max recurrent peak reverse voltage 100V. Max average forward current for resistive load at Tc=55degC 15A. Original
CP15010 PanJit Semiconductors HIGH CURRENT SILICON BRIDGE RECTIFIER(VOLTAGE - 50 to 1000 Volts CURRENT - 15 Amperes) Original
CP1501-7R Power-One DC DC Converters, Power Supplies - External/Internal (Off-Board), DC/DC CONVERT 15V 12.9A Original
CP1501-9R Power-One DC DC Converters, Power Supplies - External/Internal (Off-Board), DC/DC CONVERT 15V 12.9A Original
CP1502 PanJit Semiconductors High current silicon bridge rectifier. Max recurrent peak reverse voltage 200V. Max average forward current for resistive load at Tc=55degC 15A. Original
CP1502 PanJit Semiconductors HIGH CURRENT SILICON BRIDGE RECTIFIER(VOLTAGE - 50 to 1000 Volts CURRENT - 15 Amperes) Original
CP1504 PanJit Semiconductors High current silicon bridge rectifier. Max recurrent peak reverse voltage 400V. Max average forward current for resistive load at Tc=55degC 15A. Original
CP1504 PanJit Semiconductors HIGH CURRENT SILICON BRIDGE RECTIFIER(VOLTAGE - 50 to 1000 Volts CURRENT - 15 Amperes) Original
CP1506 PanJit Semiconductors High current silicon bridge rectifier. Max recurrent peak reverse voltage 600V. Max average forward current for resistive load at Tc=55degC 15A. Original
CP1506 PanJit Semiconductors HIGH CURRENT SILICON BRIDGE RECTIFIER(VOLTAGE - 50 to 1000 Volts CURRENT - 15 Amperes) Original
CP1508 PanJit Semiconductors High current silicon bridge rectifier. Max recurrent peak reverse voltage 800V. Max average forward current for resistive load at Tc=55degC 15A. Original
CP1508 PanJit Semiconductors HIGH CURRENT SILICON BRIDGE RECTIFIER(VOLTAGE - 50 to 1000 Volts CURRENT - 15 Amperes) Original
Showing first 20 results.

CP15

Catalog Datasheet MFG & Type PDF Document Tags

ARM11 processor

Abstract: ARM11 "instruction set summary" Management Controller on page 15. 2.1 Standby Mode The Wait For Interrupt CP15 operation is executed , ensure the following occur: · · Any DMA operations in progress are stopped. · All CP15 , saved using CP15 operations. · If the Main TLB is powered down on entry into Dormant Mode (ARM1136 only), then the Valid bits of the Main TLB must be saved using CP15 operations. · On the , Interrupt CP15 operation is then executed, putting the ARM11 processor in Standby Mode and enabling the
ARM
Original
0143C ARM11 processor ARM11 "instruction set summary" Arm1176 ARM11 instruction sets ARM1176 processor TrustZone ARM1176

CP15

Abstract: LDR Datasheet to recover. The fault status (cp15_5) or the fault address (cp15_6) are not updated on prefetch , UNPREDICTABLE 11 Manager No access permission checks Data aborts update two cp15 registers. Cp15_6 is updated with the faulting virtual address. Cp15_5 is updated with fault status as summarized in , functions (cp15_1 register writes) can be enabled in parallel; it is not necessary to perform a separate , in cp15_1. If the MMU is enabled, instruction caching is dependent on the state of the C bit in the
Intel
Original
LDR Datasheet intel application note ap- sram Intel AP-10 Intel memory management unit EBSA-110 SA-110 WRCP15

specification of ldr

Abstract: LDR SPECIFICATION registers. Cp15_6 is updated with the faulting virtual address. Cp15_5 is updated with fault status as , to recover. The fault status (cp15_5) or the fault address (cp15_6) are not updated on prefetch , registers initialized, and the MMU enabled. Any of the control register functions (cp15_1 register writes , Icache is enabled by setting bit 12 in cp15_1. If the MMU is enabled, instruction caching is dependent , checked, even when disabled. It is enabled by setting bit 2 in cp15_1. The MMU must be enabled and the C
Digital Equipment
Original
specification of ldr LDR SPECIFICATION 21285-aa 21285AA 21A85 SA-110/21285

ARM DDI 0225

Abstract: PL192 . 3-3 About the CP15 system control coprocessor registers . 3-5 CP15 register descriptions . 3-9 CP15 , . 12-13 Code examples of CP15 cache operations . 12-15 , . xxii CP15 register summary , . 3-68 CP15 instruction summary
ARM
Original
ARM1026EJ-S 0244C ARM DDI 0225 PL192 C04RD 0x3010 ARMv5TEJ

ARM1136JF-S

Abstract: Jazelle v1 Architecture Reference Manual 2.8 2.9 2.10 Chapter 3 Control Coprocessor CP15 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 , Flow Prediction 5.1 5.2 5.3 5.4 5.5 Chapter 6 About control coprocessor CP15 . 3-2 Accessing CP15 registers . 3-3 Summary of control coprocessor CP15 registers . 3-5 CP15 registers arranged by function . 3-9 CP15
ARM
Original
ARM1136JF-S Jazelle v1 Architecture Reference Manual ARM processor ARM11 datasheet "instruction set summary" ARM1136JF ARM1136J-S

DDI0198B

Abstract: ARM926EJ-S Implementation Guide . 2-2 Summary of ARM926EJ-S system control coprocessor (CP15) registers . 2-3 Register , interface . 5-2 Using CP15 TCM region register r9 , . A-14 CP15 Test and Debug Registers B.1 About the test and debug registers , . ii CP15 register summary , . 2-4 CP15 abbreviations
ARM
Original
DDI0198B ARM926EJ-S Implementation Guide DDI0198B thumb instruction set ARM DII 0015 DXI 0131 ARM9EJ-S

ARM9TDMI

Abstract: ARM922T CP15 register map summary . 2-5 , -13 CP15 Test Registers B.1 B.2 B.3 B.4 B.5 About the test registers , . 2-3 CP15 register map , . 2-6 CP15 abbreviations , . 2-23 CP15 register functions
ARM
Original
ARM922T ARM9TDMI 141 mrc basic architecture of ARM Processors B-30 0184B

ARM920T

Abstract: TAG90 CP15 register map summary . 2-5 , -13 CP15 Test Registers B.1 B.2 ARM DDI 0151C ARM920T timing diagrams , . 2-3 CP15 register map , . 2-6 CP15 abbreviations , . 2-23 CP15 register functions
ARM
Original
TAG90 ARM processor Armv4 ARM920T rom cp15 149 StrongARM SA110

power transistor mrc 438

Abstract: POWER COMMAND HM 1211 . 1-20 CP15 register summary , . 3-33 CP15 register MMU functions , . 2-12 CP15 MCR instruction format . 3-3 CP15 MRC instruction format , . 3-25 Address mapping using CP15 R13
ARM
Original
power transistor mrc 438 POWER COMMAND HM 1211 STR F 6168 ARM10E ARM10 ARM1022E ARM1022ETM

Jazelle v1 Architecture Reference Manual

Abstract: ARM11 datasheet "instruction set summary" 2.7 2.8 2.9 2.10 Chapter 3 Control Coprocessor CP15 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 , Flow Prediction 5.1 5.2 5.3 5.4 5.5 Chapter 6 About control coprocessor CP15 . 3-2 Accessing CP15 registers . 3-3 Summary of control coprocessor CP15 registers . 3-5 CP15 registers arranged by function . 3-9 CP15
ARM
Original
MVAb ARMv5 datasheet ARMv6 DDI 0225 ARMv6 energy 0211C

ARM10200E

Abstract: ARM920T , in all instructions that access CP15. Using other values results in unpredictable behavior. 2.3.2 , About the ARM9E-S programmer's model. 2-3 CP15 , requirements . 5-2 Using CP15 control register , . 1-4 CP15 register map . 2-4 CP15 abbreviations
ARM
Original
ARM10200E 16610A INTEL Core i5 760 scrolling led display atmel 270512 0066G 0066B 0066C 0066D 0066E 0066F

stk 412 -770

Abstract: E3459A . About the CP15 system control coprocessor registers . CP15 , . 12-13 Code examples of CP15 cache operations . 12-15 , . xxi CP15 register summary , . 9-4 CP15 MMU registers , . 10-35 CP15 MPU registers
ARM
Original
stk 412 -770 E3459A ARM710T ARM720T ARM740T STK 412 770

ARM946E-S

Abstract: ARM946E-S IRAM CP1500, 2500, 3500 SERIES HIGH CURRENT SILICON BRIDGE RECTIFIERS VOLTAGE - 50 to 800 Volts , CP15 15 for Resistive Load CP25 25 at TC=55 ¢J CP35 35 Non-repetitive CP15 300 Peak Forward Surge Current at CP25 300 Rated Load CP35 400 Max Forward Voltage CP15 IF 7.5A per Bridge , 1000 at Rated DC Blocking Voltage @ TA=100 ¢J 2 I t Rating for fusing ( t < 8.3ms ) CP15,CP25 , CP1500 THRU CP3500 CP3500 AVERAGE OUTPUT CURRENT, AMPER5ES IFM AMPERES PEAK 1000 100 10
ARM
Original
ARM946E-S ARM966E-S ARM946E-S IRAM b10010

AT350

Abstract: ARM1026EJ-S access CP15. Using other values results in unpredictable behavior. 2.3.2 Register 0, ID code , the ARM9E-S programmer's model . 2-3 CP15 register , ARM946E-S (Rev 1) TCM interface description . Using CP15 control , descriptions . 1-4 CP15 register map . 2-5 CP15 terms and abbreviations . 2-6
ARM
Original
AT350 CP14 MVA generator ARM1026EJ-STM

ARM10E

Abstract: STK 412 770 is through Register 0 of the System Control Coprocessor, also referred to as coprocessor 15, or CP15. CP15 is available on processor cores containing an MMU or MPU only and contains a number of configuration registers (the actual number dependent on the core). CP15 Register 0 is hard-wired, readable by , .) family cores. Note ARM7TDMI, ARM7TDMI-S, ARM7EJ-S, and ARM9TDMI cores do not have a CP15. The bit , Note 1.2 The TAP ID is not visible through CP15 and so the revision of a particular ARM core is
ARM
Original
star sproc processor multi-ice interface unit ARM940T

wildcard 88

Abstract: INTEL Core i5 760 of the fault and how to recover. The fault status (cp15_5) or the fault address (cp15_6) are updated , unpredictable 11 Manager No access permission checks Data aborts update two cp15 registers. Cp15_6 is updated with the faulting virtual address. Cp15_5 is updated with fault status as summarised in , (cp15_1 register writes) can be enabled in parallel; it is not necessary to perform a separate read , , otherwise all hits will be taken. The Icache is enabled by setting bit 12 in cp15_1. If the MMU is enabled
ARM
Original
wildcard 88

CP15

Abstract: CP1500 . 2-2 Summary of ARM926EJ-S system control coprocessor (CP15) registers . 2-3 Register , . A-14 CP15 Test and Debug Registers B.1 About the Test and Debug Registers , . ii CP15 register summary , . 2-4 CP15 abbreviations , . 2-35 MMU program-accessible CP15 registers
PanJit International
Original
CP2500 CP25 CP-25 CP-25W

ARM5

Abstract: ARM946E-S . 2-2 Summary of ARM926EJ-S system control coprocessor (CP15) registers . 2-3 Register , interface . 5-2 Using CP15 TCM region register r9 , . A-14 CP15 Test and Debug Registers B.1 About the test and debug registers , . ii CP15 register summary , . 2-4 CP15 abbreviations
ARM
Original
ARM5 ARMv5TE instruction set ARMv5TE ARM9E datasheet ARM processor based Circuit Diagram ARM9E-S

ARM922T

Abstract: arm processor 2.7 2.8 2.9 2.10 Chapter 3 Control Coprocessor CP15 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 , Flow Prediction 5.1 5.2 5.3 5.4 5.5 Chapter 6 About control coprocessor CP15 . 3-2 Accessing CP15 registers . 3-3 Summary of control coprocessor CP15 registers . 3-5 CP15 registers arranged by function . 3-9 CP15
ARM
Original
ARM926 ARM946 ARM1020T arm9 architecture arm9 processor architecture B0100 0099B IEEE1149
Showing first 20 results.