CP-01051-1 - Datasheet Archive
Method and Apparatus of Continuous PLL Adaptation to Variable Reference Input Frequency Tim Hoang, Altera Corporation Sergey
DesignCon 2009 Method and Apparatus of Continuous PLL Adaptation to Variable Reference Input Frequency Tim Hoang, Altera Corporation Sergey Shumarayev, Altera Corporation Kazi Asaduzzaman, Altera Corporation Leon Zheng, Altera Corporation CP-01051-1 CP-01051-1.0 February 2009 Abstract In most applications, a phase-locked loop (PLLs) is configured to operate with one known input frequency (fIN) and to generate an output clock signal by multiplying or dividing that fIN. However, in some applications, such as plug and play and advanced video applications, the fIN is unknown to system designers yet the PLL still must operate correctly. This paper presents an innovative apparatus to assist the PLL with adapting any fIN and generating an output frequency (fOUT) using a pre-determined multiplication factor. Author Biographies Tim Hoang is a senior design manager at Altera Corporation. He has over 14 years of experience in digital and analog design and development. Tim has worked on SERDES design in Altera's Stratix® GX, Stratix II GX, Stratix III, Stratix IV GX, Cyclone® II, and Cyclone III FPGA product lines. Tim holds a bachelor's degree in electrical engineering from University of California at Berkeley. His areas of interest are in high-speed analog. Sergey Shumarayev is director of analog IC engineering at Altera Corporation. He has worked at Altera for over 12 years as a design engineer, senior design manager of the SERDES team, and analog group director. He holds a master's degree in electrical engineering from Cornell University and a bachelor's degree in electrical engineering, computer science, and material science from the University of California at Berkeley. He has over 70 issued patents and has co-authored several papers. Kazi Asaduzzaman is a senior member of technical staff at Altera Corporation. He has over 11 years of experience in digital and mixed-signal circuit design. Kazi has worked on SERDES design in Altera's Mercury®, Stratix GX, Stratix II GX , Stratix III, Stratix IV GX FPGA product lines, as well as PLL design in Altera's Cyclone II, Cyclone III, and Stratix III product lines. Kazi holds a bachelor's degree in electrical engineering from University of California at Berkeley and a Master of Science from Santa Clara University. His areas of interest are in high-speed analog. Leon Zheng is a design engineer at Altera Corporation. He has over seven years of experience in digital design and development. Leon has worked on DSP and PLL design in Altera's Stratix, Stratix II, Stratix III, Stratix IV GX, and Cyclone III product lines. Leon holds a bachelor's degree in electrical engineering from the University of Waterloo. His areas of interest are in high-speed design. Introduction A phase-locked loop (PLL) is an electronic circuit with a voltage-controlled oscillator (VCO) or current-driven oscillator that constantly adjusts to match (and thus lock on) the phase and frequency of a reference clock signal. In addition to stabilizing a particular communications channel (keeping it set to a particular frequency), a PLL generates a signal, modulates or demodulates a signal, reconstitutes a signal with less noise, and multiplies or divides a frequency. PLLs are frequently used in wireless communication, particularly where signals are carried using frequency modulation (FM) or phase modulation (PM), as well as in amplitude modulation (AM). PLLs are more commonly used for digital data transmission. A simple PLL, as shown in Figure 1, consists of a VCO, phase frequency detector (PFD), charge pump (CP), lock detect circuitry (LD), loop filter (LF), and feedback divider. The VCO is tuned to a frequency close to the desired receiving or transmitting frequency, by means of a feedback scheme. If the VCO frequency departs from the reference-clock input frequency (fIN), the PFD applies an error pulse to the charge-pump, bringing the VCO back to the reference frequency. Reference clk (fIN) Input N Counter Lock Detect Div_Ref_clk PFD VCO_out UP DOWN Chargepump VCTRL Loop Filter Feedback clk Lock signal Feedback M Counter VCO fOUT Output C0 Counter Output C1 Counter Output C2 Counter Figure 1. PLL Simplified Block Diagram The PLL output frequency (fOUT) is calculated as a function of fIN, and the feedback counter M, output counter C, and input divider N settings: M F FOUT 2 = × IN (1) C N In most PLL designs, a VCO has a limited operating frequency range, so the user must set the correct value for pre-, post-, and feedback dividers. This ensures the VCO and PLL operate optimally and give a clock output with the smallest output jitter. If the fIN drifts away from a pre-determined value, the PLL tracks the drift until the VCO is out of its valid operating range. At this point, the PLL loses its lock on the input clock signals. The valid range of the VCO varies depending on the requirements for PLL frequency support. In an application-specific system, the VCO range may be very small. However, for multi-purpose PLLs, the VCO range must cover a much wider range to support as many applications as possible. PLL Design Requirement In applications such as advanced display or plug-and-play applications, the clock fIN is unknown to system designers. Therefore, users must make on-site adjustments to all dividers based on supporting the clock fIN to ensure the PLL operating condition. If the settings are not adjusted, the VCO/PLL: · Functions normally if system reference clock (REFCLK) is within the desired frequency range · Loses its performance substantially and introduces output jitter if the VCO operates at the limit of its valid frequency range · Stops oscillating if REFCLK is much lower than desired frequency · Runs very fast and introduces a lot of jitter at its output, and depending on the design margin on flip-flop setup and hold time, certain blocks result in functional failure because they cannot keep up with the VCO speed One way to address the fIN variation is to build a VCO to support a very wide frequency range, from a few MHz to hundreds of MHz or even a few GHz. The VCO fOUT tracks with the fIN in a pre-defined ratio (fOUT = fIN × M), shown in Figure 2 (output frequency as a function of the VCO control voltage (VCTRL). However, this method of VCO design is impractical, with low performance due to wide frequency support and high VCO gain. 1.20E+09 Frequency 1.00E+09 8.00E+08 FVCOout = (Fin*M) 6.00E+08 4.00E+08 2.00E+08 0.00E+00 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 VCTRL Figure 2. Very Wide VCO Tuning Range In many multi-purpose PLLs, the VCO spans a wide frequency range, which is achieved by adding gears with selectable loads to the VCO output nodes, or by using a post-VCO divider. In the case of PLL design in Altera® FPGAs, the optimal VCO range spans only twice the frequency (fMAX = fIN×2) and post-VCO dividers are used to ensure continuous PLL frequency support, as shown in Figure 3. This helps to reduce high VCO and maintain PLL performance, with C ranging from 1 to 512. Continuous frequency support C=1 C=2 C=4 1325 1250 1175 1100 1025 950 875 800 725 650 575 500 425 350 275 200 125 Overlapping frequency ranges MHz Figure 3. C Output Frequencies for Different Settings Design Implementation To support the variable fIN, where the range varies by as much as 10X, an innovative new method allows the PLL to adjust its internal settings automatically so the PLL locks to any fIN and generates an output clock with a pre-determined multiplication factor. By changing M, C, and N so the VCO frequency stays within its operating range, the ratio of M, N, and C in Equation 1 remains unchanged: If the input reference clock increases and the VCO speeds up beyond its upper limit, M is halved to lower the VCO frequency. C also is halved so the multiplication factor remains unchanged. M / 2 FIN FOUT 2 = × (2) C/2 N If the input reference clock decreases and the VCO slows past its lower limit, then M doubles to speed up the VCO frequency and C also doubles to maintain the multiplication factor. M * 2 FIN FOUT 2 = × (3) C *2 N To maintain PLL performance in Altera FPGAs, the optimized VCO output covers frequencies ranging from 600 MHz to 1300 MHz for all silicon corners, temperature, and power supply levels. This ensures overlap in VCO frequency ranges for different Ms (or a continuous frequency range, as shown in Figure 3). From the VCO tuning curve (where C = 1) in Figure 4, the typical (TT) supporting VCTL ranges from 0.7V to 1.15V, with some design margin. In this case, 0.7V is the VCTRL lower range and 1.15V is the VCTRL upper range. M and C ensure the VCTRL is within the desired range, as necessary. For example, if the VCO frequency falls below 600 MHz with C and M set to 1, C and M can be changed to 2, thus increasing the VCO frequency to 1200 MHz (600 MHz×2), within the normal range. 1.80E+03 1.60E+03 PLL Frequency (Mhz) Upper Range Lower Range 1.40E+03 1.20E+03 C=1 Valid VCO Freq Range 1.00E+03 8.00E+02 C=2 C=4 Full PLL Frequency Range 6.00E+02 4.00E+02 2.00E+02 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 0.75 0.70 0.65 0.60 0.55 0.50 0.45 0.40 0.00E+00 VCO VCTRL (V) Figure 4. C Output Frequency (TT) vs. Counter Settings (1,2,3,4, .,n) Two voltage detection circuits and a state machine added to the PLL architecture support an automatic frequency detection circuit, shown in Figure 5. The detection circuit (an analog comparator) compares the VCTRL level with a pre-determined voltage level to detect if the VCO operates within its normal range. The voltage detection circuits have a built-in programmable 50-mV hysterisys to prevent the PLL from adjusting the configurations if it happens to operate near the upper or lower boundaries. The hysterisys option can be switched off if necessary. Lock Detect Reference clk (fIN) Div_Ref_clk Input N Counter PFD VCO_out UP DOWN Chargepump Loop Filter Feedback clk Lock signal Feedback M Counter VCTRL 1.15V 0.60V fOUT Output C# Counter VCO Over-range comparator VCO_OVRR Under-range comparator VCO_UNDR Figure 5. PLL Simplified Block Diagram With Detection Circuits State Machine · · The "under-range" (VCOUNDR) detector sets its output to high if the VCTR is below the "lower range" (typically 0.60V). The "over-range" (VCOOVRR) detector sets its output to high if the VCTR is above the "upper range" (typically 1.15V). These two control signals are routed to a state machine, which, in turn, updates the counter settings so the VCTRL voltage level is always within the valid operating range. As the counter values are updated, the ratio of M/(N×C) counters must stay the same to keep input-to-output clock multiplication factor unchanged. The counter settings are programmable and calculated based on the user's desired multiplication factors. As the example in Table 1 shows, the output of C0 is always followed by the fIN, whereas the output of C1 is programmed to be half of fIN and output of C2 is 3.5X of fIN. The number of counter configurations is also calculated based on the user's desired fIN support. As in this case, with seven different configurations (config_[7:1]), the PLL tracks fIN variation by as much as 14 times from the pre-defined slowest frequency. Configuration M C0 (1X) C1 (/2) config_ 7 7 14 config_ 14 14 28 config_ 21 21 42 config_ 28 28 56 config_ 35 35 70 config_ 42 42 84 config_ 49 49 98 Table 1. PLL Counter Configurations C2 (3.5X) 2 4 6 8 10 12 14 For slow (SS) or fast (SS) silicon corners (as opposed to TT), the VCTRL exhibits different voltage ranges for lower and upper limits, maintaining the VCO operating frequency range within 600 MHz to 1300 MHz (shown in Figure 6). To address these variations, the state machine updates the detection voltage levels for slow and fast materials, as shown in Table 2. 2.00E+03 1.80E+03 1.60E+03 1.40E+03 MHz 1.20E+03 1.00E+03 Valid VCO Freq Range FF SS TT 8.00E+02 6.00E+02 Operating Range for SS 4.00E+02 Operating Range for TT 2.00E+02 Operating Range for FF 0.00E+00 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 Vctrl Figure 6. VCO Tuning Curves vs. Silicon Corners Silicon Corner SS TT FF VCO range range_ range_ range_ Low Voltage level 0.7V 0.6V 0.5V High Voltage level 1.3V 1.1V 0.95V Table 2. Voltage Detection Levels The state machine uses an algorithm to detect and adjust the voltage detection levels (range_[m]) as necessary, so the PLL stays locked to the in-coming fIN. In addition, the PLL loop parameters (CP current and loop resistor value) are adjusted to maintain a constant PLL bandwidth, phase margin, and peaking. Figure 7 shows the actual state machine, where: n = different PLL predefined M/N/C counter settings. · m = different sets of high and low detection levels (for TT, SS, FF corners) · POR ( n=2 and m=1) Config_[n] Range_[m] (1) PLL reset 200µs (2) Yes Stable? Range_[m-1] Config_ (3) No & [(VCO_UNDER|| VCO_OVER)=1] Range_[m+1] Config_ No (7) No VCO_UNDER=1 Yes Is m>0? (6) VCO_OVER=1 (11) Yes Yes Is n6? (8) (4) Yes Is m>1? No (10) No No Config_[n-1] Config_[n+1] (9) (5) Input reference clk > preset range Reduce counter setting SS corner Figure 7. Finite State Machine State (1) After power-on reset, the PLL enters state (1) using the initial setting and based on user input, assuming TT silicon corner and preset fIN/ fOUT. In this example, the PLL is configured with config_ (M = 14) and range_ (low_voltage_detect = 0.6V and high_voltage_detect = 1.1V). Once the PLL completes the counter configuration, the state machine transfers to state (2). State (2) In state (2), the PLL goes through initialization sequence, taking about 200µs for the PLL to lock to the input reference clock. An external known clock fIN and extra counter (timer) are needed to keep track of this duration. In case of Altera FPGAs, the frequency of the configuration clock is well controlled and an extra counter is implemented in the FPGA core. The PLL fOUT also is used to clock the timer, but the timing variation may vary up to 400 µs as the maximum VCO frequency calculates the counter value for the timer. Once 200µs is reached, the state machine transfers to state (3). State (3) The PLL lock signal is sampled in state (3). The state machine stays in this state as long as the PLL lock signal is high. · If the PLL is unstable (lock signals low) and both the VCO_UNDR and VCO_OVRR are low, it is possible for the PLL to lose the lock because of external conditions, such · · as high input clock jitter, power supply noise, or high output jitter. In this case, the PLL resets to state (2) and tries to lock to the input clock again. If the lock signal is low and the VCO_UNDR is high, the VCO operates below its lower limit. In this case, the state machine tries to change the PLL configuration with a higher counter setting to increase the VCO fOUT by going to state (4). If the lock signal is low and the VCO_OVRR is high, the VCO operates above its upper limit. In this case, the state machine tries to change the PLL configuration with a lower counter setting to decrease the VCO fOUT by going to state (8). The state machine can be programmed to ignore the PLL lock signal and only rely on the VCO_UNDR and VCO_OVRR indicators. In this configuration, the state machine remains in state (3) as long as the VCO_UNDR and VCO_OVRR remain logic low. · If the VCO_UNDR is high, the state machine transfers from state (2) to state (4) to increase the VCO frequency. · If the VCO_OVRR is high, the state machine transfers from state (2) to stage (8) to reduce the VCO frequency. States (4) and (5) The configuration is examined in state (4). If the state machine has not exhausted all configurations possible (there is a maximum of seven in this example), the state machine transfers to state (5) and the next configuration with a higher counter value (as a result of lower fIN) is selected before it resets the PLL at 200 µs. If the state machine exhausts all of the configurations and the PLL still cannot find a stable solution, it means the current lower limit is not low enough for this particular device, as in the case of a fast corner device. The state machine moves to state (6), where the setting for the voltage detection range (range_[m]) is examined. States (6) and (7) If the state machine has not exhausted all of the range_m[2:0] configurations, it configures the PLL with a new set of lower voltage detection levels. However, if it reaches the lowest configuration (range_ in this case), the PLL fails to find a solution for current fIN. In this case, the state machine returns to state (0) to restart the frequency search from the beginning. States (8) and (9) The current configuration is examined in state (8). If the state machine has not exhausted all of the configurations (there is a maximum of seven in this example), the state machine transfers to state (9), and the next configuration with a lower counter value is selected before it resets the PLL at 200 µs. If the state machine reaches config_ and the PLL still cannot find a stable solution, it means the high limit is not high enough for this particular device, as in the case of a slow corner device. The state machine moves to state (10), where the setting for the voltage detection range (rang_[m]) is examined. States (10) and (11) If the state machine has not exhausted all of the range_m[2:0] configurations, it configures the PLL with a new set of higher voltage detection levels. However, if it reaches the highest configuration (range_ in this case), the PLL fails to find a solution for the current fIN. In this case, the state machine returns to state (0) to restart the frequency search from the beginning. The state machine can be implemented within the PLL structure, using hard intellectual property (IP), or in the FPGA core, using soft IP. Soft IP is the preferred choice as it is implemented only when users need it. It also allows more design flexibility in terms of frequency range for input references, multiplication factors, and number of fOUT. (It is important to note that if the fIN clock varies faster than the PLL bandwidth, the PLL will not achieve lock condition.) Conclusion This paper presents an innovative approach that allows PLLs to adapt continuously to the variable reference fIN, and to generate fOUT using a pre-determined multiplication factor by engaging detection circuitries and a finite state machine. Altera successfully verified design and soft IP in Cyclone III devices, with the reference fIN varying from 10 MHz to 160 MHz, and a total configuration time of less than 2 ms. 101 Innovation Drive San Jose, CA 95134 www.altera.com Copyright © 2009 Altera Corporation. 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