DS012838 DS012838-1 DS012838-2 DS012838-3 DS012838-4 DS012838-5 DS012838-6 - Datasheet Archive

 

8-Bit One-Time Programmable (OTP) Microcontroller General Description 1.1 INTRODUCTION The COPSAx7 OTP microcontrollers are

 

COP8SAA7/COP8SAB7/COP8SAC7 8-Bit One-Time Programmable (OTP) Microcontroller General Description 1.1 INTRODUCTION The COPSAx7 OTP microcontrollers are members of the COP8TM feature family using an 8-bit single chip core architecture. These devices are fabricated in National Semiconductor's high-density EPROM process, and offered on a variety of packages, temperature ranges and voltage ranges to satisfy a wide variety of applications. Key features include an 8-bit memory mapped architecture, a 16-bit timer/counter with two associated 16-bit registers supporting three modes (Processor Independent PWM generation, External Event counter, and Input Capture capabilities), two power saving HALT/IDLE modes with a multi-sourced wakeup/interrupt capability, on-chip R/C oscillator, high current outputs, user selectable options such as WATCHDOGTM, Oscillator configuration, and power-on-reset. 1.4 EMI REDUCTION The COPSAx7 family of devices incorporates circuitry that guards against electromagnetic interference-an increasing problem in today's microcontroller board designs. National's patented EMI reduction technology offers low EMI clock circuitry, gradual turn-on output drivers (GTOs) and internal ICC smoothing filters, to help circumvent many of the EMI issues influencing embedded control designs. National has achieved 15 dB­20 dB reduction in EMI transmissions when designs have incorporated its patented EMI reducing circuitry. 1.5 ARCHITECTURE The COPSAx7 family is based on a modified Harvard architecture, which allows data tables to be accessed directly from program memory. This is very important with modern microcontroller-based applications, since program memory is usually ROM or EPROM, while data memory is usually RAM. Consequently data tables usually need to be contained in ROM or EPROM, so they are not lost when the microcontroller is powered down. In a modified Harvard architecture, instruction fetch and memory data transfers can be overlapped with a two stage pipeline, which allows the next instruction to be fetched from program memory while the current instruction is being executed using data memory. This is not possible with a Von Neumann single-address bus architecture. The COPSAx7 family supports a software stack scheme that allows the user to incorporate many subroutine calls. This capability is important when using High Level Languages. With a hardware stack, the user is limited to a small fixed number of stack levels. 1.6 INSTRUCTION SET In today's 8-bit microcontroller application arena cost/ performance, flexibility and time to market are several of the key issues that system designers face in attempting to build well-engineered products that compete in the marketplace. Many of these issues can be addressed through the manner in which a microcontroller's instruction set handles processing tasks. And that's why COP8 family offers a unique and code-efficient instruction set-one that provides the flexibility, functionality, reduced costs and faster time to market that today's microcontroller based products require. Code efficiency is important because it enables designers to pack more on-chip functionality into less program memory space (ROM/OTP). Selecting a microcontroller with less program memory size translates into lower system costs, and the added security of knowing that more code can be packed into the available program memory space. 1.6.1 Key Instruction Set Features The COPSAx7 family incorporates a unique combination of instruction set features, which provide designers with optimum code efficiency and program memory utilization. Single Byte/Single Cycle Code Execution The efficiency is due to the fact that the majority of instructions are of the single byte variety, resulting in minimum program space. Because compact code does not occupy a substantial amount of program memory space, designers can integrate additional features and functionality into the microcontroller program memory space. Also, the majority instructions executed by the device are single cycle, resulting in minimum program execution time. In fact, 77% of the instructions are single byte single cycle, providing greater code and I/O efficiency, and faster code execution. 1.6.2 Many Single-Byte, Multifunction Instructions The COPSAx7 instruction set utilizes many single-byte, multifunction instructions. This enables a single instruction to accomplish multiple functions, such as DRSZ, DCOR, JID, and LOAD/EXCHANGE instructions with post-incrementing and post-decrementing, to name just a few examples. In many cases, the instruction set can simultaneously execute as many as three functions with the same single-byte instruction. JID: (Jump Indirect); Single byte instruction; decodes external events and jumps to corresponding service routines (analogous to "DO CASE" statements in higher level languages). LAID: (Load Accumulator-Indirect); Single byte look up table instruction provides efficient data path from the program memory to the CPU. This instruction can be used for table lookup and to read the entire program memory for checksum calculations. RETSK: (Return Skip); Single byte instruction allows return from subroutine and skips next instruction. Decision to branch can be made in the subroutine itself, saving code. COP8SAA7/COP8SAB7/COP8SAC7 August 1996 COP8SAA7/COP8SAB7/COP8SAC7 8-Bit One-Time Programmable (OTP) Microcontroller PRELIMINARY TRI-STATE ® is a registered trademark of National Semiconductor Corporation. MICROWIRE/PLUSTM, COP8TM, MICROWIRETM and WATCHDOGTM are trademarks of National Semiconductor Corporation. iceMASTERTM is a trademark of MetaLink Corporation. PC ® is a registered trademark of International Business Machines Corporation. © 1997 National Semiconductor Corporation www.national.com DS012838 DS012838 PrintDate=1997/07/14 PrintTime=11:41:57 2277 ds012838 Rev. No. 1 Proof 1 1 General Description (Continued) 1.2.1 CPU Features AUTOINC/DEC: (Auto-Increment/Auto-Decrement); These instructions use the two memory pointers B and X to efficiently process a block of data (analogous to "FOR NEXT" in higher level languages). 1.6.3 Bit-Level Control n Versatile easy to use instruction set n 1 µs instruction cycle time n Eight multi-source vectored interrupts servicing - External interrupt - Idle Timer T0 - One Timer (with 2 interrupts) - MICROWIRE/PLUSTM Serial Interface - Multi-Input Wake Up - Software Trap - Default VIS (default interrupt) n 8-bit Stack Pointer SP (stack in RAM) n Two 8-bit Register Indirect Data Memory Pointers n True bit manipulation n Memory mapped I/O n BCD arithmetic instructions Bit-level control over many of the microcontroller's I/O ports provides a flexible means to ease layout concerns and save board space. All members of the COP8 family provide the ability to set, reset and test any individual bit in the data memory address space, including memory-mapped I/O ports and associated registers. Three memory-mapped pointers handle register indirect addressing and software stack pointer functions. The memory data pointers allow the option of post-incrementing or post-decrementing with the data movement instructions (LOAD/EXCHANGE). And 15 memory-maped registers allow designers to optimize the precise implementation of certain specific instructions. 1.7 PACKAGING/PIN EFFICIENCY Real estate and board configuration considerations demand maximum space and pin efficiency, particularly given today's high integration and small product form factors. Microcontroller users try to avoid using large packages to get the I/O needed. Large packages take valuable board space and increases device cost, two trade-offs that microcontroller designs can ill afford. The COP8 family offers a wide range of packages and do not waste pins: up to 90.9% (or 40 pins in the 44-pin package) are devoted to useful I/O. 1.2.2 Peripheral Features n Multi-Input Wakeup Logic n One 16-bit timer with two 16-bit registers supporting: - Processor Independent PWM mode - External Event counter mode - Input Capture mode n Idle Timer n MICROWIRE/PLUS Serial Interface (SPI Compatible) 1.2.3 I/O Features n Software selectable I/O options - TRI-STATE ® Output - Push-Pull Output - Weak Pull Up Input - High Impedance Input n Schmitt trigger inputs on ports G and L n UP to 12 high current outputs n Pin efficient (i.e., 40 pins in 44-pin package are devoted to useful I/O) 1.2 KEY FEATURES n n n n n n n n n Low cost 8-bit OTP microcontroller OTP program space with read/write protection Quiet Design (low radiated emissions) Multi-Input Wakeup pins with optional interrupts (4 to 8 pins) 8 bytes of user storage space in EPROM User selectable clock options - Crystal/Resonator options - Crystal/Resonator option with on-chip bias resistor - External oscillator - Internal R/C oscillator Internal Power-On Reset-user selectable WATCHDOG and Clock Monitor Logic-user selectable Up to 12 high current outputs Device EPROM RAM 0°C to +70°C, -40°C to +85°C, and -40°C to +125°C of I/O 36 40 16 16 DIP/SO 12 16 28 DIP/SO 64 n Windowed packages for DIP and PLCC n Real time emulation and full program debug offered by MetaLink Development System 24 20 DIP/SO 1k 20 DIP/SO 28 DIP/SO COP8SAA7 128 24 44 PLCC/PQFP 1.2.6 Development Support 16 40 DIP 2k 20 DIP/SO 28 DIP/SO COP8SAB7 128 1.2.5 Temperature Ranges Number Types 4k n Low current drain (typically < 4 µA) n Single supply operation: 2.7V to 5.5V n Two power saving modes: HALT and IDLE Package and I/O Package COP8SAC7 1.2.4 Fully Static CMOS Design 24 www.national.com PrintDate=1997/07/14 PrintTime=11:42:03 2277 ds012838 Rev. No. 1 2 Proof 2 Block Diagram DS012838-1 DS012838-1 FIGURE 1. COP8SAx7 Block Diagram 3 PrintDate=1997/07/14 PrintTime=11:42:04 2277 ds012838 Rev. No. 1 www.national.com Proof 3 Table of Contents C. 1. GENERAL DESCRIPTION A. Introduction D. VIS Instruction a. VIS Execution Non-Maskable Interrupt E. a. Pending Flag b. Software Trap Port L Interrupts B. Key Features a. CPU Features b. Peripheral Features F. Interrupt Summary 9. WATCHDOG/CLOCK MONITOR A. Clock Monitor B. WATCHDOG/Clock Monitor Operation c. I/O Features d. Fully Static CMOS Design e. Temperature Ranges C. D. f. Development Support Block Diagram EMI Reduction C. D. 10. MICROWIRE/PLUS A. MICROWIRE/PLUS Operation a. MICROWIRE/PLUS Master Mode Operation b. MICROWIRE/PLUS Slave Mode Operation E. Architecture F. Instruction Set a. Key Instruction Set Features b. Single Byte/Single Cycle Code Execution 2. 3. 4. 5. 6. 7. c. Alternate SK Phase Operation and SK Idle Polarity 11. MEMORY MAP 12. INSTRUCTION SET A. Introduction B. Instruction Features C. Addressing Modes a. Operand Addressing Modes b. Transfer-of-Control Addressing Modes D. Instruction Types a. Arithmetic Instructions b. Transfer-of-Control Instructions c. Load and Exchange Instructions d. Logical Instructions e. Accumulator Bit Manipulation Instructions f. Stack Control Instructions g. Memory Bit Manipulation Instructions h. Conditional Instructions i. No-Operation Instruction E. Register and Symbol Definition F. Instruction Set Summary G. Instruction Execution Time H. Opcode Table 13. DEVELOPMENT SUPPORT A. Summary B. IceMASTERTM (IM) In-Circuit Emulation C. IceMASTER Debug Module (DM) c. Many Single-Byte, Multifunction Instructions d. Bit-Level Control G. Packaging/Pin Efficiency CONNECTION DIAGRAMS A. Ordering Information ELECTRICAL CHARACTERISTICS PIN DESCRIPTIONS FUNCTIONAL DESCRIPTION A. CPU Registers B. Program Memory C. Data Memory D. ECON (EPROM Configuration) Register E. User Storage Space in EPROM F. OTP Security G. Reset a. External Reset b. On-Chip Power-On Reset H. Oscillator Circuits a. Crystal Oscillator b. External Oscillator c. R/C Oscillator I. Control Registers TIMERS A. Timer T0 (IDLE Timer) B. Timer T1 a. Mode 1. Processor Independent PWM Mode b. Mode 2. External Event Counter Mode c. Mode 3. Input Capture Mode C. Timer Control Flags POWER SAVING FEATURES A. HALT Mode D. IceMASTER Evaluation Programming Unit (EPU) E. COP8 Assembler/Linker Software Development Tool Kit F. COP8 C Compiler G. Industry Wide OTP/EPROM Programming Support H. Available Literature I. Dial-A-Helper Service J. Customer Response Center B. IDLE Mode C. Multi-Input Wakeup 8. INTERRUPTS A. Introduction B. Maskable Interrupts www.national.com PrintDate=1997/07/14 PrintTime=11:42:06 2277 ds012838 Rev. No. 1 WATCHDOG and Clock Monitor Summary Detection of Illegal Conditions 14. PHYSICAL DIMENSIONS 4 Proof 4 Connection Diagrams DS012838-2 DS012838-2 Top View DS012838-3 DS012838-3 Top View DS012838-4 DS012838-4 Top View DS012838-5 DS012838-5 Top View FIGURE 2. Connection Diagrams 5 PrintDate=1997/07/14 PrintTime=11:42:08 2277 ds012838 Rev. No. 1 www.national.com Proof 5 Connection Diagrams DS012838-6 DS012838-6 DS012838-7 DS012838-7 Top View Top View FIGURE 3. Connection Diagrams DS012838-8 DS012838-8 FIGURE 4. Part Numbering Scheme www.national.com PrintDate=1997/07/14 PrintTime=11:42:08 2277 ds012838 Rev. No. 1 6 Proof 6 Connection Diagrams (Continued) 2.1 ORDERING INFORMATION 1k EPROM 2k EPROM 4k EPROM 4k EPROM Windowed Device Temperature Order Number Package 0°C to +70°C COP8SAA716M9 COP8SAA716M9 16M COP8SAA720M9 COP8SAA720M9 COP8SAA728M9 COP8SAA728M9 COP8SAA716N9 COP8SAA716N9 16N COP8SAA720N9 COP8SAA720N9 COP8SAA728N9 COP8SAA728N9 Order Number Package 20N COP8SAC720Q9 COP8SAC720Q9 20Q 28N COP8SAC728Q9 COP8SAC728Q9 28Q COP8SAC740N9 COP8SAC740N9 40N COP8SAC740Q9 COP8SAC740Q9 40Q COP8SAC744V9 COP8SAC744V9 44V COP8SAC744J9 COP8SAC744J9 44J COP8SAC7VEJ9 -40°C to +85°C Order Number Package Order Number Package 20M COP8SAB720M9 COP8SAB720M9 20M COP8SAC720M9 COP8SAC720M9 20M 28M COP8SAB728M9 COP8SAB728M9 28M COP8SAC728M9 COP8SAC728M9 28M 20N COP8SAB720N9 COP8SAB720N9 20N COP8SAC720N9 COP8SAC720N9 28N COP8SAB728N9 COP8SAB728N9 28N COP8SAC728N9 COP8SAC728N9 44PQFP 44PQFP COP8SAA716M8 COP8SAA716M8 16M COP8SAA720M8 COP8SAA720M8 20M COP8SAB720M8 COP8SAB720M8 20M COP8SAC720M8 COP8SAC720M8 20M COP8SAA728M8 COP8SAA728M8 28M COP8SAB728M8 COP8SAB728M8 28M COP8SAC728M8 COP8SAC728M8 28M COP8SAA716N8 COP8SAA716N8 16N COP8SAA720N8 COP8SAA720N8 20N COP8SAB720N8 COP8SAB720N8 20N COP8SAC720N8 COP8SAC720N8 20N COP8SAA728N8 COP8SAA728N8 28N COP8SAB728N8 COP8SAB728N8 28N COP8SAC728N8 COP8SAC728N8 28N COP8SAC740N8 COP8SAC740N8 40N COP8SAC744V8 COP8SAC744V8 44PQFP 44PQFP COP8SAC720M7 COP8SAC720M7 20M COP8SAC728M7 COP8SAC728M7 28M COP8SAC720N7 COP8SAC720N7 20N COP8SAC728N7 COP8SAC728N7 28N COP8SAC740N7 COP8SAC740N7 -40°C to +125°C 44V COP8SAC7VEJ8 40N COP8SAC744V7 COP8SAC744V7 44V COP8SAC7VEJ7 44PQFP 44PQFP 7 PrintDate=1997/07/14 PrintTime=11:42:11 2277 ds012838 Rev. No. 1 www.national.com Proof 7 3.0 Electrical Characteristics Absolute Maximum Ratings ESD Protection Level (Note 1) Total Current into VCC Pin (Source) Total Current out of GND Pin (Sink) Storage Temperature Range If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Voltage at Any Pin -0.6V to VCC 2 kV (Human Body Model) 80 mA 100 mA -65°C to +140°C Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings. 7V +0.6V DC Electrical Characteristics 0°C TA +70°C unless otherwise specified. Parameter Conditions Operating Voltage Min Typ Max Units 5.5 2.7 V Power Supply Rise Time (On-Chip Power-On Reset Selected) Power Supply Ripple (Note 3) Supply Current (Note 4) CKI = 10 MHz CKI = 4 MHz HALT Current (Note 5) -WATCHDOG Disabled IDLE Current (Note 4) CKI = 10 MHz CKI = 4 MHz 10 ns 50 ms Peak-to-Peak 0.1 VCC VCC = 5.5V, tC = 1 µs VCC = 4.5V, tC = 2.5 µs VCC = 5.5V, CKI = 0 MHz V 6 8 µA mA 0.8 VCC = 5.5V, tC = 1 µs VCC = 4.5V, tC = 2.5 µs mA 1.5 VCC and the pins will have sink current to VCC when biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750 (typical). These two pins will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients. Note 7: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs. Note 8: Parameter characterized but not tested. www.national.com PrintDate=1997/07/14 PrintTime=11:42:32 2277 ds012838 Rev. No. 1 10 Proof 10 Absolute Maximum Ratings Total Current into VCC Pin (Source) Total Current out of GND Pin (Sink) Storage Temperature Range (Note 9) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Voltage at Any Pin ESD Protection Level 80 mA 100 mA -65°C to +140°C Note 9: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings. 7V -0.6V to VCC +0.6V 2 kV (Human Body Model) DC Electrical Characteristics -40°C TA +85°C unless otherwise specified. Parameter Conditions Min Operating Voltage Typ Max Units 5.5 2.7 V Power Supply Rise Time (On-Chip Power-On Reset Selected) Power Supply Ripple (Note 11) Supply Current (Note 12) CKI = 10 MHz 10 ns 50 ms Peak-to-Peak 0.1 VCC HALT Current (Note 13) -WATCHDOG Disabled VCC = 5.5V, tC = 1 µs VCC = 5.5V, CKI = 0 MHz IDLE Current (Note 12) CKI = 10 MHz VCC = 5.5V, tC = 1 µs V 6.0 mA 10.0 µA 1.5 VCC and the pins will have sink current to VCC when biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750 (typical). These two pins will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients. Note 15: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs. Note 16: Parameter characterized but not tested. DS012838-9 DS012838-9 FIGURE 5. MICROWIRE/PLUS Timing 13 PrintDate=1997/07/14 PrintTime=11:42:57 2277 ds012838 Rev. No. 1 www.national.com Proof 13 Absolute Maximum Ratings Total Current into VCC Pin (Source) Total Current out of GND Pin (Sink) Storage Temperature Range (Note 17) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Voltage at Any Pin ESD Protection Level 80 mA 100 mA -65°C to +140°C Note 17: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings. 7V -0.6V to VCC +0.6V 2 kV (Human Body Model) DC Electrical Characteristics -40°C TA +125°C unless otherwise specified. Parameter Conditions Operating Voltage Min Typ Max Units 5.5 4.5 V Power Supply Rise Time (On-Chip Power-On Reset Selected) Power Supply Ripple (Note 11) Supply Current (Note 12) CKI = 10 MHz HALT Current (Note 13) -WATCHDOG Disabled IDLE Current (Note 12) CKI = 10 MHz 10 ns 50 ms Peak-to-Peak 0.1 VCC 6.0 < 10 VCC = 5.5V, tC = 1 µs mA 30 µA 1.5 VCC = 5.5V, tC = 1 µs VCC = 5.5V, CKI = 0 MHz V mA Input Levels (VIH, VIL) RESET Logic High 0.8 VCC V Logic Low 0.2 VCC V CKI, All Other Inputs Logic High 0.7 VCC V Logic Low 0.2 VCC Value of the Internal Bias Resistor V 0.5 1.0 2.0 M 5 8 11 k -5 +5 µA -35 -400 µA for the Crystal/Resonator Oscillator CKI Resistance to VCC or GND when R/C VCC = 5.5V Oscillator is Selected Hi-Z Input Leakage Input Pullup Current VCC = 5.5V VCC = 5.5V, VIN = 0V G and L Port Input Hysteresis 0.25 VCC V Output Current Levels D Outputs Source Sink VCC = 4.5V, VOH = 3.3V VCC = 4.5V, VOL = 1.0V -0.4 mA 9 mA L Port Source (Weak Pull-Up) Source (Push-Pull Mode) Sink (L0­L3, Push-Pull Mode) Sink (L4­L7, Push-Pull Mode) VCC = 4.5V, VOH = 2.7V VCC = 4.5V, VOH = 3.3V VCC = 4.5V, VOL = 1.0V VCC = 4.5V, VOL = 0.4V -9 -140 -0.4 µA mA 9 mA 1.4 mA All Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) TRI-STATE Leakage VCC = 4.5V, VOH = 2.7V VCC = 4.5V, VOH = 3.3V VCC = 4.5V, VOL = 0.4V VCC = 5.5V www.national.com PrintDate=1997/07/14 PrintTime=11:43:01 2277 ds012838 Rev. No. 1 -9 -140 -0.4 1.4 -5 µA mA mA +5 µA 14 Proof 14 DC Electrical Characteristics (Continued) -40°C TA +125°C unless otherwise specified. Parameter Conditions Min Typ Max Units D Outputs and L0 to L3 15 mA All Others 3 mA ± 200 mA Allowable Sink Current per Pin (Note 16) Maximum Input Current without Latchup Room Temp (Note 14) RAM Retention Voltage, Vr 2.0 V VCC Rise Time from a VCC 2.0V 1.2 µs Input Capacitance (Note 16) 7 pF Load Capacitance on D2 (Note 16) 1000 pF AC Electrical Characteristics -40°C TA +125°C unless otherwise specified. Parameter Conditions Min Typ Max Units DC µs DC µs TBD % Instruction Cycle Time (tC) Crystal/Resonator, External 4.5V VCC 5.5V Internal R/C Oscillator 4.5V VCC 5.5V R/C Oscillator Frequency Variation 4.5V VCC 5.5V 1.0 2.0 (Note 6) fr = Max fr = 10 MHz Ext Clock fr = 10 MHz Ext Clock 45 tSETUP 4.5V VCC 5.5V 200 ns tHOLD 4.5V VCC 5.5V RL = 2.2k, CL = 100 pF 60 ns External CKI Clock Duty Cycle (Note 6) Rise Time (Note 6) Fall Time (Note 6) 55 % 12 ns 8 ns Inputs Output Propagation Delay (Note 5) tPD1, tPD0 SO, SK 4.5V VCC 5.5V 0.7 µs All Others 4.5V VCC 5.5V 1.0 µs MICROWIRE Setup Time (tUWS) (Note 5) 20 MICROWIRE Hold Time (tUWH) (Note 5) 56 MICROWIRE Output Propagation Delay (tUPD) ns ns 220 ns MICROWIRE Maximum Shift Clock Master Mode 500 kHz Slave Mode 1 MHz Input Pulse Width (Note 6) Interrupt Input High Time 1 tC Interrupt Input Low Time 1 tC Timer 1, 2, 3 Input High Time 1 tC Timer 1, 2, 3 Input Low Time 1 tC 1 µs Reset Pulse Width 15 PrintDate=1997/07/14 PrintTime=11:43:04 2277 ds012838 Rev. No. 1 www.national.com Proof 15 not selected. If WATCHDOG feature is selected, bit 1 of the Port G configuration and data register does not have any effect on Pin G1 setup. Pin G7 is either input or output depending on the oscillator option selected. With the crystal oscillator option selected, G7 serves as the dedicated output pin for the CKO clock output. With the internal R/C or the external oscillator option selected, G7 serves as a general purpose Hi-Z input pin and is also used to bring the device out of HALT mode with a low to high transition on G7. There are two registers associated with Port G, a data register and a configuration register. Using these registers, each of the 5 I/O pins (G0, G2­G5) can be individually configured under software control. Since G6 is an input only pin and G7 is the dedicated CKO clock output pin (crystal clock option) or general purpose input (R/C or external clock option), the associated bits in the data and configuration registers for G6 and G7 are used for special purpose functions as outlined below. Reading the G6 and G7 data bits will return zeroes. The device will be placed in the HALT mode by writing a "1" to bit 7 of the Port G Data Register. Similarly the device will be placed in the IDLE mode by writing a "1" to bit 6 of the Port G Data Register. Writing a "1" to bit 6 of the Port G Configuration Register enables the MICROWIRE/PLUS to operate with the alternate phase of the SK clock. The G7 configuration bit, if set high, enables the clock start up delay after HALT when the R/C clock configuration is used. 4.0 Pin Descriptions COPSAx7 I/O structure minimizes external component requirements. Software-switchable I/O enables designers to reconfigure the microcontroller's I/O functions with a single instruction. Each individual I/O pin can be independently configured as an output pin low, an output high, an input with high impedance or an input with a weak pull-up device. A typical example is the use of I/O pins as the keyboard matrix input lines. The input lines can be programmed with internal weak pull-ups so that the input lines read logic high when the keys are all up. With a key closure, the corresponding input line will read a logic zero since the weak pull-up can easily be overdriven. When the key is released, the internal weak pullup will pull the input line back to logic high. This flexibility eliminates the need for external pull-up resistors. The High current options are available for driving LEDs, motors and speakers. This flexibility helps to ensure a cleaner design, with less external components and lower costs. Below is the general description of all available pins. VCC and GND are the power supply pins. All VCC and GND pins must be connected. CKI is the clock input. This can come from the Internal R/C oscillator, external, or a crystal oscillator (in conjunction with CKO). See Oscillator Description section. RESET is the master reset input. See Reset description section. The device contains four bidirectional 8-bit I/O ports (C, G, L and F), where each individual bit may be independently configured as an input (Schmitt trigger inputs on ports L and G), output or TRI-STATE under program control. Three data memory address locations are allocated for each of these I/O ports. Each I/O port has two associated 8-bit memory mapped registers, the CONFIGURATION register and the output DATA register. A memory mapped address is also reserved for the input pins of each I/O port. (See the memory map for the various addresses associated with the I/O ports.) Figure 6 shows the I/O port configurations. The DATA and CONFIGURATION registers allow for each port bit to be individually configured under software control as shown below: CONFIGURATION DATA Register 0 1 0 Push-Pull Zero Output 1 1 G6 Input with Weak Pull-Up 1 HALT Alternate SK IDLE G has the following alternate features: INTR (External Interrupt Input) T1B (Timer T1 Capture Input) T1A (Timer T1 I/O) SO (MICROWIRE Serial Data Output) SK (MICROWIRE Serial Clock) SI (MICROWIRE Serial Data Input) G has the following dedicated functions: WDOUT WATCHDOG and/or CLock Monitor if WATCHDOG enabled, otherwise it is a general purpose I/O G7 CKO Oscillator dedicated output or general purpose input Port C is an 8-bit I/O port. The 40-pin device does not have a full complement of Port C pins. The unavailable pins are not terminated. A read operation on these unterminated pins will return unpredictable values. Only the COP8SAC7 device contains Port C. The 20/28 pin devices do not offer Port C. On these devices, the associated Port C Data and Configuration registers should not be used. Port F is an 8-bit I/O port. The 28-pin device does not have a full complement of Port F pins. The unavailable pins are not terminated. A read operation on these unterminated pins will return unpredictable values. Hi-Z Input 0 Data Reg. CLKDLY Port G0 G2 G3 G4 G5 G6 Port G1 Register 0 Config. Reg. G7 Port Set-Up Push-Pull One Output (TRI-STATE Output) Port L is an 8-bit I/O port. All L-pins have Schmitt triggers on the inputs. Port L supports the Multi-Input Wake Up feature on all eight pins. The 16-pin device does not have a full complement of Port L pins. The unavailable pins are not terminated. A read operation these unterminated pins are not terminated. A read operation these unterminated pins will return unpredictable values. To minimize current drain, the unavailable pins must be programmed as outputs. Port G is an 8-bit port. Pin G0, G2­G5 are bi-directional I/O ports. Pin G6 is always a general purpose Hi-Z input. All pins have Schmitt Triggers on their inputs. Pin G1 serves as the dedicated WDOUT WATCHDOG output with weak pullup if WATCHDOG feature is selected by the ECON register. The pin is a general purpose I/O if WATCHDOG feature is www.national.com PrintDate=1997/07/14 PrintTime=11:43:11 2277 ds012838 Rev. No. 1 16 Proof 16 4.0 Pin Descriptions 5.0 Functional Description (Continued) The architecture of the device is a modified Harvard architecture. With the Harvard architecture, the program memory EPROM is separated from the data store memory (RAM). Both EPROM and RAM have their own separate addressing space with separate address buses. The architecture, though based on the Harvard architecture, permits transfer of data from EPROM to RAM. 5.1 CPU REGISTERS The CPU can do an 8-bit addition, subtraction, logical or shift operation in one instruction (tC) cycle time. There are six CPU registers: A is the 8-bit Accumulator Register PC is the 15-bit Program Counter Register PU is the upper 7 bits of the program counter (PC) PL is the lower 8 bits of the program counter (PC) B is an 8-bit RAM address pointer, which can be optionally post auto incremented or decremented. X is an 8-bit alternate RAM address pointer, which can be optionally post auto incremented or decremented. SP is the 8-bit stack pointer, which points to the subroutine/ interrupt stack (in RAM). With reset the SP is initialized to RAM address 02F Hex (devices with 64 bytes of RAM), or initialized to RAM address 06F Hex (devices with 128 bytes of RAM). All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC). DS012838-10 DS012838-10 FIGURE 6. I/O Port Configurations 5.2 PROGRAM MEMORY The program memory consists of 1024, 2048, or 4096 bytes of EPROM. Table 1 shows the program memory sizes for the different devices. These bytes may hold program instructions or constant data (data tables for the LAID instruction, jump vectors for the JID instruction, and interrupt vectors for the VIS instruction). The program memory is addressed by the 15-bit program counter (PC). All interrupts in the device vector to program memory location 0FF Hex. The contents of the program memory read 00 Hex in the erased state. DS012838-12 DS012838-12 FIGURE 7. I/O Port Configurations-Output Mode 5.3 DATA MEMORY The data memory address space includes the on-chip RAM and data registers, the I/O registers (Configuration, Data and Pin), the control registers, the MICROWIRE/PLUS SIO shift register, and the various registers, and counters associated with the timers (with the exception of the IDLE timer). Data memory is addressed directly by the instruction or indirectly by the B, X and SP pointers. The data memory consists of 64 or 128 bytes of RAM. Table 1 shows the data memory sizes for the different devices. Fifteen bytes of RAM are mapped as "registers" at addresses 0F0 to 0FE Hex. These registers can be loaded immediately, and also decremented and tested with the DRSZ (decrement register and skip if zero) instruction. The memory pointer registers X, SP and B are memory mapped into this space at address locations 0FC to 0FE Hex respectively, with the other registers (except 0FF) being available for general usage. Address location 0FF is reserved for future RAM expansion. If compatibility with future devices (with more RAM) is not desired, this location can be used as a general purpose RAM location. DS012838-11 DS012838-11 FIGURE 8. I/O Port Configurations-Input Mode Port D is an 8-bit output port that is preset high when RESET goes low. The user can tie two or more D port outputs (except D2) together in order to get a higher drive. Note: Care must be exercised with the D2 pin operation. At RESET, the external loads on this pin must ensure that the output voltages stay above 0.7 VCC to prevent the chip from entering special modes. Also keep the external loading on D2 to less than 1000 pF. The instruction set permits any bit in memory to be set, reset or tested. All I/O and registers (except A and PC) are 17 PrintDate=1997/07/14 PrintTime=11:43:12 2277 ds012838 Rev. No. 1 www.national.com Proof 17 5.0 Functional Description 5.5 USER STORAGE SPACE IN EPROM (Continued) There are 8 bytes of user storage space in the EPROM that are not read protected by the security bit in the ECON register. When the security bit in the ECON register is set, data in User Storage Space is write-enabled, and read-enabled. This allows the user to read and write this information while still protecting the main EPROM from tampering. memory mapped; therefore, I/O bits and register bits can be directly and individually set, reset and tested. The accumulator (A) bits can also be directly and individually tested. RAM contents are undefined upon power-up. The 8 bytes of user storage space are outside the normal address range of the device, and cannot be accessed by software. This allows for the storage of non-secure information. Typical uses of this are serial numbers, data codes, copyright informations, software version, or lot numbers. TABLE 1. Program/Data Memory Sizes Program Data User Memory Device Memory Storage (Bytes) (Bytes) (Bytes) COP8SAA7 1024 64 8 COP8SAB7 2048 128 8 COP8SAC7 4096 128 8 To place information into this area, the user can place the following in the assembly file: 1. Place data in the 8 bytes of user storage space Data is 1 2 3 4 5 6 7 8 .USER = 0x01 0x02 0x03 m0x04 0x05 0x06 0x07 0x08 2. Place assembly date in 8 bytes of user storage space Date is in format DD MM YY 00 HH MM SS (all information is in Hex) .USER = ASS_DATE 3. Place programming date in 8 bytes of user storage space Date is in format DD MM YY 00 HH MM SS (all information is in Hex) .USER = PRG_DATE 4. To place data in both memory space (for example, 4F9­4FF) to be read out using the LAID instruction, and the user storage space Data is 1 2 3 4 5 6 7 8 . = 0x4F9 .BYTE 0x01 0x02 0x03 m0x04 0x05 0x06 0x07 0x08 .USER = 0x01 0x02 0x03 m0x04 0x05 0x06 0x07 0x08 5.4 ECON (EPROM CONFIGURATION) REGISTER The ECON register is used to configure the user selectable clock, security, RAM size, power-on reset, WATCHDOG, and HALT options. The register can be programmed and read only in EPROM programming mode. Therefore, the register should be programmed at the same time as the program memory. The contents of the ECON register shipped from the factory read 00 Hex (windowed device) or 80 Hex (OTP device). The format of the ECON register is as follows: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 X POR SECURITY CKI 2 CKI 1 WATCH Bit 2 Bit 1 Bit 0 Reserved HALT DOG Bit 7 =x Bit 6 =1 =0 =1 Bit 5 =0 Bits 4, 3 = 0, 0 = 0, 1 = 1, 0 = 1, 1 Bit 2 =1 =0 Bit 1 Bit 0 = =1 =0 This is for factory test. The polarity is "Don't Care." Power-on reset enabled. Power-on reset disabled. Security enabled. EPROM read and write are not allowed. Security disabled. EPROM read and write are allowed. External CKI option selected. G7 is available as a HALT restart and/or general purpose input. CKI is clock input. R/C oscillator option selected. G7 is available as a HALT restart and/or general purpose input. CKI clock input. Internal R/C components are supplied for maximum R/C frequency. Crystal oscillator with on-chip crystal bias resistor disabled. G7 (CKO) is the clock generator output to crystal/resonator. Crystal oscillator with on-chip crystal bias resistor enabled. G7 (CKO) is the clock generator output to crystal/resonator. Note: Not all programmers support the PRG_Date option. Other serialization schemes are currently being worked on with device programming manufacturers. Please contact your device programmer supplier or National for more information. 5.6 OTP SECURITY The device has a security feature, when enabled, that prevents external reading of the OTP program memory. The security bit in the ECON register determines, whether security is enabled or disabled. If the security feature is disabled, the contents of the internal EPROM may be read. If the security feature is enabled, then any attempt to externally read the contents of the EPROM will result in the value FF Hex being read from all program locations. In addition, with the security feature enabled, the write operation to the EPROM program memory and ECON register is inhibited. The ECON register is readable regardless of the state of the security bit. If security is being used, it is recommended that all other bits in the ECON register be programmed first. Then the security bit can be programmed. WATCHDOG feature disabled. G1 is a general purpose I/O. WATCHDOG feature enabled. G1 pin is WATCHDOG output with waek pullup. Reserved. HALT mode disabled. HALT mode enabled. www.national.com PrintDate=1997/07/14 PrintTime=11:43:15 2277 ds012838 Rev. No. 1 18 Proof 18 5.0 Functional Description ing reset if the clock has not reached the minimum specified frequency at the termination of reset. A Clock Monitor error will cause an active low error output on pin G1. This error output will continue until 16 tC­32 tC clock cycles following the clock frequency reaching the minimum specified value, at which time the G1 output will go high. (Continued) 5.7 RESET The device is initialized when the RESET pin is pulled low or the On-chip Power-On Reset is enabled. 5.7.1 External Reset The RESET input when pulled low initializes the device. The RESET pin must be held low for a minimum of one instruction cycle to guarantee a valid reset. During Power-Up initialization, the user must ensure that the RESET pin is held low until the device is within the specified VCC voltage. An R/C circuit on the RESET pin with a delay 5 times (5x) greater than the power supply rise time or 15 µs whichever is greater, is recommended. Reset should also be wide enough to ensure crystal start-up upon Power-Up. DS012838-13 DS012838-13 FIGURE 9. Reset Logic The following occurs upon initialization: RESET may also be used to cause an exit from the HALT mode. A recommended reset circuit for this deviced is shown in Figure 10. Port L: TRISTATE Port C: TRISTATE Port G: TRISTATE Port F: TRISTATE Port D: HIGH PC: CLEARED to 0000 PSW, CNTRL and ICNTRL registers: CLEARED SIOR: UNAFFECTED after RESET with power already applied RANDOM after RESET at power-on T1CNTRL: CLEARED Accumulator, Timer 1: RANDOM after RESET with crystal clock option (power already applied) UNAFFECTED after RESET with R/C clock option (power already applied) RANDOM after RESET at power-on WKEN, WKEDG: CLEARED WKPND: RANDOM SP (Stack Pointer): Initialized to RAM address 02F Hex (devices with 64 bytes of RAM), or initialized to RAM address 06F Hex (devices with 128 bytes of RAM). B and X Pointers: DS012838-14 DS012838-14 RC > 5x power supply rise time or 15 µs, whichever is greater. FIGURE 10. Reset Circuit Using External Reset 5.7.2 On-Chip Power-On Reset The on-chip reset circuit is selected by a bit in the ECON register. When enabled, the device generates an internal reset as VCC rises to a voltage level above 2.0V. The on-chip reset circuitry is able to detect both fast and slow rise times on VCC (VCC rise time between 10 ns and 50 ms). Under no circumstances should the RESET pin be allowed to float. If the on-chip Power-On Reset feature is being used, RESET pin should be connected directly to VCC. The output of the power-on reset detector will always preset the Idle timer to 0FFF(4096 tC). At this time, the internal reset will be generated. If the Power-On Reset feature is enabled, the internal reset will not be turned off until the Idle timer underflows. The internal reset will perform the same functions as external reset. The user is responsible for ensuring that VCC is at the minimum level for the operating frequency within the 4096 tC. After the underflow, the logic is designed such that no additional internal resets occur as long as VCC remains above 2.0V. The contents of data registers and RAM are unknown following the on-chip reset. UNAFFECTED after RESET with power already applied RANDOM after RESET at power-on RAM: UNAFFECTED after RESET with power already applied RANDOM after RESET at power-on WATCHDOG (if enabled): The device comes out of reset with both the WATCHDOG logic and the Clock Monitor detector armed, with the WATCHDOG service window bits set and the Clock Monitor bit set. The WATCHDOG and Clock Monitor circuits are inhibited during reset. The WATCHDOG service window bits being initialized high default to the maximum WATCHDOG service window of 64k tC clock cycles. The Clock Monitor bit being initialized high will cause a Clock Monitor error follow- 19 PrintDate=1997/07/14 PrintTime=11:43:18 2277 ds012838 Rev. No. 1 www.national.com Proof 19 5.0 Functional Description (Continued) ECON4 ECON3 Oscillator Option 0 1 R/C Oscillator 1 1 Crystal Oscillator with Bias Resistor 5.8.1 Crystal Oscillator The crystal Oscillator mode can be selected by programming ECON Bit 4 to 1. CKI is the clock input while G7/CKO is the clock generator output to the crystal. An on-chip bias resistor connected between CKI and CKO can be enabled by programming ECON Bit 3 to 1 with the crystal oscillator option selection. The value of the resistor is in the range of 0.5M to 2M (typically 1.0M). Table 3 shows the component values required for various standard crystal values. Resistor R2 is only used when the on-chip bias resistor is disabled. Figure 13 shows the crystal oscillator connection diagram. TABLE 3. Crystal Oscillator Configuration, TA = 25°C, VCC = 5V R1 (k) R2 (M) C1 (pF) C2 (pF) CKI Freq. 0 1 30 30 15 0 1 32 32 10 0 1 45 30­36 4 5.6 1 100 100­156 0.455 (MHz) 5.8.2 External Oscillator The External Oscillator mode can be selected by programming ECON Bit 3 to 0 and ECON Bit 4 to 0. CKI can be driven by an external clock signal provided it meets the specified duty cycle, rise and fall times, and input levels. G7/ CKO is available as a general purpose input G7 and/or Halt control. Figure 14 shows the external oscillator connection diagram. DS012838-15 DS012838-15 FIGURE 11. Reset Timing (Power-On Reset Enabled) with VCC Tied to RESET 5.8.3 R/C Oscillator The R/C Oscillator mode can be selected by programming ECON Bit 3 to 1 and ECON Bit 4 to 0. In R/C oscillation mode, CKI is left floating, while G7/CKO is available as a general purpose input G7 and/or HALT control. The R/C controlled oscillator has on-chip resistor and capacitor for maximum R/C oscillator frequency operation. The maximum frequency is 5 MHz ± 35% for VCC between 4.5V to 5.5V and temperature range of -40°C to +85°C. For max frequency operation, the CKI pin should be left floating. For lower frequencies, an external capacitor should be connected between CKI and GND. Table 4 shows the oscillator frequency as a function of external capacitance on the CKI pin. Figure 15 shows the R/C oscillator configuration. DS012838-16 DS012838-16 FIGURE 12. Reset Circuit Using Power-On Reset 5.8 OSCILLATOR CIRCUITS There are four clock oscillator options available: Crystal Oscillator with or without on-chip bias resistor, R/C Oscillator with on-chip resistor and capacitor, and External Oscillator. The oscillator feature is selected by programming the ECON register, which is summarized in Table 2. TABLE 4. R/C Oscillator Configuration, -40°C to +85°C, VCC = 4.5V to 5.5V, OSC Freq. Variation of ± 35% External Capacitor R/C OSC Freq Instr. Cycle (pF) (MHz) (µs) 0 5 2.0 9 4 2.5 52 2 5.0 150 1 10 TBD 32 kHz 312.5 TABLE 2. Oscillator Option ECON4 ECON3 Oscillator Option 0 0 External Oscillator 1 0 Crystal Oscillator without Bias Resistor www.national.com PrintDate=1997/07/14 PrintTime=11:43:24 2277 ds012838 Rev. No. 1 20 Proof 20 5.0 Functional Description (Continued) Without On-Chip Bias Resistor With On-Chip Bias Resistor DS012838-17 DS012838-17 DS012838-18 DS012838-18 FIGURE 13. Crystal Oscillator DS012838-19 DS012838-19 FIGURE 14. External Oscillator DS012838-20 DS012838-20 DS012838-21 DS012838-21 For operation at lower than maximum R/C oscillator frequency. For operation at maximum R/C oscillator frequency. FIGURE 15. R/C Oscillator 21 PrintDate=1997/07/14 PrintTime=11:43:25 2277 ds012838 Rev. No. 1 www.national.com Proof 21 5.0 Functional Description (Continued) Unused T1C0 T1C3 T1C1 T1C0 MSEL IEDG SL1 Bit 7 SL0 PSW Register (Address X'00EF) The PSW register contains the following select bits: GIE Global interrupt enable (enables interrupts) EXEN Enable external interrupt BUSY MICROWIRE/PLUS busy shifting flag EXPND External interrupt pending T1ENA Timer T1 Interrupt Enable for Timer Underflow or T1A Input capture edge T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA in mode 1, T1 Underflow in Mode 2, T1A capture edge in mode 3) C Carry Flag HC Half Carry Flag HC C T1PNDA T1ENA T1PNDB EXPND BUSY EXEN GIE The Half-Carry flag is also affected by all the instructions that affect the Carry flag. The SC (Set Carry) and R/C (Reset Carry) instructions will respectively set or clear both the carry flags. In addition to the SC and R/C instructions, ADC, SUBC, RRC and RLC instructions affect the Carry and Half Carry flags. 6.2.1 Mode 1. Processor Independent PWM Mode One of the timer's operating modes is the Processor Independent PWM mode. In this mode, the timer generates a "Processor Independent" PWM signal because once the timer is setup, no more action is required from the CPU which translates to less software overhead and greater throughput. The user software services the timer block only when the PWM parameters require updating. This capability is provided by the fact that the timer has two separate 16-bit reload registers. One of the reload registers contains the "ON" timer while the other holds the "OFF" time. By contrast, a microcontroller that has only a single reload register requires an additional software to update the reload value (alternate between the on-time/off-time). ICNTRL Register (Address X'00E8) The ICNTRL register contains the following bits: T1ENB Timer T1 Interrupt Enable for T1B Input capture edge T1PNDB Timer T1 Interrupt Pending Flag for T1B capture edge µWEN Enable MICROWIRE/PLUS interrupt µWPND T0EN T0PND LPEN MICROWIRE/PLUS interrupt pending Timer T0 Interrupt Enable (Bit 12 toggle) Timer T0 Interrupt pending L Port Interrupt Enable (Multi-Input Wakeup/ Interrupt) Bit 7 could be used as a general purpose status flag PrintDate=1997/07/14 PrintTime=11:43:31 2277 ds012838 Rev. No. 1 Bit 0 6.2 TIMER T1 One of the main functions of a microcontroller is to provide timing and counting capability for real-time control tasks. The COP888 COP888 family offers a very versatile 16-bit timer/counter structure, and two supporting 16-bit autoreload/capture registers (R1A and R1B), optimized to reduce software burdens in real-time control applications. The timer block has two pins associated with it, T1A and T1B. Pin T1A supports I/O required by the timer block, while pin T1B is an input to the timer block. The timer block has three operating modes: Processor Independent PWM mode, External Event Counter mode, and Input Capture mode. The control bits T1C3, T1C2, and T1C1 allow selection of the different modes of operation. Bit 0 www.national.com T1ENB · Exit out of the Idle Mode (See Idle Mode description) · WATCHDOG logic (See WATCHDOG description) · Start up delay out of the HALT mode · Timing the width of the internal power-on-reset The IDLE Timer T0 can generate an interrupt when the twelfth bit toggles. This toggle is latched into the T0PND pending flag, and will occur every 4.096 ms at the maximum clock frequency (tC = 1 µs). A control flag T0EN allows the interrupt from the twelfth bit of Timer T0 to be enabled or disabled. Setting T0EN will enable the interrupt, while resetting it will disable the interrupt. Bit 0 Bit 7 WEN The Timer T0 supports the following functions: Timer T1 mode control bit Timer T1 mode control bit Timer T1 mode control bit T1C2 WPND 6.1 TIMER T0 (IDLE TIMER) The device supports applications that require maintaining real time and low power with the IDLE mode. This IDLE mode support is furnished by the IDLE timer T0. The Timer T0 runs continuously at the fixed rate of the instruction cycle clock, tC. The user cannot read or write to the IDLE Timer T0, which is a count down timer. Timer T1 Start/Stop control in timer modes 1 and 2 T1 Underflow Interrupt Pending Flag in timer mode 3 T1C1 T1C2 T1C3 T0EN The device contains a very versatile set of timers (T0, T1). Timer T1 and associated autoreload/capture registers power up containing random data. External interrupt edge polarity select (0 = Rising edge, 1 = Falling edge) Selects G5 and G4 as MICROWIRE/PLUS signals SK and SO respectively MSEL T0PND 6.0 Timers CNTRL Register (Address X'00EE) The Timer1 (T1) and MICROWIRE/PLUS control register contains the following bits: SL1 & SL0 Select the MICROWIRE/PLUS clock divide by (00 = 2, 01 = 4, 1x = 8) IEDG LPEN Bit 7 5.9 CONTROL REGISTERS The timer can generate the PWM output with the width and duty cycle controlled by the values stored in the reload registers. The reload registers control the countdown values and the reload values are automatically written into the timer when it counts down through 0, generating interrupt on each 22 Proof 22 6.0 Timers Underflows from the timer are alternately latched into two pending flags, T1PNDA and T1PNDB. The user must reset these pending flags under software control. Two control enable flags, T1ENA and T1ENB, allow the interrupts from the timer underflow to be enabled or disabled. Setting the timer enable flag T1ENA will cause an interrupt when a timer underflow causes the R1A register to be reloaded into the timer. Setting the timer enable flag T1ENB will cause an interrupt when a timer underflow causes the R1B register to be reloaded into the timer. Resetting the timer enable flags will disable the associated interrupts. Either or both of the timer underflow interrupts may be enabled. This gives the user the flexibility of interrupting once per PWM period on either the rising or falling edge of the PWM output. Alternatively, the user may choose to interrupt on both edges of the PWM output. (Continued) reload. Under software control and with minimal overhead, the PMW outputs are useful in controlling motors, triacs, the intensity of displays, and in providing inputs for data acquisition and sine wave generators. In this mode, the timer T1 counts down at a fixed rate of tC. Upon every underflow the timer is alternately reloaded with the contents of supporting registers, R1A and R1B. The very first underflow of the timer causes the timer to reload from the register R1A. Subsequent underflows cause the timer to be reloaded from the registers alternately beginning with the register R1B. The T1 Timer control bits, T1C3, T1C2 and T1C1 set up the timer for PWM mode operation. Figure 16 shows a block diagram of the timer in PWM mode. The underflows can be programmed to toggle the T1A output pin. The underflows can also be programmed to generate interrupts. DS012838-22 DS012838-22 FIGURE 16. Timer in PWM Mode 6.2.2 Mode 2. External Event Counter Mode This mode is quite similar to the processor independent PWM mode described above. The main difference is that the timer, T1, is clocked by the input signal from the T1A pin. The T1 timer control bits, T1C3, T1C2 and T1C1 allow the timer to be clocked either on a positive or negative edge from the T1A pin. Underflows from the timer are latched into the T1PNDA pending flag. Setting the T1ENA control flag will cause an interrupt when the timer underflows. In this mode the input pin T1B can be used as an independent positive edge sensitive interrupt input if the T1ENB control flag is set. The occurrence of a positive edge on the T1B input pin is latched into the T1PNDB flag. Figure 17 shows a block diagram of the timer in External Event Counter mode. DS012838-23 DS012838-23 Note: The PWM output is not available in this mode since the T1A pin is being used as the counter input clock. FIGURE 17. Timer in External Event Counter Mode 6.2.3 Mode 3. Input Capture Mode The device can precisely measure external frequencies or time external events by placing the timer block, T1, in the input capture mode. In this mode, the reload registers serve as independent capture registers, capturing the contents of the 23 PrintDate=1997/07/14 PrintTime=11:43:33 2277 ds012838 Rev. No. 1 www.national.com Proof 23 6.0 Timers on the T1A and T1B pins will be respectively latched into the pending flags, T1PNDA and T1PNDB. The control flag T1ENA allows the interrupt on T1A to be either enabled or disabled. Setting the T1ENA flag enables interrupts to be generated when the selected trigger condition occurs on the T1A pin. Similarly, the flag T1ENB controls the interrupts from the T1B pin. Underflows from the timer can also be programmed to generate interrupts. Underflows are latched into the timer T1C0 pending flag (the T1C0 control bit serves as the timer underflow interrupt pending flag in the Input Capture mode). Consequently, the T1C0 control bit should be reset when entering the Input Capture mode. The timer underflow interrupt is enabled with the T1ENA control flag. When a T1A interrupt occurs in the Input Capture mode, the user must check both the T1PNDA and T1C0 pending flags in order to determine whether a T1A input capture or a timer underflow (or both) caused the interrupt. (Continued) timer when an external event occurs (transition on the timer input pin). The capture registers can be read while maintaining count, a feature that lets the user measure elapsed time and time between events. By saving the timer value when the external event occurs, the time of the external event is recorded. Most microcontrollers have a latency time because they cannot determine the timer value when the external event occurs. The capture register eliminates the latency time, thereby allowing the applications program to retrieve the timer value stored in the capture register. In this mode, the timer T1 is constantly running at the fixed tC rate. The two registers, R1A and R1B, act as capture registers. Each register acts in conjunction with a pin. The register R1A acts in conjunction with the T1A pin and the register R1B acts in conjunction with the T1B pin. The timer value gets copied over into the register when a trigger event occurs on its corresponding pin. Control bits, T1C3, T1C2 and T1C1, allow the trigger events to be specified either as a positive or a negative edge. The trigger condition for each input pin can be specified independently. The trigger conditions can also be programmed to generate interrupts. The occurrence of the specified trigger condition Figure 18 shows a block diagram of the timer in Input Capture mode. DS012838-24 DS012838-24 FIGURE 18. Timer in Input Capture Mode www.national.com PrintDate=1997/07/14 PrintTime=11:43:35 2277 ds012838 Rev. No. 1 24 Proof 24 6.0 Timers T1PNDB Timer Interrupt Pending Flag T1ENA Timer Interrupt Enable Flag T1ENB Timer Interrupt Enable Flag 1 = Timer Interrupt Enabled (Continued) 6.3 TIMER CONTROL FLAGS The control bits and their functions are summarized below. T1C0 Timer Start/Stop control in Modes 1 and 2 (Processor Independent PWM and External Event Counter), where 1 = Start, 0 = Stop Timer Underflow Interrupt Pending Flag in Mode 3 (Input Capture) T1PNDA Timer Interrupt Pending Flag T1C3 T1C2 0 = Timer Interrupt Disabled Timer mode control Timer mode control T1C1 Timer mode control The timer mode control bits (T1C3, T1C2 and T1C1) are detailed below: T1C3 Interrupt B Timer Source Counts On 0 0 1 1 0 0 Pos. T1B T1A Underflow Edge Pos. Edge MODE 2 (External Timer Pos. T1B T1A Underflow Edge Neg. Edge MODE 1 (PWM) Autoreload Autoreload tC RA RB MODE 1 (PWM) Autoreload Autoreload No T1A Toggle 1 0 Timer T1A Toggle 1 1 MODE 2 (External Event Counter) 0 0 Timer Mode Event Counter) 0 0 T1C1 Interrupt A Source 0 T1C2 RA RB MODE 3 (Capture) Pos. T1A Pos. T1B Captures: Edge or Edge T1A Pos. Edge Timer T1B Pos. Edge 1 0 Pos. T1A Neg. T1B Edge or Edge T1A Pos. Edge 1 1 Underflow MODE 3 (Capture) Neg. T1A Pos. T1B Captures: Edge or Edge T1A Neg. Edge Timer T1B Pos. Edge Neg. T1B Edge or tC Underflow Edge Timer T1B Neg. Edge 1 Neg. T1A T1A Neg. Edge 1 MODE 3 (Capture) Captures: 1 tC Timer T1B Neg. Edge 0 tC Underflow MODE 3 (Capture) Captures: 1 tC Underflow 25 PrintDate=1997/07/14 PrintTime=11:43:39 2277 ds012838 Rev. No. 1 tC www.national.com Proof 25 with a low to high transition on the CKO (G7) pin. This method precludes the use of the crystal clock configuration (since CKO becomes a dedicated output), and so may only be used with an R/C clock configuration. The third method of exiting the HALT mode is by pulling the RESET pin low. 7.0 Power Save Modes Today, the proliferation of battery-operated based applications has placed new demands on designers to drive power consumption down. Battery-operated systems are not the only type of applications demanding low power. The power budget constraints are also imposed on those consumer/ industrial applications where well regulated and expensive power supply costs cannot be tolerated. Such applications rely on low cost and low power supply voltage derived directly from the "mains" by using voltage rectifier and passive components. Low power is demanded even in automotive applications, due to increased vehicle electronics content. This is required to ease the burden from the car battery. Low power 8-bit microcontrollers supply the smarts to control battery-operated, consumer/industrial, and automotive applications. The COPSAx7 devices offers system designers a variety of low-power consumption features that enable them to meet the demanding requirements of today's increasing range of low-power applications. These features include low voltage operation, low current drain, and power saving features such as HALT, IDLE, and Multi-Input wakeup (MIWU). The devices offers the user two power save modes of operation: HALT and IDLE. In the HALT mode, all microcontroller activities are stopped. In the IDLE mode, the on-board oscillator circuitry and timer T0 are active but all other microcontroller activities are stopped. In either mode, all on-board RAM, registers, I/O states, and timers (with the exception of T0) are unaltered. Since a crystal or ceramic resonator may be selected as the oscillator, the Wakeup signal is not allowed to start the chip running immediately since crystal oscillators and ceramic resonators have a delayed start up time to reach full amplitude and frequency stability. The IDLE timer is used to generate a fixed delay to ensure that the oscillator has indeed stabilized before allowing instruction execution. In this case, upon detecting a valid Wakeup signal, only the oscillator circuitry is enabled. The IDLE timer is loaded with a value of 256 and is clocked with the tC instruction cycle clock. The tC clock is derived by dividing the oscillator clock down by a factor of 10. The Schmitt trigger following the CKI inverter on the chip ensures that the IDLE timer is clocked only when the oscillator has a sufficiently large amplitude to meet the Schmitt trigger specifications. This Schmitt trigger is not part of the oscillator closed loop. The start-up time-out from the IDLE timer enables the clock signals to be routed to the rest of the chip. If an R/C clock option is being used, the fixed delay is introduced optionally. A control bit, CLKDLY, mapped as configuration bit G7, controls whether the delay is to be introduced or not. The delay is included if CLKDLY is set, and excluded if CLKDLY is reset. The CLKDLY bit is cleared on reset. The device has two options associated with the HALT mode. The first option enables the HALT mode feature, while the second option disables the HALT mode selected through bit 0 of the ECON register. With the HALT mode enable option, the device will enter and exit the HALT mode as described above. With the HALT disable option, the device cannot be placed in the HALT mode (writing a "1" to the HALT flag will have no effect, the HALT flag will remain "0"). The WATCHDOG detector circuit is inhibited during the HALT mode. However, the clock monitor circuit if enabled remains active during HALT mode in order to ensure a clock monitor error if the device inadvertently enters the HALT mode as a result of a runaway program or power glitch. If the device is placed in the HALT mode, with the R/C oscillator selected, the clock input pin (CKI) is forced to a logic high internally. With the crystal or external oscillator the CKI pin is TRI-STATE. Clock Monitor if enabled can be active in both modes. 7.1 HALT MODE The device can be placed in the HALT mode by writing a "1" to the HALT flag (G7 data bit). All microcontroller activities, including the clock and timers, are stopped. The WATCHDOG logic on the device is disabled during the HALT mode. However, the clock monitor circuitry, if enabled, remains active and will cause the WATCHDOG output pin (WDOUT) to go low. If the HALT mode is used and the user does not want to activate the WDOUT pin, the Clock Monitor should be disabled after the device comes out of reset (resetting the Clock Monitor control bit with the first write to the WDSVR register). In the HALT mode, the power requirements of the device are minimal and the applied voltage (VCC) may be decreased to Vr (Vr = 2.0V) without altering the state of the machine. The device supports three different ways of exiting the HALT mode. The first method of exiting the HALT mode is with the Multi-Input Wakeup feature on Port L. The second method is www.national.com PrintDate=1997/07/14 PrintTime=11:44:02 2277 ds012838 Rev. No. 1 26 Proof 26 7.0 Power Save Modes (Continued) DS012838-25 DS012838-25 FIGURE 19. Wakeup from HALT The user can enter the IDLE mode with the Timer T0 interrupt enabled. In this case, when the T0PND bit gets set, the device will first execute the Timer T0 interrupt service routine and then return to the instruction following the "Enter Idle Mode" instruction. Alternatively, the user can enter the IDLE mode with the IDLE Timer T0 interrupt disabled. In this case, the device will resume normal operation with the instruction immediately following the "Enter IDLE Mode" instruction. 7.2 IDLE MODE The device is placed in the IDLE mode by writing a "1" to the IDLE flag (G6 data bit). In this mode, all activities, except the associated on-board oscillator circuitry and the IDLE Timer T0, are stopped. As with the HALT mode, the device can be returned to normal operation with a reset, or with a Multi-Input Wakeup from the L Port. Alternately, the microcontroller resumes normal operation from the IDLE mode when the twelfth bit (representing 4.096 ms at internal clock frequency of 10 MHz, tC = 1 µs) of the IDLE Timer toggles. This toggle condition of the twelfth bit of the IDLE Timer T0 is latched into the T0PND pending flag. The user has the option of being interrupted with a transition on the twelfth bit of the IDLE Timer T0. The interrupt can be enabled or disabled via the T0EN control bit. Setting the T0EN flag enables the interrupt and vice versa. Note: It is necessary to program two NOP instructions following both the set HALT mode and set IDLE mode instructions. These NOP instructions are necessary to allow clock resynchronization following the HALT or IDLE modes. DS012838-26 DS012838-26 FIGURE 20. Wakeup from IDLE 27 PrintDate=1997/07/14 PrintTime=11:44:04 2277 ds012838 Rev. No. 1 www.national.com Proof 27 7.0 Power Save Modes RBIT 5, WKEN ; Disable MIWU SBIT 5, WKEDG ; Change edge polarity RBIT 5, WKPND ; Reset pending flag SBIT 5, WKEN ; Enable MIWU If the L port bits have been used as outputs and then changed to inputs with Multi-Input Wakeup/Interrupt, a safety procedure should also be followed to avoid wakeup conditions. After the selected L port bits have been changed from output to input but before the associated WKEN bits are enabled, the associated edge select bits in WKEDG should be set or reset for the desired edge selects, followed by the associated WKPND bits being cleared. This same procedure should be used following reset, since the L port inputs are left floating as a result of reset. The occurrence of the selected trigger condition for Multi-Input Wakeup is latched into a pending register called WKPND. The respective bits of the WKPND register will be set on the occurrence of the selected trigger edge on the corresponding Port L pin. The user has the responsibility of clearing these pending flags. Since WKPND is a pending register for the occurrence of selected wakeup conditions, the device will not enter the HALT mode if any Wakeup bit is both enabled and pending. Consequently, the user must clear the pending flags before attempting to enter the HALT mode. WKEN and WKEDG are all read/write registers, and are cleared at reset. WKPND register contains random value after reset. (Continued) 7.3 MULTI-INPUT WAKEUP The Multi-Input Wakeup feature is used to return (wakeup) the device from either the HALT or IDLE modes. Alternately Multi-Input Wakeup/Interrupt feature may also be used to generate up to 8 edge selectable external interrupts. Figure 21 shows the Multi-Input Wakeup logic. The Multi-Input Wakeup feature utilizes the L Port. The user selects which particular L port bit (or combination of L Port bits) will cause the device to exit the HALT or IDLE modes. The selection is done through the register WKEN. The register WKEN is an 8-bit read/write register, which contains a control bit for every L port bit. Setting a particular WKEN bit enables a Wakeup from the associated L port pin. The user can select whether the trigger condition on the selected L Port pin is going to be either a positive edge (low to high transition) or a negative edge (high to low transition). This selection is made via the register WKEDG, which is an 8-bit control register with a bit assigned to each L Port pin. Setting the control bit will select the trigger condition to be a negative edge on that particular L Port pin. Resetting the bit selects the trigger condition to be a positive edge. Changing an edge select entails several steps in order to avoid a Wakeup condition as a result of the edge change. First, the associated WKEN bit should be reset, followed by the edge select change in WKEDG. Next, the associated WKPND bit should be cleared, followed by the associated WKEN bit being re-enabled. An example may serve to clarify this procedure. Suppose we wish to change the edge select from positive (low going high) to negative (high going low) for L Port bit 5, where bit 5 has previously been enabled for an input interrupt. The program would be as follows: DS012838-27 DS012838-27 FIGURE 21. Multi-Input Wake Up Logic www.national.com PrintDate=1997/07/14 PrintTime=11:44:07 2277 ds012838 Rev. No. 1 28 Proof 28 The Software trap has the highest priority while the default VIS has the lowest priority. Each of the six maskable inputs has a fixed arbitration ranking and vector. 8.0 Interrupts 8.1 INTRODUCTION The device supports eight vectored interrupts. Interrupt sources include Timer 1, Timer T0, Port L Wakeup, Software Trap, MICROWIRE/PLUS, and External Input. All interrupts force a branch to location 00FF Hex in program memory. The VIS instruction may be used to vector to the appropriate service routine from location 00FF Hex. Figure 22 shows the Interrupt Block Diagram. DS012838-28 DS012838-28 FIGURE 22. Interrupt Block Diagram 29 PrintDate=1997/07/14 PrintTime=11:44:08 2277 ds012838 Rev. No. 1 www.national.com Proof 29 8.0 Interrupts The interrupt service routine stored at location 00FF Hex should use the VIS instruction to determine the cause of the interrupt, and jump to the interrupt handling routine corresponding to the highest priority enabled and active interrupt. Alternately, the user may choose to poll all interrupt pending and enable bits to determine the source(s) of the interrupt. If more than one interrupt is active, the user's program must decide which interrupt to service. Within a specific interrupt service routine, the associated pending bit should be cleared. This is typically done as early as possible in the service routine in order to avoid missing the next occurrence of the same type of interrupt event. Thus, if the same event occurs a second time, even while the first occurrence is still being serviced, the second occurrence will be serviced immediately upon return from the current interrupt routine. An interrupt service routine typically ends with an RETI instruction. This instruction sets the GIE bit back to 1, pops the address stored on the stack, and restores that address to the program counter. Program execution then proceeds with the next instruction that would have been executed had there been no interrupt. If there are any valid interrupts pending, the highest-priority interrupt is serviced immediately upon return from the previous interrupt. (Continued) 8.2 MASKABLE INTERRUPTS All interrupts other than the Software Trap are maskable. Each maskable interrupt has an associated enable bit and pending flag bit. The pending bit is set to 1 when the interrupt condition occurs. The state of the interrupt enable bit, combined with the GIE bit determines whether an active pending flag actually triggers an interrupt. All of the maskable interrupt pending and enable bits are contained in mapped control registers, and thus can be controlled by the software. A maskable interrupt condition triggers an interrupt under the following conditions: 1. The enable bit associated with that interrupt is set. 2. The GIE bit is set. 3. The device is not processing a non-maskable interrupt. (If a non-maskable interrupt is being serviced, a maskable interrupt must wait until that service routine is completed.) An interrupt is triggered only when all of these conditions are met at the beginning of an instruction. If different maskable interrupts meet these conditions simultaneously, the highest priority interrupt will be serviced first, and the other pending interrupts must wait. Upon Reset, all pending bits, individual enable bits, and the GIE bit are reset to zero. Thus, a maskable interrupt condition cannot trigger an interrupt until the program enables it by setting both the GIE bit and the individual enable bit. When enabling an interrupt, the user should consider whether or not a previously activated (set) pending bit should be acknowledged. If, at the time an interrupt is enabled, any previous occurrences of the interrupt should be ignored, the associated pending bit must be reset to zero prior to enabling the interrupt. Otherwise, the interrupt may be simply enabled; if the pending bit is already set, it will immediately trigger an interrupt. A maskable interrupt is active if its associated enable and pending bits are set. An interrupt is an asychronous event which may occur before, during, or after an instruction cycle. Any interrupt which occurs during the execution of an instruction is not acknowledged until the start of the next normally executed instruction is to be skipped, the skip is performed before the pending interrupt is acknowledged. At the start of interrupt acknowledgment, the following actions occur: 1. The GIE bit is automatically reset to zero, preventing any subsequent maskable interrupt from interrupting the current service routine. This feature prevents one maskable interrupt from interrupting another one being serviced. 2. The address of the instruction about to be executed is pushed onto the stack. 3. The program counter (PC) is loaded with 00FF Hex, causing a jump to that program memory location. The device requires seven instruction cycles to perform the actions listed above. If the user wishes to allow nested interrupts, the interrupts service routine may set the GIE bit to 1 by writing to the PSW register, and thus allow other maskable interrupts to interrupt the current service routine. If nested interrupts are allowed, caution must be exercised. The user must write the program in such a way as to prevent stack overflow, loss of saved context information, and other unwanted conditions. www.national.com PrintDate=1997/07/14 PrintTime=11:44:09 2277 ds012838 Rev. No. 1 8.3 VIS INSTRUCTION The general interrupt service routine, which starts at address 00FF Hex, must be capable of handling all types of interrupts. The VIS instruction, together with an interrupt vector table, directs the device to the specific interrupt handling routine based on the cause of the interrupt. VIS is a single-byte instruction, typically used at the very beginning of the general interrupt service routine at address 00FF Hex, or shortly after that point, just after the code used for context switching. The VIS instruction determines which enabled and pending interrupt has the highest priority, and causes an indirect jump to the address corresponding to that interrupt source. The jump addresses (vectors) for all possible interrupts sources are stored in a vector table. The vector table may be as long as 32 bytes (maximum of 16 vectors) and resides at the top of the 256-byte block containing the VIS instruction. However, if the VIS instruction is at the very top of a 256-byte block (such as at 00FF Hex), the vector table resides at the top of the next 256-byte block. Thus, if the VIS instruction is located somewhere between 00FF and 01DF Hex (the usual case), the vector table is located between addresses 01E0 and 01FF Hex. If the VIS instruction is located between 01FF and 02DF Hex, then the vector table is located between addresses 02E0 and 02FF Hex, and so on. Each vector is 15 bits long and points to the beginning of a specific interrupt service routine somewhere in the 32 kbyte memory space. Each vector occupies two bytes of the vector table, with the higher-order byte at the lower address. The vectors are arranged in order of interrupt priority. The vector of the maskable interrupt with the lowest rank is located to 0yE0 (higher-order byte) and 0yE1 (lower-order byte). The next priority interrupt is located at 0yE2 and 0yE3, and so forth in increasing rank. The Software Trap has the highest rank and its vector is always located at 0yFE and 0yFF. The number of interrupts which can become active defines the size of the table. Table 5 shows the types of interrupts, the interrupt arbitration ranking, and the locations of the corresponding vectors in the vector table. 30 Proof 30 8.0 Interrupts or from inadvertent execution of the VIS command outside of the context of an interrupt. It is a good idea to make this vector point to the Software Trap interrupt service routine or some other error handling routine. A normal RETI instruction should not be used in any such routine because the stack might not contain a valid return address. (Continued) The vector table should be filled by the user with the memory locations of the specific interrupt service routines. For example, if the Software Trap routine is located at 0310 Hex, then the vector location 0yFE and -0yFF should contain the data 03 and 10 Hex, respectively. When a Software Trap interrupt occurs and the VIS instruction is executed, the program jumps to the address specified in the vector table. The interrupt sources in the vector table are listed in order of rank, from highest to lowest priority. If two or more enabled and pending interrupts are detected at the same time, the one with the highest priority is serviced first. Upon return from the interrupt service routine, the next highest-level pending interrupt is serviced. If the VIS instruction is executed, but no interrupts are enabled and pending, the lowest-priority interrupt vector is used, and a jump is made to the corresponding address in the vector table. This is an unusual occurrence, and probably the result of an error. It can result from a change in the enable bits or pending flags prior to using the VIS instruction, To ensure reliable operation, the user should always use the VIS instruction to determine the source of an interrupt. Although it is possible to poll the pending bits to detect the source of an interrupt, this practice is not recommended. The use of polling allows the standard arbitration ranking to be altered, but the reliability of the interrupt system is compromised. The polling routine must individually test the enable and pending bits of each maskable interrupt. If a Software Trap interrupt should occur, it will be serviced last, even though it should have the highest priority. Under certain conditions, a Software Trap could be triggered but not serviced, resulting in an inadvertent "locking out" of all maskable interrupts by the Software Trap pending flag. Problems such as this can be avoided by using VIS instruction. TABLE 5. Interrupt Vector Table Arbitration Ranking Vector (Note 18) Source Description Address (Hi-Low Byte) (1) Highest Software INTR Instruction 0yFE­0yFF (2) Reserved Future 0yFC­0yFD (3) External G0 0yFA­0yFB (4) Timer T0 Underflow 0yF8­0yF9 (5) Timer T1 T1A/Underflow 0yF6­0yF7 (6) Timer T1 T1B 0yF4­0yF5 (7) MICROWIRE/PLUS BUSY Low 0yF2­0yF3 (8) Reserved Future 0yF0­0yF1 (9) Reserved Future 0yEE­0yEF (10) Reserved Future 0yEC­0yED (11) Reserved Future 0yEA­0yEB (12) Reserved Future 0yE8­0yE9 (13) Reserved Future 0yE6­0yE7 (14) Reserved Future 0yE4­0yE5 (15) Port L/Wakeup Port L Edge 0yE2­0yE3 (16) Lowest Default VIS Instruction 0yE0­0yE1 Execution without any interrupts Note 18: y is a variable which represents the VIS block. VIS and the vector table must be located in the same 256-byte block except if VIS is located at the last address of a block. In this case, the table must be in the next block. 31 PrintDate=1997/07/14 PrintTime=11:44:13 2277 ds012838 Rev. No. 1 www.national.com Proof 31 8.0 Interrupts mains unchanged. The new PC is therefore pointing to the vector of the active interrupt with the highest arbitration ranking. This vector is read from program memory and placed into the PC which is now pointed to the 1st instruction of the service routine of the active interrupt with the highest arbitration ranking. (Continued) 8.3.1 VIS Execution When the VIS instruction is executed it activates the arbitration logic. The arbitration logic generates an even number between E0 and FE (E0, E2, E4, E6 etc.) depending on which active interrupt has the highest arbitration ranking at the time of the 1st cycle of VIS is executed. For example, if the software trap interrupt is active, FE is generated. If the external interrupt is active and the software trap interrupt is not, then FA is generated and so forth. If the only active interrupt is software trap, than E0 is generated. This number replaces the lower byte of the PC. The upper byte of the PC re- Figure 23 illustrates the different steps performed by the VIS instruction. Figure 24 shows a flowchart for the VIS instruction. The non-maskable interrupt pending flag is cleared by the RPND (Reset Non-Maskable Pending Bit) instruction (under certain conditions) and upon RESET. DS012838-29 DS012838-29 FIGURE 23. VIS Operation www.national.com PrintDate=1997/07/14 PrintTime=11:44:15 2277 ds012838 Rev. No. 1 32 Proof 32 8.0 Interrupts (Continued) DS012838-30 DS012838-30 FIGURE 24. VIS Flowchart 33 PrintDate=1997/07/14 PrintTime=11:44:16 2277 ds012838 Rev. No. 1 www.national.com Proof 33 8.0 Interrupts (Continued) Programming Example: External Interrupt = 00EF PSW = 00EE CNTRL RBIT 0,PORTGC RBIT 0,PORTGD SBIT IEDG, CNTRL SBIT GIE, PSW SBIT EXEN, PSW WAIT: JP WAIT . . . . = 0FF VIS . . . . = 01FA .ADDRW SERVICE ; ; ; ; ; G0 pin configured Hi-Z Ext interrupt polarity; falling edge Set the GIE bit Enable the external interrupt Wait for external interrupt ; The interrupt causes a ; branch to address 0FF ;The VIS causes a branch to ;interrupt vector table ; Vector table (within 256 byte ; of VIS inst.) containing the ext ;interrupt service routine . . . SERVICE: RBIT, EXPND, PSW . . . RET I ; Interrupt Service Routine ; Reset ext interrupt pend. bit ; Return, set the GIE bit www.national.com PrintDate=1997/07/14 PrintTime=11:44:29 2277 ds012838 Rev. No. 1 34 Proof 34 8.0 Interrupts STPND flag will have the wrong state. This will allow maskable interrupts to be acknowledged during the servicing of the first Software Trap. To avoid problems such as this, the user program should contain the Software Trap routine to perform a recovery procedure rather than a return to normal execution. (Continued) 8.4 NON-MASKABLE INTERRUPT 8.4.1 Pending Flag There is a pending flag bit associated with the non-maskable interrupt, called STPND. This pending flag is not memory-mapped and cannot be accessed directly by the software. The pending flag is reset to zero when a device Reset occurs. When the non-maskable interrupt occurs, the associated pending bit is set to 1. The interrupt service routine should contain an RPND instruction to reset the pending flag to zero. The RPND instruction always resets the STPND flag. Under normal conditions, the STPND flag is reset by a RPND instruction in the Software Trap service routine. If a programming error or hardware condition (brownout, power supply glitch, etc.) sets the STPND flag without providing a way for it to be cleared, all other interrupts will be locked out. To alleviate this condition, the user can use extra RPND instructions in the main program and in the WATCHDOG service routine (if present). There is no harm in executing extra RPND instructions in these parts of the program. 8.5 PORT L INTERRUPTS Port L provides the user with an additional eight fully selectable, edge sensitive interrupts which are all vectored into the same service subroutine. The interrupt from Port L shares logic with the wake up circuitry. The register WKEN allows interrupts from Port L to be individually enabled or disabled. The register WKEDG specifies the trigger condition to be either a positive or a negative edge. Finally, the register WKPND latches in the pending trigger conditions. The GIE (Global Interrupt Enable) bit enables the interrupt function. A control flag, LPEN, functions as a global interrupt enable for Port L interrupts. Setting the LPEN flag will enable interrupts and vice versa. A separate global pending flag is not needed since the register WKPND is adequate. Since Port L is also used for waking the device out of the HALT or IDLE modes, the user can elect to exit the HALT or IDLE modes either with or without the interrupt enabled. If he elects to disable the interrupt, then the device will restart execution from the instruction immediately following the instruction that placed the microcontroller in the HALT or IDLE modes. In the other case, the device will first execute the interrupt service routine and then revert to normal operation. (See HALT MODE for clock option wakeup information.) 8.4.2 Software Trap The Software Trap is a special kind of non-maskable interrupt which occurs when the INTR instruction (used to acknowledge interrupts) is fetched from program memory and placed in the instruction register. This can happen in a variety of ways, usually because of an error condition. Some examples of causes are listed below. If the program counter incorrectly points to a memory location beyond the available program memory space, the non-existent or unused memory location returns zeroes which is interpreted as the INTR instruction. If the stack is popped beyond the allowed limit (address 02F or 06F Hex), a Software Trap is triggered. A Software Trap can be triggered by a temporary hardware condition such as a brownout or power supply glitch. The Software Trap has the highest priority of all interrupts. When a Software Trap occurs, the STPND bit is set. The GIE bit is not affected and the pending bit (not accessible by the user) is used to inhibit other interrupts and to direct the program to the ST service routine with the VIS instruction. Nothing can interrupt a Software Trap service routine except for another Software Trap. The STPND can be reset only by the RPND instruction or a chip Reset. The Software Trap indicates an unusual or unknown error condition. Generally, returning to normal execution at the point where the Software Trap occurred cannot be done reliably. Therefore, the Software Trap service routine should reinitialize the stack pointer and perform a recovery procedure that restarts the software at some known point, similar to a device Reset, but not necessarily performing all the same functions as a device Reset. The routine must also execute the RPND instruction to reset the STPND flag. Otherwise, all other interrupts will be locked out. To the extent possible, the interrupt routine should record or indicate the context of the device so that the cause of the Software Trap can be determined. If the user wishes to return to normal execution from the point at which the Software Trap was triggered, the user must first execute RPND, followed by RETSK rather than RETI or RET. This is because the return address stored on the stack is the address of the INTR instruction that triggered the interrupt. The program must skip that instruction in order to proceed with the next one. Otherwise, an infinite loop of Software Traps and returns will occur. Programming a return to normal execution requires careful consideration. If the Software Trap routine is interrupted by another Software Trap, the RPND instruction in the service routine for the second Software Trap will reset the STPND flag; upon return to the first Software Trap routine, the 8.6 INTERRUPT SUMMARY The device uses the following types of interrupts, listed below in order of priority: 1. The Software Trap non-maskable interrupt, triggered by the INTR (00 opcode) instruction. The Software Trap is acknowledged immediately. This interrupt service routine can be interrupted only by another Software Trap. The Software Trap should end with two RPND instructions followed by a restart procedure. 2. Maskable interrupts, triggered by an on-chip peripheral block or an external device connected to the device. Under ordinary conditions, a maskable interrupt will not interrupt any other interrupt routine in progress. A maskable interrupt routine in progress can be interrupted by the non-maskable interrupt request. A maskable interrupt routine should end with an RETI instruction. 9.0 WATCHDOG/Clock Monitor The devices contain a user selectable WATCHDOG and clock monitor. The following section is applicable only if WATCHDOG feature has been selected in the ECON regis- 35 PrintDate=1997/07/14 PrintTime=11:44:32 2277 ds012838 Rev. No. 1 www.national.com Proof 35 9.0 WATCHDOG/Clock Monitor 9.2 WATCHDOG/CLOCK MONITOR OPERATION The WATCHDOG is enabled by bit 2 of the ECON register. When this ECON bit is 0, the WATCH