C1996 DD12865 RRD-B30M106 COP8ACC520M9 COP8ACC520N8 COP8ACC520M6 COP8ACC528N9 - Datasheet Archive

 

COP8ACC5 8-Bit Microcontroller with High Resolution A D Conversion General Description The COP8ACC5 is a member of the COP8TM

 

October 1996 COP8ACC5 8-Bit Microcontroller with High Resolution A D Conversion General Description The COP8ACC5 is a member of the COP8TM 8-bit Microcontroller family It is a fully static Microcontroller fabricated using double-metal silicon gate microCMOS technology (Continued) Y CPU Instruction Set Features Y Y Key Features Y Y Y Y Analog Function Block for high resolution A D including Analog comparator with seven input muxes Constant Current Source and VCC 2 Reference 16-bit capture timer (upcounter) clocked from CKI with auto reset on timer startup Quiet design (reduced radiated emissions) 4096 bytes on-board ROM 128 bytes on-board RAM Y Y Y Additional Peripheral Features Y Y Y Y Y Idle Timer One 16-bit timer with two 16-bit registers supporting Processor Independent PWM mode External Event counter mode Input Capture mode Multi-Input Wake-Up (MIWU) with optional interrupts (4) WATCHDOGTM and clock monitor logic MICROWIRE PLUSTM serial I O with programmable shift clock-polarity Y Y Y Y Y Y Y Y Low current drain (typically k 5 mA) Two power saving modes HALT and IDLE Single supply operation 2 5V to 5 5V Temperature ranges 0 C to a 70 C b40 C to a 85 C b 55 C to a 125 C Development System Y Memory mapped I O Software selectable I O options (TRI-STATE Output Push-Pull Output Weak Pull-Up Input High Impedance Input) High current outputs Schmitt Trigger inputs on ports G and L 1 ms instruction cycle time Eight multi-source vectored interrupt servicing External Interrupt Idle Timer T0 Timer T1 associated Interrupts MICROWIRE PLUS Multi-Input Wake Up Software Trap Default VIS A D (Capture Timer) Versatile and easy to use instruction set 8-bit Stack Pointer (SP) stack in RAM Two 8-bit Registers Indirect Data Memory Pointers (B and X) Fully Static CMOS Y I O Features Packages 28 DIP SO with 24 I O pins 20 SO with 16 I O pins Emulation and OTP devices Real time emulation and full program debug offered by MetaLink development system Applications Y Y Y Battery Chargers Appliances Data Acquisition systems TRI-STATE is a registered trademark of National Semiconductor Corporation MICROWIRE PLUSTM COP8TM MICROWIRETM and WATCHDOGTM are trademarks of National Semiconductor Corporation IBM PC and PC-XT are registered trademarks of International Business Machines Corporation iceMASTERTM is a trademark of MetaLink Corporation C1996 C1996 National Semiconductor Corporation TL DD12865 DD12865 RRD-B30M106 RRD-B30M106 Printed in U S A http www national com COP8ACC5 8-Bit Microcontroller with High Resolution A D Conversion PRELIMINARY Block Diagram TL DD 12865 ­ 1 FIGURE 1 Block Diagram http www national com 2 General Description (Continued) tecture MICROWIRE PLUS serial I O one 16-bit PWM-timer with two autoreload registers multi-sourced interrupts an Analog Function Block and an idle timer WATCHDOG Each I O pin has software selectable options to adapt the device to the specific application The device operates over a voltage range of 2 5V to 5 5V High throughput is achieved with an efficient regular instruction set operating at a minimum of 2 ms per instruction cycle Low radiated emissions are achieved by gradual turn-on output drivers and internal ICC smoothing filters on the chip logic and crystal oscillator The device provides up to 6 channels of A D performing a measurement with 12 bits of resolution in less than 0 5 ms at a clock-rate of 10 MHz There is only an external capacitor required to complete the measurement setup and establishing low cost high-resolution (up to 16 bits) and accurate A D This device is a complete microcomputer containing all system timing interrupt logic ROM RAM and I O necessary to implement dedicated control functions in a variety of applications Features include an 8-bit memory mapped archi- Connection Diagrams TL DD 12865 ­ 3 Top View Order Number COP8ACC520M9 COP8ACC520M9 COP8ACC520N8 COP8ACC520N8 or COP8ACC520M6 COP8ACC520M6 See NS Molded Package Number M20B TL DD 12865 ­ 2 Top View Order Number COP8ACC528N9 COP8ACC528N9 COP8ACC528N8 COP8ACC528N8 or COP8ACC528N6 COP8ACC528N6 See NS Molded Package Number N28A Order Number COP8ACC528M9 COP8ACC528M9 COP8ACC528M8 COP8ACC528M8 or COP8ACC528M6 COP8ACC528M6 See NS Molded Package Number M28B FIGURE 2 3 http www national com Connection Diagrams (Continued) Pinouts for 28-Pin 20-Pin Packages Port Type Alt Fun Alt Fun 28-Pin DIP SO L4 I O MIWU Ext Int 4 L5 I O MIWU Ext Int 5 L6 I O MIWU Ext Int 6 L7 I O MIWU Ext Int 7 G0 I O INT G1 WDOUT G2 I O G3 20-Pin SO 23 15 24 16 T1B 25 17 I O T1A 26 18 G4 I O SO 27 19 G5 I O SK 28 20 G6 I SI 1 1 G7 I CKO HALT Restart 2 2 D0 O 11 7 D1 O 12 8 D2 O 13 9 D3 O 14 I0 I Analog CH1 15 10 I1 I ISRC 16 11 I2 I Analog CH2 17 12 I3 I Analog CH3 18 13 I4 I Analog CH4 19 14 I5 I Analog CH5 20 I6 I Analog CH6 21 I7 I COUT 22 VCC 5 GND 8 4 CKI 3 3 RESET http 9 10 6 www national com 4 Absolute Maximum Ratings Total Current out of GND Pin (Sink) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VCC) Voltage at Any Pin Total Current into VCC Pin (Source) Storage Temperature Range 110 mA b 65 C to a 140 C Note Absolute maximum ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings 7V b 0 3V to VCC a 0 3V 100 mA DC Electrical Characteristics 0 C s TA s a 70 C unless otherwise specified Parameter Operating Voltage Power Supply Ripple (Note 1) Supply Current (Note 2) CKI e 4 MHz CKI e 4 MHz CKI e 1 MHz HALT Current (Note 3) IDLE Current CKI e 4 MHz CKI e 1 MHz Conditions Min Input Pullup Current VCC e 5 5V VIN e 0V G and L Port Input Hysteresis (Note 5) Source (Push-Pull Mode) Sink (Push-Pull Mode) TRI-STATE Leakage mA mA V V V V 0 7 VCC VCC e 5 5V All Others Source (Weak Pull-Up Mode) mA mA 0 8 VCC Hi-Z Input Leakage Sink 8 4 0 2 VCC VCC e 5 5V tC e 2 5 ms VCC e 4V tC e 10 ms mA mA mA 15 05 k5 k3 V V 55 25 14 VCC e 5 5V CKI e 0 MHz VCC e 4V CKI e 0 MHz Units 55 0 1 VCC VCC e 5 5V tC e 2 5 ms VCC e 4V tC e 2 5 ms VCC e 4V tC e 10 ms Input Levels (VIH VIL) RESET Logic High Logic Low CKI All Other Inputs Logic High Logic Low Output Current Levels D Outputs Source Typ 25 Max 0 2 VCC Peak-to-Peak 1 1 mA b 40 b 250 mA 0 35 VCC V 4V VOH e 3 3V 2 5V VOH e 1 8V 4V VOL e 1V 2 5V VOL e 0 4V b0 4 b0 2 VCC e 4V VOH e 2 7V VCC e 2 5V VOH e 1 8V VCC e 4V VOH e 3 3V VCC e 2 5V VOH e 1 8V VCC e 4V VOL e 0 4V VCC e 2 5V VOL e 0 4V b 10 b2 5 b0 4 b0 2 VCC VCC VCC VCC e e e e mA mA mA mA 10 20 mA mA mA mA mA mA 1 mA 15 3 mA mA g 200 VCC e 5 5V b 110 b 33 mA 16 07 1 Allowable Sink Source Current per Pin D Outputs (Sink) All others Maximum Input Current without Latchup (Note 4) Room Temp RAM Retention Voltage Vr 500 ns Rise and Fall Time (min) Input Capacitance (Note 5) 7 pF Load Capacitance on D2 (Note 5) 1000 pF 5 2 V http www national com AC Electrical Characteristics 0 C s TA s a 70 C unless otherwise specified Parameter Instruction Cycle Time (tC) Crystal Resonator R C Oscillator Inputs tSETUP tHOLD Output Propagation Delay (Note 5) tPD1 tPD0 SO SK All Others MICROWIRE Setup Time (tUWS) (Note 5) MICROWIRE Hold Time (tUWH) (Note 5) MICROWIRE Output Propagation Delay (tUPD) Conditions Min 2 5V s VCC s 4V 4V s VCC s 5 5V 2 5V s VCC s 4V 4V s VCC s 5 5V 25 10 75 30 4V s VCC s 5 5V 2 5V s VCC s 4V 4V s VCC s 5 5V 2 5V s VCC s 4V Typ Max Units DC DC DC DC ms ms ms ms 200 500 60 150 ns ns ns ns RL e 2 2k CL e 100 pF 4V s VCC s 5 5V 2 5V s VCC s 4V 4V s VCC s 5 5V 2 5V s VCC s 4V VCC t 4V VCC t 4V VCC t 4V 07 1 75 25 ms ms 1ms ms 220 ns ns ns 20 56 Input Pulse Width (Note 6) Interrupt Input High Time Interrupt Input Low Time Timer 1 2 3 Input High Time Timer 1 2 3 Input Low Time 1 1 1 1 tC tC tC tC Reset Pulse Width 1 ms Note 1 Maximum rate of voltage change must be k 0 5V ms Note 2 Supply current is measured after running 2000 cycles with a square wave CKI input CKO open inputs at rails and outputs open Note 3 The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations Measurement of IDD HALT is done with device neither sourcing or sinking current with L C and G0­G5 programmed as low outputs and not driving a load all outputs programmed low and not driving a load all inputs tied to VCC clock monitor and comparator disabled Parameter refers to HALT mode entered via setting bit 7 of the G Port data register Part will pull up CKI during HALT in crystal clock mode Note 4 Pins G6 and RESET are designed with a high voltage input network These pins allow input voltages l VCC and the pins will have sink current to VCC when biased at voltages l VCC (the pins do not have source current when biased at a voltage below VCC) The effective resistance to VCC is 750X (typical) These two pins will not latch up The voltage at the pins must be limited to less than 14V WARNING Voltages in excess of 14V will cause damage to the pins This warning excludes ESD transients Note 5 The output propagation delay is referenced to the end of the instruction cycle where the output change occurs Note 6 Parameter characterized but not tested Note 7 tC e Instruction Cycle Time http www national com 6 Absolute Maximum Ratings Total Current out of GND Pin (Sink) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VCC) Voltage at Any Pin Total Current into VCC Pin (Source) Storage Temperature Range 110 mA b 65 C to a 140 C Note Absolute maximum ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings 7V b 0 3V to VCC a 0 3V 100 mA DC Electrical Characteristics b40 C s TA s a 85 C unless otherwise specified Parameter Conditions Min HALT Current (Note 3) IDLE Current CKI e 4 MHz CKI e 1 MHz VCC e 5 5V tC e 2 5 ms VCC e 4V tC e 10 ms Input Levels (VIH VIL) RESET Logic High Logic Low CKI All Other Inputs Logic High Logic Low Input Pullup Current VCC e 5 5V VIN e 0V G and L Port Input Hysteresis (Note 5) All Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) TRI-STATE Leakage mA mA V V V V 0 7 VCC VCC e 5 5V Sink mA mA 0 8 VCC Hi-Z Input Leakage Output Current Levels D Outputs Source 10 6 0 2 VCC k5 k3 mA mA mA 15 05 VCC e 5 5V CKI e 0 MHz VCC e 4V CKI e 0 MHz V V 55 25 14 VCC e 5 5V tC e 2 5 ms VCC e 4V tC e 2 5 ms VCC e 4V tC e 10 ms Units 55 0 1 VCC Peak-to-Peak Supply Current (Note 2) CKI e 4 MHz CKI e 4 MHz CKI e 1 MHz Typ 25 Max 0 2 VCC Operating Voltage Power Supply Ripple (Note 1) b2 a2 mA b 40 b 250 mA 0 35 VCC V VCC VCC VCC VCC e e e e 4V VOH e 3 3V 2 5V VOH e 1 8V 4V VOL e 1V 2 5V VOL e 0 4V b0 4 b0 2 VCC VCC VCC VCC VCC VCC e e e e e e 4V VOH e 2 7V 2 5V VOH e 1 8V 4V VOH e 3 3V 2 5V VOH e 1 8V 4V VOL e 0 4V 2 5V VOL e 0 4V b 10 b2 5 b0 4 b0 2 mA mA mA mA 10 20 mA mA mA mA mA mA a2 mA 15 3 mA mA g 200 VCC e 5 5V b 110 b 33 mA 16 07 b2 Allowable Sink Source Current per Pin D Outputs (Sink) All others Maximum Input Current without Latchup (Note 4) Room Temp RAM Retention Voltage Vr 500 ns Rise and Fall Time (min) Input Capacitance (Note 5) 7 pF Load Capacitance on D2 (Note 5) 1000 pF 7 2 V http www national com AC Electrical Characteristics b40 C s TA s a 85 C unless otherwise specified Parameter Instruction Cycle Time (tC) Crystal Resonator R C Oscillator Inputs tSETUP tHOLD Output Propagation Delay (Note 5) tPD1 tPD0 SO SK All Others MICROWIRE Setup Time (tUWS) (Note 5) MICROWIRE Hold Time (tUWH) (Note 5) MICROWIRE Output Propagation Delay (tUPD) Conditions Min 2 5V s VCC k 4V 4V s VCC s 5 5V 2 5V s VCC k 4V 4V s VCC k 5 5V 25 10 75 30 4V s VCC s 5 5V 2 5V s VCC k 4V 4V s VCC s 5 5V 2 5V s VCC k 4V Typ Max Units DC DC DC DC ms ms ms ms 200 500 60 150 ns ns ns ns RL e 2 2k CL e 100 pF 4V s VCC s 5 5V 2 5V s VCC k 4V 4V s VCC s 5 5V 2 5V s VCC k 4V VCC t 4V VCC t 4V VCC t 4V 07 1 75 1 25 ms ms ms ms 220 ns ns ns 20 56 Input Pulse Width (Note 6) Interrupt Input High Time Interrupt Input Low Time Timer 1 2 3 Input High Time Timer 1 2 3 Input Low Time 1 1 1 1 tC tC tC tC Reset Pulse Width 1 ms Note 1 Maximum rate of voltage change must be k 0 5 V ms Note 2 Supply current is measured after running 2000 cycles with a square wave CKI input CKO open inputs at rails and outputs open Note 3 The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations Measurement of IDD HALT is done with device neither sourcing or sinking current with L C and G0­G5 programmed as low outputs and not driving a load all outputs programmed low and not driving a load all inputs tied to VCC clock monitor and comparator disabled Parameter refers to HALT mode entered via setting bit 7 of the G Port data register Part will pull up CKI during HALT in crystal clock mode Note 4 Pins G6 and RESET are designed with a high voltage input network These pins allow input voltages l VCC and the pins will have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC) The effective resistance to VCC is 750X (typical) These two pins will not latch up The voltage at the pins must be limited to less than 14V WARNING Voltages in excess of 14V will cause damage to the pins This warning excludes ESD transients Note 5 The output propagation delay is referenced to the end of the instruction cycle where the output change occurs Note 6 Parameter characterized but not tested Note 7 tC e Instruction Cycle Time http www national com 8 Absolute Maximum Ratings Total Current into VCC Pin (Source) Supply Voltage (VCC) Voltage at Any Pin 100 mA Total Current out of GND Pin (Sink) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications 110 mA b 65 C to a 140 C Storage Temperature Range Note Absolute maximum ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings 7V b 0 3V to VCC a 0 3V DC Electrical Characteristics b55 C s TA s a 125 C unless otherwise specified Parameter Conditions Min VCC e 5 5V tC e 2 5 ms Input Levels (VIH VIL) RESET Logic High Logic Low CKI All Other Inputs Logic High Logic Low mA mA mA V V 0 2 VCC IDLE Current CKI e 4 MHz k5 30 15 VCC e 5 5V CKI e 0 MHz V V 55 VCC e 5 5V tC e 2 5 ms HALT Current (Note 3) Units 55 0 1 VCC Peak-to-Peak Supply Current (Note 2) CKI e 4 MHz Typ 45 Max 0 2 VCC Operating Voltage Power Supply Ripple (Note 1) V V 0 8 VCC 0 7 VCC Hi-Z Input Leakage VCC e 5 5V 5 5 mA Input Pullup Current VCC e 5 5V VIN e 0V 35 400 mA G and L Port Input Hysteresis (Note 5) 0 35 VCC V Output Current Levels D Outputs Source Sink All Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) TRI-STATE Leakage VCC e 4 5V VOH e 3 3V VCC e 4 5V VOL e 1V b0 4 VCC e 4 5V VOH e 2 7V VCC e 4 5V VOH e 3 3V VCC e 4 5V VOL e 0 4V VCC e 5 5V b 10 b0 4 mA mA 10 b 110 a2 mA mA mA mA 15 3 mA mA g 200 mA 16 b2 Allowable Sink Source Current per Pin D Outputs (Sink) All others Maximum Input Current without Latchup (Note 4) Room Temp RAM Retention Voltage Vr 500 ns Rise and Fall Time (min) Input Capacitance (Note 5) 7 pF Load Capacitance on D2 (Note 5) 1000 pF 9 2 V http www national com AC Electrical Characteristics b55 C s TA s a 125 C unless otherwise specified Parameter Conditions Min Instruction Cycle Time (tC) Crystal Resonator R C Oscillator 4 5V s VCC s 5 5V 4 5V s VCC s 5 5V 10 30 Inputs tSETUP tHOLD 4 5 s VCC s 5 5V 4 5V s VCC s 5 5V Typ Max Units DC DC ms ms 200 60 Output Propagation Delay (Note 5) tPD1 tPD0 SO SK All Others 4 5V s VCC s 5 5V 4 5V s VCC s 5 5V MICROWIRE Setup Time (tUWS) (Note 5) MICROWIRE Hold Time (tUWH) (Note 5) MICROWIRE Output Propagation Delay (tUPD) VCC t 4 5V VCC t 4 5V VCC t 4 5V ns ns RL e 2 2k CL e 100 pF 07 1 ms ms 220 ns ns ns 20 56 Input Pulse Width (Note 6) Interrupt Input High Time Interrupt Input Low Time Timer 1 2 3 Input High Time Timer 1 2 3 Input Low Time 1 1 1 1 tC tC tC tC Reset Pulse Width 1 ms Note 1 Maximum rate of voltage change must be k 0 5V ms Note 2 Supply current is measured after running 2000 cycles with a square wave CKI input CKO open inputs at rails and outputs open Note 3 The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations Measurement of IDD HALT is done with device neither sourcing or sinking current with L C and G0­G5 programmed as low outputs and not driving a load all outputs programmed low and not driving a load all inputs tied to VCC clock monitor and comparator disabled Parameter refers to HALT mode entered via setting bit 7 of the G Port data register Part will pull up CKI during HALT in crystal clock mode Note 4 Pins G6 and RESET are designed with a high voltage input network These pins allow input voltages l VCC and the pins will have sink current to VCC when biased at voltages l VCC (the pins do not have source current when biased at a voltage below VCC) The effective resistance to VCC is 750X (typical) These two pins will not latch up The voltage at the pins must be limited to less than 14V WARNING Voltages in excess of 14V will cause damage to the pins This warning excludes ESD transients Note 5 The output propagation delay is referenced to the end of the instruction cycle where the output change occurs Note 6 Parameter characterized but not tested Note 7 tC e Instruction Cycle Time http www national com 10 Comparator AC and DC Characteristics VCC e 5V Parameter Input Offset Voltage Conditions b 40 C s TA s a 85 C Min Typ Input Common Mode Voltage Range (Note 8) Max Units 10 0 4V k VIN k VCC b1 5V 25 mV 04 VCC b1 5 Voltage Gain 300k VCC 2 Reference 4 0V k VCC k 5 5V DC Supply Current For Comparator (when enabled) VCC e 5 5V DC Supply Current For VCC 2 reference (when enabled) VCC 5 5V DC Supply Current For Constant Current Source (when enabled) VCC e 5 5V Constant Current Source 4 0V k VCC k 5 5V Current Source Variation 0 5 VCC b0 04 4 0V k VCC k 5 5V Temp e Constant 10 10 mV overdrive 100 pF load 80 mA mA 40 mA mA 2 ms 1 15 mA 2 20 V 200 50 0 5VCC a 0 04 250 Current Source Enable Time Comparator Response Time 0 5VCC V V V ms Note 8 The device is capable of operating over a common mode voltage range of 0 to VCC b 1 5V however increased offset voltage will be observed between 0V and 0 4V TL DD 12865 ­ 4 FIGURE 2 MICROWIRE PLUS Timing 11 http www national com Pin Descriptions VCC and GND are the power supply pins All VCC and GND pins must be connected CKI is the clock input This can come from an R C generated oscillator or a crystal oscillator (in conjunction with CKO) See Oscillator Description section RESET is the master reset input See Reset description section The device contains two bidirectional (one 8-bit one 4-bit) I O ports (G and L) where each individual bit may be independently configured as an input (Schmitt trigger inputs on ports L and G) output or TRI-STATE under program control Three data memory address locations are allocated for each of these I O ports Each I O port has two associated 8-bit memory mapped registers the CONFIGURATION register and the output DATA register A memory mapped address is also reserved for the input pins of each I O port (See the memory map for the various addresses associated with the I O ports ) Figure 3 shows the I O port configurations The DATA and CONFIGURATION registers allow for each port bit to be individually configured under software control as shown below PORT L is a 4-bit I O port All L-pins have Schmitt triggers on the inputs The Port L supports Multi-Input Wake Up on all four pins The Port L has the following alternate features L4 MIWU or external interrupt L5 MIWU or external interrupt L6 MIWU or external interrupt L7 MIWU or external interrupt Configuration Data Register Register Port Set-Up 0 0 Hi-Z Input (TRI-STATE Output) 0 1 Input with Weak Pull-Up 1 0 Push-Pull Zero Output 1 1 Push-Pull One Output Please note The lower 4 L-bits read all ones (L0 L3) This is independant from the states of the associated bits in the L-port Data- and Configuration register The lower 4 bits in the L-port Data- and Configuration register can be used as general purpose status indicators (flags) Port G is an 8-bit port with 5 I O pins (G0 G2 ­ G5) an input pin (G6) and a dedicated output pin (G7) Pins G0 and G2 ­ G6 all have Schmitt Triggers on their inputs Pin G1 serves as the dedicated WDOUT WATCHDOG output while pin G7 is either input or output depending on the oscillator mask option selected With the crystal oscillator option selected G7 serves as the dedicated output pin for the CKO clock output With the single-pin R C oscillator mask option selected G7 serves as a general purpose input pin but is also used to bring the device out of HALT mode with a low to high transition on G7 There are two registers associated with the G Port a data register and a configuration register Therefore each of the 5 I O bits (G0 G2 ­ G5) can be individually configured under software control Since G6 is an input only pin and G7 is the dedicated CKO clock output pin (crystal clock option) or general purpose input (R C clock option) the associated bits in the data and configuration registers for G6 and G7 are used for special purpose functions as outlined below Reading the G6 and G7 data bits will return zeros Note that the chip will be placed in the HALT mode by writing a ``1'' to bit 7 of the Port G Data Register Similarly the chip will be placed in the IDLE mode by writing a ``1'' to bit 6 of the Port G Data Register Writing a ``1'' to bit 6 of the Port G Configuration Register enables the MICROWIRE PLUS to operate with the alternate phase of the SK clock The G7 configuration bit if set high enables the clock start up delay after HALT when the R C clock configuration is used Config Reg CLKDLY HALT G6 FIGURE 3 I P Port Configurations Data Reg G7 TL DD 12865­5 Alternate SK IDLE Port G has the following alternate features G0 G2 G3 G4 G5 G6 Port G1 http www national com 12 INTR (External Interrupt Input) T1B (Timer T1 Capture Input) T1A (Timer T1 I O) SO (MICROWIRE Serial Data Output) SK (MICROWIRE Serial Clock) SI (MICROWIRE Serial Data Input) G has the following dedicated functions WDOUT WATCHDOG and or Clock Monitor dedicated output Pin Descriptions (Continued) G7 CKO Oscillator dedicated output or general purpose input DATA MEMORY The data memory address space includes the on-chip RAM and data registers the I O registers (Configuration Data and Pin) the control registers the MICROWIRE PLUS SIO shift register and the various registers and counters associated with the timers (with the exception of the IDLE timer) Data memory is addressed directly by the instruction or indirectly by the B X SP pointers and S register The data memory consists of 128 bytes of RAM Sixteen bytes of RAM are mapped as ``registers'' at addresses 0F0 to 0FF Hex These registers can be loaded immediately and also decremented and tested with the DRSZ (decrement register and skip if zero) instruction The memory pointer registers X B and SP are memory mapped into this space at address locations 0FC to 0FF Hex respectively with the other registers being available for general usage The instruction set permits any bit in memory to be set reset or tested All I O and registers (except A and PC) are memory mapped therefore I O bits and register bits can be directly and individually set reset and tested The accumulator (A) bits can also be directly and individually tested Port I is an eight-bit Hi-Z input port Port I0 ­ I7 are used for the analog function block The Port I has the following alternate features I0 COMPIN1 a (Comparator Positive Input 1) I1 COMPINb (Comparator Negative Input Current Source Out) I2 COMPIN0 a (Comparator Positive Input 0) I3 COMPOUT COMPIN2 a (Comparator Output Comparator Positive Input 2) I4 COMPIN3 a (Comparator Positive Input 3) I5 COMPIN4 a (Comparator Positive Input 4) I6 COMPIN5 a (Comparator Positive Input 5) I7 COMPOUT (Comparator Output) Port D is a 4-bit output port that is preset high when RESET goes low The user can tie two or more D port outputs (except D2) together in order to get a higher drive Functional Description Note RAM contents are undefined upon power-up The architecture of the device is a modified Harvard architecture With the Harvard architecture the control store program memory (ROM) is separated from the data store memory (RAM) Both ROM and RAM have their own separate addressing space with separate address buses The architecture though based on the Harvard architecture permits transfer of data from ROM to RAM Reset The RESET input when pulled low initializes the microcontroller Initialization will occur whenever the RESET input is pulled low Upon initialization the data and configuration registers for ports L and G are cleared resulting in these Ports being initialized to the TRI-STATE mode Pin G1 of the G Port is an exception (as noted below) since pin G1 is dedicated as the WATCHDOG and or Clock Monitor error output pin Port D is set high The PC PSW ICNTRL and CNTRL-control registers are cleared The Comparator Select Register is cleared The S register is initialized to zero The Multi-Input Wakeup registers WKEN and WKEDG are cleared Wakeup register WKPND is unknown The stack pointer SP is initialized to 6F Hex The device comes out of reset with both the WATCHDOG logic and the Clock Monitor detector armed with the WATCHDOG service window bits set and the Clock Monitor bit set The WATCHDOG and Clock Monitor circuits are inhibited during reset The WATCHDOG service window bits being initialized high default to the maximum WATCHDOG service window of 64k tC clock cycles The Clock Monitor bit being initialized high will cause a Clock Monitor error following reset if the clock has not reached the minimum specified frequency at the termination of reset A Clock Monitor error will cause an active low error output on pin G1 This error output will continue until 16 tC-32 tC clock cycles following the clock frequency reaching the minimum specified value at which time the G1 output will enter the TRI-STATE mode The external RC network shown in Figure 4 should be used to ensure that the RESET pin is held low until the power supply to the chip stabilizes CPU REGISTERS The CPU can do an 8-bit addition subtraction logical or shift operation in one instruction (tC) cycle time There are six CPU registers A is the 8-bit Accumulator Register PC is the 15-bit Program Counter Register PU is the upper 7 bits of the program counter (PC) PL is the lower 8 bits of the program counter (PC) B is an 8-bit RAM address pointer which can be optionally post auto incremented or decremented X is an 8-bit alternate RAM address pointer which can be optionally post auto incremented or decremented SP is the 8-bit stack pointer which points to the subroutine interrupt stack (in RAM) The SP is initialized to RAM address 06F with reset All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC) PROGRAM MEMORY The program memory consists of 4096 bytes of ROM These bytes may hold program instructions or constant data (data tables for the LAID instruction jump vectors for the JID instruction and interrupt vectors for the VIS instruction) The program memory is addressed by the 15-bit program counter (PC) All interrupts in the device vector to program memory location 0FF Hex Oscillator Circuits The chip can be driven by a clock input on the CKI input pin which can be between DC and 10 MHz The CKO output clock is on pin G7 (crystal configuration) The CKI input frequency is divided down by 10 to produce the instruction cycle clock (tC) 13 http www national com Oscillator Circuits (Continued) Control Registers CNTRL Register (Address X'00EE) The Timer1 (T1) and MICROWIRE PLUS control register contains the following bits SL1 and SL0 Select the MICROWIRE PLUS clock divide by (00 e 2 01 e 4 1x e 8) IEDG External interrupt edge polarity select (0 e Rising edge 1 e Falling edge) MSEL Selects G5 and G4 as MICROWIRE PLUS signals SK and SO respectively T1C0 Timer T1 Start Stop control in timer modes 1 and 2 T1 Underflow Interrupt Pending Flag in timer mode 3 T1C1 Timer T1 mode control bit T1C2 Timer T1 mode control bit T1C3 Timer T1 mode control bit TL DD 12865­6 RC l 5 x POWER SUPPLY RISE TIME FIGURE 4 Recommended Reset Circuit Figure 5 shows the Crystal and R C Oscillator diagrams CRYSTAL OSCILLATOR CKI and CKO can be connected to make a closed loop crystal (or resonator) controlled oscillator Table I shows the component values required for various standard crystal values T1C3 TABLE I Crystal Oscillator Configuration TA e 25 C T1C2 T1C1 T1C0 MSEL IEDG SL1 Bit 7 R1 (kX) R2 (MX) C1 (pF) C2 (pF) CKI Freq (MHz) Conditions 0 1 30 30­36 10 VCC e 5V 0 1 30 30­36 4 VCC e 5V 0 1 200 100­150 0 455 VCC e 5V PSW Register (Address X'00EF) The PSW register contains the following select bits GIE Global interrupt enable (enables interrupts) EXEN Enable external interrupt BUSY MICROWIRE PLUS busy shifting flag EXPND External interrupt pending T1ENA Timer T1 Interrupt Enable for Timer Underflow or T1A Input capture edge T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA in mode 1 T1 Underflow in Mode 2 T1A capture edge in mode 3) C Carry Flag HC Half Carry Flag R C OSCILLATOR By selecting CKI as a single pin oscillator input a single pin R C oscillator circuit can be connected to it CKO is available as a general purpose input and or HALT restart input Note Use of the R C oscillator option will result in higher electromagnetic emissions Table II shows the variation in the oscillator frequencies as functions of the component (R and C) values TABLE II RC Oscillator Configuration TA e 25 C HC C T1PNDA T1ENA Bit 7 R (kX) C (pF) CKI Freq (MHz) Instr Cycle (ms) Conditions 33 82 2 2 to 2 7 3 7 to 4 6 VCC e 5V 56 100 1 1 to 1 3 7 4 to 9 0 VCC e 5V 68 100 0 9 to 1 1 8 8 to 10 8 SL0 Bit 0 VCC e 5V EXPND BUSY EXEN GIE Bit 0 The Half-Carry flag is also affected by all the instructions that affect the Carry flag The SC (Set Carry) and RC (Reset Carry) instructions will respectively set or clear both the carry flags In addition to the SC and RC instructions ADC SUBC RRC and RLC instructions affect the Carry and Half Carry flags Note 3k s R s 200k 50 pF s C s 200 pF TL DD 12865 ­ 7 TL DD 12865 ­ 19 FIGURE 5 Crystal and R C Oscillator Diagrams http www national com 14 Control Registers (Continued) Figure 6 is a functional block diagram showing the structure of the IDLE Timer and its associated interrupt logic Bits 11 through 15 of the ITMR register can be selected for triggering the IDLE Timer interrupt Each time the selected bit underflows (every 4k 8k 16k 32k or 64k instruction cycles) the IDLE Timer interrupt pending bit T0PND is set thus generating an interrupt (if enabled) and bit 6 of the Port G data register is reset thus causing an exit from the IDLE mode if the device is in that mode In order for an interrupt to be generated the IDLE Timer interrupt enable bit T0EN must be set and the GIE (Global Interrupt Enable) bit must also be set The T0PND flag and T0EN bit are bits 5 and 4 of the ICNTRL register respectively The interrupt can be used for any purpose Typically it is used to perform a task upon exit from the IDLE mode For more information on the IDLE mode refer to the Power Save Modes section The Idle Timer period is selected by bits 0 ­ 2 of the ITMR register Bits 3 ­ 7 of the ITMR Register are reserved and should not be used as software flags ICNTRL Register (Address X'00E8) The ICNTRL register contains the following bits T1ENB Timer T1 Interrupt Enable for T1B Input capture edge T1PNDB Timer T1 Interrupt Pending Flag for T1B capture edge mWEN Enable MICROWIRE PLUS interrupt mWPND MICROWIRE PLUS interrupt pending T0EN Timer T0 Interrupt Enable (Bit 12 toggle) T0PND Timer T0 Interrupt pending LPEN L Port Interrupt Enable (Multi-Input Wakeup Interrupt) Bit 7 could be used as a flag Unused LPEN T0PND T0EN WPND WEN T1PNDB T1ENB Bit 7 Bit 0 CAPCNTL Register (Address X'00) The CAPCNTL register contains the following bits CAPIEN Capture Interrupts enable CAPPND Capture pending CAPOVL Capture Timer overflow CAPRUN Capture Timer Run CAPMOD Reset Timer TABLE III Idle Timer Window Length CAPMOD Bit 7 CAPRUN CAPOVL CAPPND ITSEL1 ITSEL0 Idle Timer Period (Instruction Cycles) 0 0 0 4 096 0 Unused ITSEL2 0 1 8 192 0 1 0 16 384 0 1 1 32 768 1 X X 65 536 CAPIEN Bit 0 Timers The device contains a very versatile set of timers (T0 and T1) All timers and associated autoreload capture registers power up containing random data The ITMR register is cleared on Reset and the Idle Timer period is reset to 4 096 instruction cycles ITMR Register (Address X'0xCF) TIMER T0 (IDLE TIMER) The device supports applications that require maintaining real time and low power with the IDLE mode This IDLE mode support is furnished by the IDLE timer T0 which is a 16-bit timer The Timer T0 runs continuously at the fixed rate of the instruction cycle clock tC The user cannot read or write to the IDLE Timer T0 which is a count down timer The Timer T0 supports the following functions Reserved ITSEL2 ITSEL1 ITSEL0 Bit 7 Bit 0 Any time the IDLE Timer period is changed there is the possibility of generating a spurious IDLE Timer interrupt by setting the T0PND bit The user is advised to disable IDLE Timer interrupts prior to changing the value of the ITSEL bits of the ITMR Register and then clear the T0PND bit before attempting to synchronize operation to the IDLE Timer Exit out of the Idle Mode (See Idle Mode description) WATCHDOG logic (See WATCHDOG description) Start up delay out of the HALT mode 15 http www national com Timers (Continued) TL DD 12865 ­ 8 FIGURE 6 Functional Block Diagram for Idle Timer T0 The T1 Timer control bits T1C3 T1C2 and T1C1 set up the timer for PWM mode operation TIMER T1 The device has a powerful timer counter block The timer consists of a 16-bit timer T1 and two supporting 16-bit autoreload capture registers R1A and R1B The timer block has two pins associated with it T1A and T1B The pin T1A supports I O required by the timer block while the pin T1B is an input to the timer block The powerful and flexible timer block allows the device to easily perform all timer functions with minimal software overhead The timer block has three operating modes Processor Independent PWM mode External Event Counter mode and Input Capture mode The control bits T1C3 T1C2 and T1C1 allow selection of the different modes of operation Figure 7 shows a block diagram of the timer in PWM mode The underflows can be programmed to toggle the T1A output pin The underflows can also be programmed to generate interrupts Underflows from the timer are alternately latched into two pending flags T1PNDA and T1PNDB The user must reset these pending flags under software control Two control enable flags T1ENA and T1ENB allow the interrupts from the timer underflow to be enabled or disabled Setting the timer enable flag T1ENA will cause an interrupt when a timer underflow causes the R1A register to be reloaded into the timer Setting the timer enable flag T1ENB will cause an interrupt when a timer underflow causes the R1B register to be reloaded into the timer Resetting the timer enable flags will disable the associated interrupts Either or both of the timer underflow interrupts may be enabled This gives the user the flexibility of interrupting once per PWM period on either the rising or falling edge of the PWM output Alternatively the user may choose to interrupt on both edges of the PWM output Mode 1 Processor Independent PWM Mode As the name suggests this mode allows the device to generate a PWM signal with very minimal user intervention The user only has to define the parameters of the PWM signal (ON time and OFF time) Once begun the timer block will continuously generate the PWM signal completely independent of the microcontroller The user software services the timer block only when the PWM parameters require updating In this mode the timer T1 counts down at a fixed rate of tC Upon every underflow the timer is alternately reloaded with the contents of supporting registers R1A and R1B The very first underflow of the timer causes the timer to reload from the register R1A Subsequent underflows cause the timer to be reloaded from the registers alternately beginning with the register R1B http www national com 16 Timers (Continued) The trigger conditions can also be programmed to generate interrupts The occurrence of the specified trigger condition on the T1A and T1B pins will be respectively latched into the pending flags T1PNDA and T1PNDB The control flag T1ENA allows the interrupt on T1A to be either enabled or disabled Setting the T1ENA flag enables interrupts to be generated when the selected trigger condition occurs on the T1A pin Similarly the flag T1ENB controls the interrupts from the T1B pin Underflows from the timer can also be programmed to generate interrupts Underflows are latched into the timer T1C0 pending flag (the T1C0 control bit serves as the timer underflow interrupt pending flag in the Input Capture mode) Consequently the T1C0 control bit should be reset when entering the Input Capture mode The timer underflow interrupt is enabled with the T1ENA control flag When a T1A interrupt occurs in the Input Capture mode the user must check both the T1PNDA and T1C0 pending flags in order to determine whether a T1A input capture or a timer underflow (or both) caused the interrupt Mode 2 External Event Counter Mode This mode is quite similar to the processor independent PWM mode previously described The main difference is that the timer T1 is clocked by the input signal from the T1A pin The T1 timer control bits T1C3 T1C2 and T1C1 allow the timer to be clocked either on a positive or negative edge from the T1A pin Underflows from the timer are latched into the T1PNDA pending flag Setting the T1ENA control flag will cause an interrupt when the timer underflows In this mode the input pin T1B can be used as an independent positive edge sensitive interrupt input if the T1ENB control flag is set The occurrence of a positive edge on the T1B input pin is latched into the T1PNDB flag Figure 8 shows a block diagram of the timer in External Event Counter mode Note The PWM output is not available in this mode since the T1A pin is being used as the counter input clock Mode 3 Input Capture Mode The device can precisely measure external frequencies or time external events by placing the timer block T1 in the input capture mode In this mode the timer T1 is constantly running at the fixed tC rate The two registers R1A and R1B act as capture registers Each register acts in conjunction with a pin The register R1A acts in conjunction with the T1A pin and the register R1B acts in conjunction with the T1B pin The timer value gets copied over into the register when a trigger event occurs on its corresponding pin Control bits T1C3 T1C2 and T1C1 allow the trigger events to be specified either as a positive or a negative edge The trigger condition for each input pin can be specified independently TL DD 12865 ­ 10 FIGURE 8 Timer in External Event Counter Mode TL DD 12865 ­ 9 FIGURE 7 Timer in PWM Mode 17 http www national com Timers (Continued) TL DD 12865 ­ 11 FIGURE 9 Timer in Input Capture Mode Figure 9 shows a block diagram of the timer in Input Capture mode HIGH SPEED CAPTURE TIMER The device provides a 16-bit high-speed capture timer The timer consists of a 16-bit up-counter that is clocked with the device clock input frequency (CKI) and an 8-bit control register The 16-bit counter is mapped as two read write 8-bit registers This timer is specifically designed to be used in conjunction with the Analog Function Block (comparator analog multiplexer constant current source) to implement a low-cost high-resolution single-slope A D The timer is automatically stopped in the event of a capture to allow the software to read the timer value Coming out of reset the counter is disabled (stopped) and reads all ``0'' Setting the Capture Timer Run bit CAPRUN bit in the Capture Control Register (CAPCNTL) will start the counter The counter will count up until a capture event (negative edge) is received Upon a capture the counter will be stopped the Capture Pending bit (CAPPND) is set and the CAPRUN bit is automatically reset If capture interrupts are enabled (CAPIEN e 1) the capture event will generate an interrupt Setting the CAPRUN bit again by software will start a new counting cycle If the Capture Mode bit is reset (CAPMOD e 0) the capture timer will be automatically initialized to all ``0'' with each setting of the CAPRUN bit If CAPMOD e 1 the timer will not be cleared when setting the CAPRUN bit thus allowing the user's software to pre-load the timer registers with any desired value This mode can be used in conjunction with the timer's overflow to implement for example a programmable delay counter TIMER CONTROL FLAGS The Timer T1 control bits and their functions are summarized below T1C0 Timer Start Stop control in Modes 1 and 2 (Processor Independent PWM and External Event Counter) where 1 e Start 0 e Stop Timer Underflow Interrupt Pending Flag in Mode 3 (Input Capture) T1PNDA Timer Interrupt Pending Flag T1PNDB Timer Interrupt Pending Flag T1ENA Timer Interrupt Enable Flag T1ENB Timer Interrupt Enable Flag 1 e Timer Interrupt Enabled T1C3 T1C2 T1C1 http 0 e Timer Interrupt Disabled Timer mode control Timer mode control Timer mode control www national com 18 Timers (Continued) The timer mode control bits (T1C3 T1C2 and T1C1) are detailed below TABLE IV Timer Mode Control T1C3 T1C2 T1C1 Timer Mode Interrupt A Source Interrupt B Source Timer Counts On 0 0 0 MODE 2 (External Event Counter) Timer Underflow Pos T1B Edge T1A Pos Edge 0 0 1 MODE 2 (External Event Counter) Timer Underflow Pos T1B Edge T1A Neg Edge 1 0 1 MODE 1 (PWM) T1A Toggle Autoreload RA Autoreload RB tC 1 0 0 MODE 1 (PWM) No T1A Toggle Autoreload RA Autoreload RB tC 0 1 0 MODE 3 (Capture) Captures T1A Pos Edge T1B Pos Edge Pos T1A Edge Timer Underflow Pos T1B Edge tC 1 1 0 MODE 3 (Capture) Captures T1A Pos Edge T1B Neg Edge Pos T1A Edge or Timer Underflow Neg T1B Edge tC 0 1 1 MODE 3 (Capture) Captures T1A Neg Edge T1B Pos Edge Neg T1A Edge or Timer Underflow Pos T1B Edge tC 1 1 1 MODE 3 (Capture) Captures T1A Neg Edge T1B Neg Edge Neg T1A Edge or Timer Underflow Neg T1B Edge tC ``CAPTURE MODE'' is only active when the CAPRUN bit is set i e any capture events received while the timer is stopped (CAPRUN e 0) will be ignored and will not cause the CAPPND bit to be set The capture counter can also be stopped (frozen) by the user's software resetting the CAPRUN bit If the user program tries to set the CAPRUN bit at the same time that the hardware gets a capture event and tries to reset the CAPRUN bit the hardware will have precedence Should the counter overflow before a capture condition occurs the Capture Overflow bit (CAPOVL) bit in the CAPCNTL register will be set If Capture interrupts are enabled (CAPIEN e 1) an overflow will generate an interrupt The user software should reset this bit before the next overflow occurs otherwise subsequent overflow conditions cannot be detected Capture Overflow interrupt and Capture Pending interrupt share the same interrupt vector HALT MODE The device can be placed in the HALT mode by writing a ``1'' to the HALT flag (G7 data bit) All microcontroller activities including the clock and timers are stopped The WATCHDOG logic on the device is disabled during the HALT mode However the clock monitor circuitry if enabled remains active and will cause the WATCHDOG output pin (WDOUT) to go low If the HALT mode is used and the user does not want to activate the WDOUT pin the Clock Monitor should be disabled after the device comes out of reset (resetting the Clock Monitor control bit with the first write to the WDSVR register) In the HALT mode the power requirements of the device are minimal and the applied voltage (VCC) may be decreased to Vr (Vr e 2 0V) without altering the state of the machine The device supports three different ways of exiting the HALT mode The first method of exiting the HALT mode is with the Multi-Input Wakeup feature on the Port L The second method is with a low to high transition on the CKO (G7) pin This method precludes the use of the crystal clock configuration (since CKO becomes a dedicated output) and so may only be used with an RC clock configuration The third method of exiting the HALT mode is by pulling the RESET pin low Since a crystal or ceramic resonator may be selected as the oscillator the Wakeup signal is not allowed to start the chip running immediately since crystal oscillators and ceramic resonators have a delayed start up time to reach full ampli- Power Save Modes The device offers the user two power save modes of operation HALT and IDLE In the HALT mode all microcontroller activities are stopped In the IDLE mode the on-board oscillator circuitry and timer T0 are active but all other microcontroller activities are stopped In either mode all on-board RAM registers I O states and timers (with the exception of T0) are unaltered 19 http www national com Power Save Modes (Continued) Multi-Input Wakeup tude and frequency stability The IDLE timer is used to generate a fixed delay to ensure that the oscillator has indeed stabilized before allowing instruction execution In this case upon detecting a valid Wakeup signal only the oscillator circuitry is enabled The IDLE timer is loaded with a value of 256 and is clocked with the tC instruction cycle clock The tC clock is derived by dividing the oscillator clock down by a factor of 10 The Schmitt trigger following the CKI inverter on the chip ensures that the IDLE timer is clocked only when the oscillator has a sufficiently large amplitude to meet the Schmitt trigger specifications This Schmitt trigger is not part of the oscillator closed loop The startup timeout from the IDLE timer enables the clock signals to be routed to the rest of the chip If an RC clock option is being used the fixed delay is introduced optionally A control bit CLKDLY mapped as configuration bit G7 controls whether the delay is to be introduced or not The delay is included if CLKDLY is set and excluded if CLKDLY is reset The CLKDLY bit is cleared on reset The device has two mask options associated with the HALT mode The first mask option enables the HALT mode feature while the second mask option disables the HALT mode With the HALT mode enable mask option the device will enter and exit the HALT mode as described above With the HALT disable mask option the device cannot be placed in the HALT mode (writing a ``1'' to the HALT flag will have no effect the HALT flag will remain ``0'') The Multi-Input Wakeup feature is used to return (wakeup) the device from either the HALT or IDLE modes Alternately Multi-Input Wakeup Interrupt feature may also be used to generate up to 4 edge selectable external interrupts Figure 10 shows the Multi-Input Wakeup logic The Multi-Input Wakeup feature utilizes the L Port The user selects which particular L port bit (or combination of L Port bits) will cause the device to exit the HALT or IDLE modes The selection is done through the register WKEN The register WKEN is an 8-bit read write register which contains a control bit for every L port bit Setting a particular WKEN bit enables a Wakeup from the associated L port pin The user can select whether the trigger condition on the selected L Port pin is going to be either a positive edge (low to high transition) or a negative edge (high to low transition) This selection is made via the register WKEDG which is an 8-bit control register with a bit assigned to each L Port pin Setting the control bit will select the trigger condition to be a negative edge on that particular L Port pin Resetting the bit selects the trigger condition to be a positive edge Changing an edge select entails several steps in order to avoid a Wakeup condition as a result of the edge change First the associated WKEN bit should be reset followed by the edge select change in WKEDG Next the associated WKPND bit should be cleared followed by the associated WKEN bit being re-enabled An example may serve to clarify this procedure Suppose we wish to change the edge select from positive (low going high) to negative (high going low) for L Port bit 5 where bit 5 has previously been enabled for an input interrupt The program would be as follows RBIT 5 WKEN SBIT 5 WKEDG RBIT 5 WKPND SBIT 5 WKEN If the L port bits have been used as outputs and then changed to inputs with Multi-Input Wakeup Interrupt a safety procedure should also be followed to avoid wakeup conditions After the selected L port bits have been changed from output to input but before the associated WKEN bits are enabled the associated edge select bits in WKEDG should be set or reset for the desired edge selects followed by the associated WKPND bits being cleared This same procedure should be used following reset since the L port inputs are left floating as a result of reset The occurrence of the selected trigger condition for Multi-Input Wakeup is latched into a pending register called WKPND The respective bits of the WKPND register will be set on the occurrence of the selected trigger edge on the corresponding Port L pin The user has the responsibility of clearing these pending flags Since WKPND is a pending register for the occurrence of selected wakeup conditions the device will not enter the HALT mode if any Wakeup bit is both enabled and pending Consequently the user must clear the pending flags before attempting to enter the HALT mode WKEN WKPND and WKEDG are all read write registers and are cleared at reset IDLE MODE The device is placed in the IDLE mode by writing a ``1'' to the IDLE flag (G6 data bit) In this mode all activities except the associated on-board oscillator circuitry and the IDLE Timer T0 are stopped As with the HALT mode the device can be returned to normal operation with a reset or with a Multi-Input Wakeup from the L Port Alternately the microcontroller resumes normal operation from the IDLE mode when the thirteenth bit (representing 4 096 ms at internal clock frequency of 10 MHz tC e 1 ms) of the IDLE Timer toggles This toggle condition of the thirteenth bit of the IDLE Timer T0 is latched into the T0PND pending flag The user has the option of being interrupted with a transition on the thirteenth bit of the IDLE Timer T0 The interrupt can be enabled or disabled via the T0EN control bit Setting the T0EN flag enables the interrupt and vice versa The user can enter the IDLE mode with the Timer T0 interrupt enabled In this case when the T0PND bit gets set the device will first execute the Timer T0 interrupt service routine and then return to the instruction following the ``Enter Idle Mode'' instruction Alternatively the user can enter the IDLE mode with the IDLE Timer T0 interrupt disabled In this case the device will resume normal operation with the instruction immediately following the ``Enter IDLE Mode'' instruction Note It is necessary to program two NOP instructions following both the set HALT mode and set IDLE mode instructions These NOP instructions are necessary to allow clock resynchronization following the HALT or IDLE modes http www national com 20 Multi-Input Wakeup (Continued) TL DD 12865 ­ 12 FIGURE 10 Multi-Input Wake Up Logic PORT L INTERRUPTS Port L provides the user with an additional eight fully selectable edge sensitive interrupts which are all vectored into the same service subroutine The interrupt from Port L shares logic with the wake up circuitry The register WKEN allows interrupts from Port L to be individually enabled or disabled The register WKEDG specifies the trigger condition to be either a positive or a negative edge Finally the register WKPND latches in the pending trigger conditions The GIE (Global Interrupt Enable) bit enables the interrupt function A control flag LPEN functions as a global interrupt enable for Port L interrupts Setting the LPEN flag will enable interrupts and vice versa A separate global pending flag is not needed since the register WKPND is adequate Since Port L is also used for waking the device out of the HALT or IDLE modes the user can elect to exit the HALT or IDLE modes either with or without the interrupt enabled If he elects to disable the interrupt then the device will restart execution from the instruction immediately following the instruction that placed the microcontroller in the HALT or IDLE modes In the other case the device will first execute the interrupt service routine and then revert to normal operation (See HALT MODE for clock option wakeup information ) 21 http www national com Analog Function Block CMPT2B This device contains an analog function block with the intent to provide a function which allows for single slope low cost A D conversion of up to 6 channels CMPSL REGISTER (ADDRESS X'00B7) The CMPSL register contains the following bits CMPNEG Will drive I1 to a low level This bit can be used to discharge an external capacitor This bit is disabled if the comparator is not enabled (CMPEN e 0) CMPEN Enable the comparator (``1'' e enable) CSEN Enables the internal constant current source This current source provides a nominal 20 mA constant current at the I1 pin This current can be used to ensure a linear charging rate on an external capacitor This bit has no affect and the current source is disabled if the comparator is not enabled (CMPEN e 0) CMPOE Enables the comparator output to either pin I3 or pin I7 (``1'' e enable) depending on the value of CMPISEL0 1 2 CMPISEL0 1 2 Will select one of seven possible sources (I0 I2 I3 I4 I5 I6 internal reference) as a positive input to the comparator (see Table V for more information ) Selects the timer T2B input to be driven directly by the comparator output If the comparator is disabled (CMPEN e 0) this function is disabled i e the T2B input is connected to Port L5 CMPT2B CMPISEL2 CMPISEL1 CMPISEL0 CMPOE CSEN CMPEN CMPNEG Bit 7 Bit 0 The Comparator Select Register is cleared on RESET (the comparator is disabled) To save power the program should also disable the comparator before the mC enters the HALT IDLE modes Disabling the comparator will turn off the constant current source and the VCC 2 reference disconnect the comparator output from the T2B input and pin I3 or I7 and remove the low on I1 caused by CMPNEG It is often useful for the user's program to read the result of a comparator operation Since I1 is always selected to be COMPIN when the comparator is enabled (CMPEN e 1) the comparator output can be read internally by reading bit 1 (CMPRD) of register PORTI (RAM address 0xD7) The following table lists the comparator inputs and outputs versus the value of the CMPISEL0 1 2 bits The output will only be driven if the CMPOE bit is set to 1 TL DD 12865 ­ 13 FIGURE 11 COP884CT COP884CT Analog Function Block http www national com 22 Analog Function Block (Continued) The comparator outputs have the same specification as Ports L and G except that the rise and fall times are symmetrical TABLE V Comparator Input Selection Control Bit CMPISEL2 CMPISEL1 CMPISEL0 Comparator Input Source Comparator Output Neg Pos Input Interrupts Input 0 0 0 I1 I2 0 0 1 I1 I2 I7 0 1 0 I1 I3 I7 0 1 1 I1 I0 I7 1 0 0 I1 I4 I7 1 0 1 I1 I5 I7 1 1 0 I1 I6 I7 1 1 1 I1 VCC 2 Ref The device supports a vectored interrupt scheme It supports a total of twelve interrupt sources The following table lists all the possible device interrupt sources their arbitration rankings and the memory locations reserved for the interrupt vector for each source Two bytes of program memory space are reserved for each interrupt source All interrupt sources except the software interrupt are maskable Each of the maskable interrupts have an Enable bit and one or more Pending bits A maskable interrupt is active if its associated enable and pending bits are set If GIE e 1 and an interrupt is active then the processor will be interrupted as soon as it is ready to start executing an instruction except if the above conditions happen during the Software Trap service routine This exception is described in the Software Trap sub-section The interruption process is accomplished with the INTR instruction (opcode 00) which is jammed inside the Instruction Register and replaces the opcode about to be executed The following steps are performed for every interrupt 1 The GIE (Global Interrupt Enable) bit is reset 2 The address of the instruction about to be executed is pushed into the stack 3 The PC (Program Counter) branches to address 00FF This procedure takes 7 tC cycles to execute I3 I7 Reset The state of the Comparator Block immediately after RESET is as follows 1 The CMPSL Register is set to all zeros 2 The Comparator is disabled 3 The Constant Current Source is disabled 4 CMPNEG is turned off 5 The Port I inputs are electrically isolated from the comparator 6 The T2B input is as normally selected by the T2CNTRL Register 7 CMPISEL0­CMPISEL2 are set to zero 8 All Port I inputs are selected to the default digital input mode TABLE VI Interrupt Vector Table ARBITRATION RANKING VECTOR ADDRESS (Hi-Low Byte) SOURCE DESCRIPTION (1) Highest Software (2) Reserved INTR Instruction 0yFE ­ 0yFF (3) External G0 0yFA ­ 0yFB (4) Timer T0 Idle Timer 0yF8 ­ 0yF9 (5) Timer T1 T1A Underflow 0yF6 ­ 0yF7 (6) Timer T1 T1B 0yF4 ­ 0yF5 (7) Microwire Plus Busy Low (8) Reserved 0yF0 ­ 0yF1 (9) Reserved 0yEE ­ 0yEF (10) Reserved (11) High Speed Capture Timer (12) Reserved 0yE8 ­ 0yE9 (13) Reserved 0yE6 ­ 0yE7 (14) Reserved (15) Port L Wakeup Port L Edge 0yE2 ­ 0yE3 (16) Lowest Default VIS Reserved 0yE0 ­ 0yE1 0yFC ­ 0yFD 0yF2 ­ 0yF3 0yEC ­ 0yED Capture Overflow Capture Pending 0yEA ­ 0yEB 0yE4 ­ 0yE5 y is a variable which represents the VIS block VIS and the vector table must be located in the same 256-byte block except if VIS is located at the last address of a block In this case the table must be in the next block 23 http www national com Interrupts (Continued) Inside the interrupt service routine the associated pending bit has to be cleared by software The RETI (Return from Interrupt) instruction at the end of the interrupt service routine will set the GIE (Global Interrupt Enable) bit allowing the processor to be interrupted again if another interrupt is active and pending The VIS instruction looks at all the active interrupts at the time it is executed and performs an indirect jump to the beginning of the service routine of the one with the highest rank The addresses of the different interrupt service routines called vectors are chosen by the user and stored in ROM in a table starting at 01E0 (assuming that VIS is located between 00FF and 01DF) The vectors are 15-bit wide and therefore occupy 2 ROM locations VIS and the vector table must be located in the same 256byte block (0y00 to 0yFF) except if VIS is located at the last address of a block In this case the table must be in the next block The vector table cannot be inserted in the first 256-byte block (y i 0) At this time since GIE e 0 other maskable interrupts are disabled The user is now free to do whatever context switching is required by saving the context of the machine in the stack with PUSH instructions The user would then program a VIS (Vector Interrupt Select) instruction in order to branch to the interrupt service routine of the highest priority interrupt enabled and pending at the time of the VIS Note that this is not necessarily the interrupt that caused the branch to address location 00FF Hex prior to the context switching Thus if an interrupt with a higher rank than the one which caused the interruption becomes active before the decision of which interrupt to service is made by the VIS then the interrupt with the higher rank will override any lower ones and will be acknowledged The lower priority interrupt(s) are still pending however and will cause another interrupt immediately following the completion of the interrupt service routine associated with the higher priority interrupt just serviced This lower priority interrupt will occur immediately following the RETI (Return from Interrupt) instruction at the end of the interrupt service routine just completed TL DD 12865 ­ 14 FIGURE 12 Interrupt Block Diagram http www national com 24 Interrupts (Continued) Servicing the WATCHDOG consists of writing a specific value to a WATCHDOG Service Register named WDSVR which is memory mapped in the RAM This value is composed of three fields consisting of a 2-bit Window Select a 5-bit Key Data field and the 1-bit Clock Monitor Select field Table VII shows the WDSVR register The vector of the maskable interrupt with the lowest rank is located at 0yE0 (Hi-Order byte) and 0yE1 (Lo-Order byte) and so forth in increasing rank number The vector of the maskable interrupt with the highest rank is located at 0yFA (Hi-Order byte) and 0yFB (Lo-Order byte) The Software Trap has the highest rank and its vector is located at 0yFE and 0yFF If by accident a VIS gets executed and no interrupt is active then the PC (Program Counter) will branch to a vector located at 0yE0-0yE1 WARNING A Default VIS interrupt handler routine must be present As a minimum this handler should confirm that the GIE bit is cleared (this indicates that the interrupt sequence has been taken) take care of any required housekeeping restore context and return Some sort of Warm Restart procedure should be implemented These events can occur without any error on the part of the system designer or programmer TABLE VII WATCHDOG Service Register (WDSVR) Window Select X X Clock Monitor Key Data 0 1 1 0 0 Y 7 6 5 4 3 2 1 0 The lower limit of the service window is fixed at 2048 instruction cycles Bits 7 and 6 of the WDSVR register allow the user to pick an upper limit of the service window Table VIII shows the four possible combinations of lower and upper limits for the WATCHDOG service window This flexibility in choosing the WATCHDOG service window prevents any undue burden on the user software Bits 5 4 3 2 and 1 of the WDSVR register represent the 5-bit Key Data field The key data is fixed at 01100 Bit 0 of the WDSVR Register is the Clock Monitor Select bit Note There is always the possibility of an interrupt occurring during an instruction which is attempting to reset the GIE bit or any other interrupt enable bit If this occurs when a single cycle instruction is being used to reset the interrupt enable bit the interrupt enable bit will be reset but an interrupt may still occur This is because interrupt processing is started at the same time as the interrupt bit is being reset To avoid this scenario the user should always use a two three or four cycle instruction to reset interrupt enable bits TABLE VIII WATCHDOG Service Window Select Figure 12 shows the Interrupt block diagram WDSVR Bit 7 WDSVR Bit 6 0 0 2k ­8k tC Cycles 0 1 2k ­ 16k tC Cycles 1 0 2k ­ 32k tC Cycles 1 SOFTWARE TRAP The Software Trap (ST) is a special kind of non-maskable interrupt which occurs when the INTR instruction (used to acknowledge interrupts) is fetched from ROM and placed inside the instruction register This may happen when the PC is pointing beyond the available ROM address space or when the stack is over-popped When an ST occurs the user can re-initialize the stack pointer and do a recovery procedure (similar to reset but not necessarily containing all of the same initialization procedures) before restarting The occurrence of an ST is latched into the ST pending bit The GIE bit is not affected and the ST pending bit (not accessible by the user) is used to inhibit other interrupts and to direct the program to the ST service routine with the VIS instruction The RPND instruction is used to clear the software interrupt pending bit This pending bit is also cleared on reset The ST has the highest rank among all interrupts Nothing (except another ST) can interrupt an ST being serviced Service Window (Lower-Upper Limits) 1 2k ­ 64k tC Cycles Clock Monitor The Clock Monitor aboard the device can be selected or deselected under program control The Clock Monitor is guaranteed not to reject the clock if the instruction cycle clock (1 tC) is greater or equal to 10 kHz This equates to a clock input rate on CKI of greater or equal to 100 kHz WATCHDOG Operation The WATCHDOG and Clock Monitor are disabled during reset The device comes out of reset with the WATCHDOG armed the WATCHDOG Window Select bits (bits 6 7 of the WDSVR Register) set and the Clock Monitor bit (bit 0 of the WDSVR Register) enabled Thus a Clock Monitor error will occur after coming out of reset if the instruction cycle clock frequency has not reached a minimum specified value including the case where the oscillator fails to start The WDSVR register can be written to only once after reset and the key data (bits 5 through 1 of the WDSVR Register) must match to be a valid write This write to the WDSVR register involves two irrevocable choices (i) the selection of WATCHDOG The devices contain a WATCHDOG and clock monitor The WATCHDOG is designed to detect the user program getting stuck in infinite loops resulting in loss of program control or ``runaway'' programs The Clock Monitor is used to detect the absence of a clock or a very slow clock below a specified rate on the CKI pin The WATCHDOG consists of two independent logic blocks WD UPPER and WD LOWER WD UPPER establishes the upper limit on the service window and WD LOWER defines the lower limit of the service window 25 http www national com WATCHDOG Operation (Continued) The WATCHDOG service window and CLOCK MONI- the WATCHDOG service window (ii) enabling or disabling of the Clock Monitor Hence the first write to WDSVR Register involves selecting or deselecting the Clock Monitor select the WATCHDOG service window and match the WATCHDOG key data Subsequent writes to the WDSVR register will compare the value being written by the user to the WATCHDOG service window value and the key data (bits 7 through 1) in the WDSVR Register Table IX shows the sequence of events that can occur The user must service the WATCHDOG at least once before the upper limit of the service window expires The WATCHDOG may not be serviced more than once in every lower limit of the service window The user may service the WATCHDOG as many times as wished in the time period between the lower and upper limits of the service window The first write to the WDSVR Register is also counted as a WATCHDOG service The WATCHDOG has an output pin associated with it This is the WDOUT pin on pin 1 of the port G WDOUT is active low The WDOUT pin is in the high impedance state in the inactive state Upon triggering the WATCHDOG the logic will pull the WDOUT (G1) pin low for an additional 16 tC ­ 32 tC cycles after the signal level on WDOUT pin goes below the lower Schmitt trigger threshold After this delay the device will stop forcing the WDOUT output low The WATCHDOG service window will restart when the WDOUT pin goes high It is recommended that the user tie the WDOUT pin back to VCC through a resistor in order to pull WDOUT high A WATCHDOG service while the WDOUT signal is active will be ignored The state of the WDOUT pin is not guaranteed on reset but if it powers up low then the WATCHDOG will time out and WDOUT will enter high impedance state The Clock Monitor forces the G1 pin low upon detecting a clock frequency error The Clock Monitor error will continue until the clock frequency has reached the minimum specified value after which the G1 output will enter the high impedance TRI-STATE mode following 16 tC ­ 32 tC clock cycles The Clock Monitor generates a continual Clock Monitor error if the oscillator fails to start or fails to reach the minimum specified frequency The specification for the Clock Monitor is as follows 1 tC l 10 kHz No clock rejection 1 tC k 10 Hz Guaranteed clock rejection TOR enable disable option can only be changed once during the initial WATCHDOG service following RESET The initial WATCHDOG service must match the key data value in the WATCHDOG Service register WDSVR in order to avoid a WATCHDOG error Subsequent WATCHDOG services must match all three data fields in WDSVR in order to avoid WATCHDOG errors The correct key data value cannot be read from the WATCHDOG Service register WDSVR Any attempt to read this key data value of 01100 from WDSVR will read as key data value of all 0's The WATCHDOG detector circuit is inhibited during both the HALT and IDLE modes The CLOCK MONITOR detector circuit is active during both the HALT and IDLE modes Consequently the device inadvertently entering the HALT mode will be detected as a CLOCK MONITOR error (provided that the CLOCK MONITOR enable option has been selected by the program) With the single-pin R C oscillator mask option selected and the CLKDLY bit reset the WATCHDOG service window will resume following HALT mode from where it left off before entering the HALT mode With the crystal oscillator mask option selected or with the single-pin R C oscillator mask option selected and the CLKDLY bit set the WATCHDOG service window will be set to its selected value from WDSVR following HALT Consequently the WATCHDOG should not be serviced for at least 2048 instruction cycles following HALT but must be serviced within the selected window to avoid a WATCHDOG error The IDLE timer T0 is not initialized with RESET The user can sync in to the IDLE counter cycle with an IDLE counter (T0) interrupt or by monitoring the T0PND flag The T0PND flag is set whenever the thirteenth bit of the IDLE counter toggles (every 4096 instruction cycles) The user is responsible for resetting the T0PND flag A hardware WATCHDOG service occurs just as the device exits the IDLE mode Consequently the WATCHDOG should not be serviced for at least 2048 instruction cycles following IDLE but must be serviced within the selected window to avoid a WATCHDOG error WATCHDOG AND CLOCK MONITOR SUMMARY The following salient points regarding the WATCHDOG and CLOCK MONITOR should be noted Following RESET the initial WATCHDOG service (where the service window and the CLOCK MONITOR enable disable must be selected) may be programmed anywhere within the maximum service window (65 536 instruction cycles) initialized by RESET Note that this initial WATCHDOG service may be programmed within the initial 2048 instruction cycles without causing a WATCHDOG error Both the WATCHDOG and CLOCK MONITOR detector circuits are inhibited during RESET Following RESET the WATCHDOG and CLOCK MONITOR are both enabled with the WATCHDOG having the maximum service window selected TABLE IX WATCHDOG Service Actions Key Data Window Data Clock Monitor Action Match Match Match Valid Service Restart Service Window Don't Care Don't Care Error Generate WATCHDOG Output Don't Care Don't Care Error Generate WATCHDOG Output Don't Care http Mismatch Mismatch Don't Care Mismatch Error Generate WATCHDOG Output www national com 26 ers E2PROMs etc ) and with other microcontrollers which support the MICROWIRE interface It consists of an 8-bit serial shift register (SIO) with serial data input (SI) serial data output (SO) and serial shift clock (SK) Figure 13 shows a block diagram of the MICROWIRE PLUS logic The shift clock can be selected from either an internal source or an external source Operating the MICROWIRE PLUS arrangement with the internal clock source is called the Master mode of operation Similarly operating the MICROWIRE PLUS arrangement with an external shift clock is called the Slave mode of operation The CNTRL register is used to configure and control the MICROWIRE PLUS mode To use the MICROWIRE PLUS the MSEL bit in the CNTRL register is set to one In the master mode the SK clock rate is selected by the two bits SL0 and SL1 in the CNTRL register Table X details the different clock rates that may be selected Detection of Illegal Conditions The device can detect various illegal conditions resulting from coding errors transient noise power supply voltage drops runaway programs etc Reading of undefined ROM gets zeros The opcode for software interrupt is 00 If the program fetches instructions from undefined ROM this will force a software interrupt thus signaling that an illegal condition has occurred The subroutine stack grows down for each call (jump to subroutine) interrupt or PUSH and grows up for each return or POP The stack pointer is initialized to RAM location 06F Hex during reset Consequently if there are more returns than calls the stack pointer will point to addresses 070 and 071 Hex (which are undefined RAM) Undefined RAM from addresses 070 to 07F (Segment 0) and all other segments (i e Segments 4 etc ) is read as all 1's which in turn will cause the program to return to address 7FFF Hex This is an undefined ROM location and the instruction fetched (all 0's) from this location will generate a software interrupt signaling an illegal condition Thus the chip can detect the following illegal conditions 1 Executing from undefined ROM 2 Over ``POP''ing the stack by having more returns than calls When the software interrupt occurs the user can re-initialize the stack pointer and do a recovery procedure before restarting (this recovery program is probably similar to that following reset but might not contain the same program initialization procedures) The recovery program should reset the software interrupt pending bit using the RPND instruction TABLE X MICROWIRE PLUS Master Mode Clock Select SL1 SL0 SK period 0 0 2 X tC 0 1 4 X tC 1 x 8 X tC Where tC is the instruction cycle clock MICROWIRE PLUS OPERATION Setting the BUSY bit in the PSW register causes the MICROWIRE PLUS to start shifting the data It gets reset when eight data bits have been shifted The user may reset the BUSY bit by software to allow less than 8 bits to shift If enabled an interrupt is generated when eight data bits have been shifted The device may enter the MICROWIRE PLUS mode either as a Master or as a Slave Figure 14 shows how two devices microcontrollers and several peripherals may be interconnected using the MICROWIRE PLUS arrangements MICROWIRE PLUS MICROWIRE PLUS is a serial synchronous communications interface The MICROWIRE PLUS capability enables the device to interface with any of National Semiconductor's MICROWIRE peripherals (i e A D converters display driv- TL DD 12865 ­ 15 FIGURE 13 MICROWIRE PLUS Block Diagram 27 http www national com MICROWIRE PLUS (Continued) TABLE XI MICROWIRE Mode Settings WARNING The SIO register should only be loaded when the SK clock is low Loading the SIO register while the SK clock is high will result in undefined data in the SIO register SK clock is normally low when not shifting Setting the BUSY flag when the input SK clock is high in the MICROWIRE PLUS slave mode may cause the current SK clock for the SIO shift register to be narrow For safety the BUSY flag should only be set when the input SK clock is low G4 (SO) G5 (SK) G4 Config Bit Config Bit Fun G5 Fun 4 Operation 1 SO Int SK MICROWIRE PLUS Master 0 1 TRISTATE Int SK MICROWIRE PLUS Master 1 0 SO Ext SK MICROWIRE PLUS Slave 0 MICROWIRE PLUS Master Mode Operation In the MICROWIRE PLUS Master mode of operation the shift clock (SK) is generated internally The MICROWIRE Master always initiates all data exchanges The MSEL bit in the CNTRL register must be set to enable the SO and SK functions onto the G Port The SO and SK pins must also be selected as outputs by setting appropriate bits in the Port G configuration register Table XI summarizes the bit settings required for Master mode of operation 1 0 TRI- Ext STATE SK MICROWIRE PLUS Slave This table assumes that the control flag MSEL is set Alternate SK Phase Operation The device allows either the normal SK clock or an alternate phase SK clock to shift data in and out of the SIO register In both the modes the SK is normally low In the normal mode data is shifted in on the rising edge of the SK clock and the data is shifted out on the falling edge of the SK clock The SIO register is shifted on each falling edge of the SK clock In the alternate SK phase operation data is shifted in on the falling edge of the SK clock and shifted out on the rising edge of the SK clock A control flag SKSEL allows either the normal SK clock or the alternate SK clock to be selected Resetting SKSEL causes the MICROWIRE PLUS logic to be clocked from the normal SK signal Setting the SKSEL flag selects the alternate SK clock The SKSEL is mapped into the G6 configuration bit The SKSEL flag will power up in the reset condition selecting the normal SK signal MICROWIRE PLUS Slave Mode Operation In the MICROWIRE PLUS Slave mode of operation the SK clock is generated by an external source Setting the MSEL bit in the CNTRL register enables the SO and SK functions onto the G Port The SK pin must be selected as an input and the SO pin is selected as an output pin by setting and resetting the appropriate bits in the Port G configuration register Table XI summarizes the settings required to enter the Slave mode of operation The user must set the BUSY flag immediately upon entering the Slave mode This will ensure that all data bits sent by the Master will be shifted properly After eight clock pulses the BUSY flag will be cleared and the sequence may be repeated TL DD 12865 ­ 16 FIGURE 14 MICROWIRE PLUS Application http www national com 28 Memory Map All RAM ports and registers (except A and PC) are mapped into data memory address space Address S ADD REG Address S ADD REG xxDA xxDB xxDC xxDD to DF Contents 0000 to 006F On-Chip RAM bytes (112 bytes) 0070 to 007F Unused RAM Address Space (Reads As All Ones) Unused RAM Address Space (Reads Undefined Data) xx80 to xxAF xxB0 XXB1 xxB2 xxB3 xxB4 xxB5 xxB6 xxB7 xxB8 to xxBF xxC0 xxC1 xxC2 xxC3 xxC4 xxC5 xxC6 xxC7 xxE0 to xxE5 xxE6 xxE7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Comparator Select Register (CMPSL) Reserved xxCF xxED xxEE xxEF Reserved Reserved Reserved Reserved Reserved Reserved Reserved WATCHDOG Service Register (Reg WDSVR) MIWU Edge Select Register (Reg WKEDG) MIWU Enable Register (Reg WKEN) MIWU Pending Register (Reg WKPND) Reserved CAPTLO (Capture Timer Low-Byte) CAPTHI (Capture Timer High-Byte) CAPCNTL (Capture Timer Control Register) Idle Timer Control Register xxD0 xxD1 xxD2 xxD3 xxD4 xxD5 xxD6 xxD7 xxD8 xxD9 xxE8 xxE9 xxEA xxEB xxEC Contents Reserved Reserved Port D Reserved Reserved Timer T1 Autoload Register T1RB Lower Byte Timer T1 Autoload Register T1RB Upper Byte ICNTRL Register MICROWIRE PLUS Shift Register Timer T1 Lower Byte Timer T1 Upper Byte Timer T1 Autoload Register T1RA Lower Byte Timer T1 Autoload Register T1RA Upper Byte CNTRL Control Register PSW Register Port L Data Register Port L Configuration Register Port L Input Pins (Read Only) Reserved Port G Data Register Port G Configuration Register Port G Input Pins (Read Only) Port I Input Pins (Read Only) Reserved Reserved xxC8 xxC9 xxCA xxCB xxCC xxCD xxCE xxF0 to FB xxFC xxFD xxFE xxFF On-Chip RAM Mapped as Registers X Register SP Register B Register Reserved 0100-017F 0100-017F Reserved Reading memory locations 0070H-007FH 0070H-007FH (Segment 0) will return all ones Reading unused memory locations 0080H00AFH 0080H00AFH (Segment 0) will return undefined data Reading memory locations from other Segments (i e Segment 2 Segment 3 etc ) will return all ones 29 http www national com Addressing Modes There are ten addressing modes six for operand addressing and four for transfer of control Absolute This mode is used with the JMP and JSR instructions with the instruction field of 12 bits replacing the lower 12 bits of the program counter (PC) This allows jumping to any location in the current 4k program memory segment OPERAND ADDRESSING MODES Register Indirect This is the ``normal'' addressing mode The operand is the data memory addressed by the B pointer or X pointer Register Indirect (with auto post increment or decrement of pointer) This addressing mode is used with the LD and X instructions The operand is the data memory addressed by the B pointer or X pointer This is a register indirect mode that automatically post increments or decrements the B or X register after executing the instruction Absolute Long This mode is used with the JMPL and JSRL instructions with the instruction field of 15 bits replacing the entire 15 bits of the program counter (PC) This allows jumping to any location up to 32k in the program memory space Indirect This mode is used with the JID instruction The contents of the accumulator are used as a partial address (lower 8 bits of PC) for accessing a location in the program memory The contents of this program memory location serve as a partial address (lower 8 bits of PC) for the jump to the next instruction Direct The instruction contains an 8-bit address field that directly points to the data memory for the operand Immediate The instruction contains an 8-bit immediate field as the operand Note The VIS is a special case of the Indirect Transfer of Control addressing mode where the double byte vector associated with the interrupt is transferred from adjacent addresses in the program memory into the program counter (PC) in order to jump to the associated interrupt service routine Short Immediate This addressing mode is used with the Load B Immediate instruction The instruction contains a 4-bit immediate field as the operand Instruction Set Register and Symbol Definition Indirect This addressing mode is used with the LAID instruction The contents of the accumulator are used as a partial address (lower 8 bits of PC) for accessing a data operand from the program memory Registers A B X SP PC PU PL C HC GIE TRANSFER OF CONTROL ADDRESSING MODES Relative This mode is used for the JP instruction with the instruction field being added to the program counter to get the new program location JP has a range from b31 to a 32 to allow a 1-byte relative jump (JP a 1 is implemented by a NOP instruction) There are no ``pages'' when using JP since all 15 bits of PC are used VU VL 8-Bit Accumulator Register 8-Bit Address Register 8-Bit Address Register 8-Bit Stack Pointer Register 15-Bit Program Counter Register Upper 7 Bits of PC Lower 8 Bits of PC 1-Bit of PSW Register for Carry 1-Bit of PSW Register for Half Carry 1-Bit of PSW Register for Global Interrupt Enable Interrupt Vector Upper Byte Interrupt Vector Lower Byte Symbols B X MD Mem Meml Imm Reg Bit w http www national com 30 Memory Indirectly Addressed by B Register Memory Indirectly Addressed by X Register Direct Addressed Memory Direct Addressed Memory or B Direct Addressed Memory or B or Immediate Data 8-Bit Immediate Data Register Memory Addresses F0 to FF (Includes B X and SP) Bit Number (0 to 7) Loaded with Exchanged with Instruction Set (Continued) ADD ADD with Carry Subtract with Carry Logical AND Logical AND Immed Skip if Zero Logical OR Logical EXclusive OR IF EQual IF EQual IF Not Equal IF Greater Than If B Not Equal Decrement Reg Skip if Zero Set BIT Reset BIT IF BIT Reset PeNDing Flag A w A a Meml A w A a Meml a C C w Carry HC w Half Carry A w A b MemI a C C w Carry HC w Half Carry A w A and Meml Skip next if (A and Imm) e 0 A w A or Meml A w A xor Meml Compare MD and Imm Do next if MD e Imm Compare A and Meml Do next if A e Meml Compare A and Meml Do next if A i Meml Compare A and Meml Do next if A l Meml Do next if lower 4 bits of B i Imm Reg w Reg b 1 Skip if Reg e 0 1 to bit Mem (bit e 0 to 7 immediate) 0 to bit Mem If bit A or Mem is true do next instruction Reset Software Interrupt Pending Flag A Mem A X A Meml A X B Imm Mem Imm Reg Imm EXchange A with Memory EXchange A with Memory X LoaD A with Memory LoaD A with Memory X LoaD B with Immed LoaD Memory Immed LoaD Register Memory Immed A Mem X A A w Meml Aw X B w Imm Mem w Imm Reg w Imm X X LD LD LD A Bg A Xg A Bg A Xg B g Imm EXchange A with Memory B EXchange A with Memory X LoaD A with Memory B LoaD A with Memory X LoaD Memory B Immed A B (B w B g 1) A X (X w X g 1) A w B (B w B g 1) A w X (X w X g 1) B w Imm (B w B g 1) CLR INC DEC LAID DCOR RRC RLC SWAP SC RC IFC IFNC POP PUSH A A A CLeaR A INCrement A DECrement A Load A InDirect from ROM Decimal CORrect A Rotate A Right thru C Rotate A Left thru C SWAP nibbles of A Set C Reset C IF C IF Not C POP the stack into A PUSH A onto the stack Aw0 AwAa1 AwAb1 A w ROM (PU A) A w BCD correction of A (follows ADC SUBC) C x A7 x x A0 x C C w A7 w w A0 w C A7 A4 A3 A0 C w 1 HC w 1 C w 0 HC w 0 IF C is true do next instruction If C is not true do next instruction SP w SP a 1 A w SP SP w A SP w SP b 1 Vector to Interrupt Service Routine Jump absolute Long Jump absolute Jump relative short Jump SubRoutine Long Jump SubRoutine Jump InDirect RETurn from subroutine RETurn and SKip RETurn from Interrupt Generate an Interrupt No OPeration PU w VU PL w VL PC w ii (ii e 15 bits 0 to 32k) PC9 0 w i (i e 12 bits) PC w PC a r (r is b31 to a 32 except 1) SP w PL SP-1 w PU SP-2 PC w ii SP w PL SP-1 w PU SP-2 PC9 0 w i PL w ROM (PU A) SP a 2 PL w SP PU w SP-1 SP a 2 PL w SP PU w SP-1 skip next instruction SP a 2 PL w SP PU w SP-1 GIE w 1 SP w PL SP-1 w PU SP-2 PC w 0FF PC w PC a 1 ADD ADC SUBC AND ANDSZ OR XOR IFEQ IFEQ IFNE IFGT IFBNE DRSZ SBIT RBIT IFBIT RPND A Meml A Meml A Meml A Meml A Imm A Meml A Meml MD Imm A Meml A Meml A Meml X X LD LD LD LD LD VIS JMPL JMP JP JSRL JSR JID RET RETSK RETI INTR NOP Reg Mem Mem Mem A A A A A A Addr Addr Disp Addr Addr 31 http www national com Instruction Execution Time See the BYTES and CYCLES per INSTRUCTION table for details Most instructions are single byte (with immediate addressing mode instructions taking two bytes) Most single byte instructions take one cycle time to execute Skipped instructions require x number of cycles to be skipped where x equals the number of bytes in the skipped instruction opcode Arithmetic and Logic Instructions B ADD ADC SUBC AND OR XOR IFEQ IFGT IFBNE DRSZ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SBIT RBIT IFBIT 1 1 1 1 1 1 RPND Direct 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 Instructions Using A and C CLRA INCA DECA LAID DCORA RRCA RLCA SWAPA SC RC IFC IFNC PUSHA POPA ANDSZ Immed 2 2 2 2 2 2 2 2 Bytes and Cycles per Instruction The following table shows the number of bytes and cycles for each instruction in the format of byte cycle 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 Transfer of Control Instructions 1 1 1 3 1 1 1 1 1 1 1 1 3 3 2 JMPL JMP JP JSRL JSR JID VIS RET RETSK RETI INTR NOP 1 1 1 3 3 4 3 4 3 4 Memory Transfer Instructions Register Indirect Direct B XA 1 1 1 3 2 3 LD A 1 1 1 3 2 3 Immed X Register Indirect Auto Incr and Decr B a Bb X a Xb 1 2 2 2 1 3 1 2 1 3 LD B Imm 1 1 (If B k 16) LD B Imm 2 2 (If B l 15) LD Mem Imm 2 2 3 3 LD Reg Imm IFEQ MD Imm 2 2 2 3 3 3 Memory location addressed by B or X or directly http www national com 32 3 2 1 3 2 1 1 1 1 1 1 1 4 3 3 5 5 3 5 5 5 5 7 1 i i i JP b11 JP b27 LD 0F4 JP b10 JP b26 LD 0F5 JP b25 LD 0F6 JP b24 LD 0F7 JP b9 JP b8 JP b23 LD 0F8 i JP b12 JP b28 LD 0F3 33 http JP b20 LD 0FB JP b19 LD 0FC JP b18 LD 0FD JP b17 LD 0FE JP b16 LD 0FF JP b5 JP b4 JP b3 JP b2 JP b1 JP b0 i i i i i i i i B DRSZ 0FF DRSZ 0FE LD A X DRSZ 0FD DIR DRSZ 0FC LD Md DRSZ 0FB LD A Xb DRSZ 0FA LD A Xa DRSZ 0F9 IFNE A B DRSZ 0F8 NOP DRSZ 0F7 DRSZ 0F6 X A X DRSZ 0F5 RPND DRSZ 0F4 VIS DRSZ 0F3 X A Xb DRSZ 0F2 X A Xa DRSZ 0F1 DRSZ 0F0 RRCA C Note The opcode 60 Hex is also the opcode for IFBIT iA i is the immediate data Md is a directly addressed memory location is an unused opcode JP b21 LD 0FA JP b6 where JP b22 LD 0F9 JP b7 i JP b13 JP b29 LD 0F2 i i JP b14 JP b30 LD 0F1 D i E JP b15 JP b31 LD 0F0 F Opcode Table LD A B JSRL i JMPL LD A Bb LD A Ba IFEQ Md i RLCA XA B JID LAID XA Bb XA Ba SC RC A i i LD B LD B i LD A Md X A Md LD Bb i LD B a i IFNE A i LD A OR A XOR A i AND A i ADD A i IFGT A i IFEQ A i SUBC A i ADC A 9 6 SBIT RBIT 3 B 3 B DECA RETI i RET SBIT RBIT 7 B 7 B SBIT RBIT 6 B 6 B SBIT RBIT 5 B 5 B SBIT RBIT 4 B 4 B SBIT RBIT 2 B 2 B SBIT RBIT 0 B 0 B LD B LD B LD B LD B LD B LD B LD B LD B IFBIT PUSHA LD B 7 B IFBIT DCORA LD B 6 B INCA RETSK LD B LD B LD B LD B IFBIT SWAPA LD B 5 B IFBIT CLRA 4 B IFBIT 3 B IFBIT 2 B IFBIT 1 B SBIT RBIT 1 B 1 B POPA 5 IFBIT ANDSZ LD B 0 B A i IFNC IFC OR A B XOR A B AND A B ADD A B IFGT A B IFEQ A B SUBC A B i ADC A B 7 UPPER NIBBLE 8 4 3 JSR x900 ­x9FF JSR x800 ­x8FF JSR x700 ­x7FF JSR x600 ­x6FF JSR x500 ­x5FF JSR x400 ­x4FF JSR x300 ­x3FF JSR x200 ­x2FF JSR x100 ­x1FF JSR x000 ­x0FF 2 JMP x900 ­x9FF JMP x800 ­x8FF JMP x700 ­x7FF JMP x600 ­x6FF JMP x500 ­x5FF JMP x400 ­x4FF JMP x300 ­x3FF JMP x200 ­x2FF JMP x100 ­x1FF JMP x000 ­x0FF 1 0 8 7 6 5 4 3 2 1 JP a 26 JP a 10 9 JP a 25 JP a 9 JP a 24 JP a 8 JP a 23 JP a 7 JP a 22 JP a 6 JP a 21 JP a 5 JP a 20 JP a 4 JP a 19 JP a 3 JP a 18 JP a 2 JP a 17 INTR 00 IFBNE 0F JSR JMP JP a 32 JP a 16 F xF00 ­xFFF xF00 ­xFFF 01 IFBNE 0E JSR JMP JP a 31 JP a 15 E xE00 ­xEFF xE00 ­xEFF 02 IFBNE 0D JSR JMP JP a 30 JP a 14 D xD00 ­xDFF xD00 ­xDFF 03 IFBNE 0C JSR JMP JP a 29 JP a 13 C xC00 ­xCFF xC00 ­xCFF 04 IFBNE 0B JSR JMP JP a 28 JP a 12 B xB00 ­xBFF xB00 ­xBFF 05 IFBNE 0A JSR JMP JP a 27 JP a 11 A xA00 ­xAFF xA00 ­xAFF 06 IFBNE 9 07 IFBNE 8 08 IFBNE 7 09 IFBNE 6 0A IFBNE 5 0B IFBNE 4 0C IFBNE 3 0D IFBNE 2 0E IFBNE 1 0F IFBNE 0 LOWER NIBBLE www national com Mask Options Development Support The mask programmable options are shown below The options are programmed at the same time as the ROM pattern submission Summary iceMASTER IM-COP8 400 Full feature in-circuit emulation for all COP8 products A full set of COP8 Basic and Feature Family device and package specific probes are available OPTION 1 CLOCK CONFIGURATION e 1 Crystal Oscillator (CKI 10) G7 (CKO) is clock generator output to crystal resonator CKI is the clock input e 2 Single-pin RC controlled oscillator (CKI 10) G7 is available as a HALT restart and or general purpose input OPTION 2 HALT COP8 Debug Module Moderate cost in-circuit emulation and development programming unit Assembler COP8-DEV-IBMA A DOS installable cross development Assembler Linker Librarian and Utility Software Development Tool Kit C Compiler COP8C A DOS installable cross development Software Tool Kit OTP EPROM Programmer Support Covering needs e 1 e 2 Enable HALT mode Disable HALT mode OPTION 3 BONDING OPTIONS e 1 28-Pin DIP e 2 28-Pin SO e 3 N A e 4 20-Pin SO http www national com from engineering prototype pilot production to full production environments 34 Development Support (Continued) IceMASTER (IM) IN-CIRCUIT EMULATION The iceMASTER IM-COP8 400 is a full feature PC based in-circuit emulation tool developed and marketed by MetaLink Corporation to support the whole COP8 family of products National is a resale vendor for these products See Figure 15 for configuration Instruction by instruction memory register changes displayed on source window when in single step operation Single base unit and debugger software reconfigurable to support the entire COP8 family only the probe personality needs to change Debugger software is processor customized and reconfigured from a master model file The iceMASTER IM-COP8 400 with its device specific COP8 Probe provides a rich feature set for developing testing and maintaining product Processor specific symbolic display of registers and bit level assignments configured from master model file Real-time in-circuit emulation full 2 4V­5 5V operation Halt Idle mode notification On-line HELP customized to specific processor using range full DC-10 DC-10 MHz clock Chip options are programmable or jumper selectable master model file Direct connection to application board by package com- Includes a copy of COP8-DEV-IBMA assembler and link- patible socket or surface mount assembly er SDK Full 32 KByte of loadable programming space that over- IM Order Information lays (replaces) the on-chip ROM or EPROM On-chip RAM and I O blocks are used directly or recreated on the probe as necessary Base Unit IM-COP8 400-1 struction and eight unspecified circuit connectable trace lines Display can be HLL source (e g C source) assembly or mixed A full 64k hardware configurable break trace on trace iceMASTER Base Unit 110V Power Supply IM-COP8 400-2 Full 4k frame synchronous trace memory Address in- iceMASTER Base Unit 220V Power Supply iceMASTER Probe off control and pass count increment events COP8AC-IM28N COP8AC-IM28N COP8AC-IM20N COP8AC-IM20N Tool set integrated interactive symbolic debugger supports both assembler (COFF) and C Compiler ( COD) linked object formats 28 DIP 20 DIP Surface Mount Adapter Real time performance profiling analysis selectable MHW-SOIC28 MHW-SOIC28 MHW-SOIC20 MHW-SOIC20 bucket definition Watch windows content updated automatically at each 28 SO 20 SO execution break TL DD 12865 ­ 17 FIGURE 15 COP8 iceMASTER Environment 35 http www national com Development Support (Continued) Tool set integrated interactive symbolic debugger sup- IceMASTER DEBUG MODULE (DM) ports both assembler (COFF) and C Compiler ( COD) SDK linked object