CMR3000-D0X FI-01621 CMR3000 CMR3000-D01 J-STD-020D - Datasheet Archive

 

Product Family Specification CMR3000-D0X Series 3-axis gyro CMR3000-D0X Series TABLE OF CONTENTS 1 General Description

 

Doc.Nr. 82112900.A.02 Product Family Specification CMR3000-D0X CMR3000-D0X Series 3-axis gyro CMR3000-D0X CMR3000-D0X Series TABLE OF CONTENTS 1 General Description . 4 1.1 Introduction .4 1.2 Functional Description .4 1.2.1 Sensing element.4 1.2.2 Interface IC.4 1.2.3 Factory calibration .5 1.2.4 Supported features .5 1.2.5 Operation modes.5 1.2.5.1 1.2.5.2 1.2.5.3 1.2.6 1.2.7 Power Down .5 Stand By .5 Measurement.5 Interrupt.5 Operational flow chart .6 2 Reset and power up, Operation Modes, HW functions and Clock . 7 2.1 Reset and power up.7 2.2 Power Down mode.7 2.3 Measurement Mode .7 2.3.1 Description.7 2.3.2 Usage.7 2.4 Stand By Mode .7 2.5 Interrupt function (INT-pin) .7 2.6 Clock .7 3 Addressing Space . 8 3.1 Register Description.8 3.2 Non-volatile memory .8 3.3 Registers.8 4 Serial Interfaces . 11 4.1 SPI Interface .11 4.1.1 SPI frame format.11 4.1.2 Examples of SPI communication.12 4.1.2.1 4.1.3 4.1.4 Example of register read.12 Multiple slave devices in SPI bus .12 Output register data refresh.13 4.2 I2C Interface .13 4.2.1 I2C frame format.13 VTI Technologies Oy Myllynkivenkuja 6 P.O. Box 27 FI-01621 FI-01621 Vantaa www.vti.fi Doc.Nr. 82112900.A.02 2/ 26 Rev. A.02 CMR3000-D0X CMR3000-D0X Series 4.2.1.1 4.2.1.2 4.2.2 4.2.3 4.2.4 I2C write mode .13 I2C read mode.13 Examples of I2C communication.14 Output register data refresh.16 Electrical Characteristics .16 4.3 Absolute maximum ratings.16 4.4 Power Supply .16 4.5 Digital I/O Specification.16 4.5.1 Digital I/O DC characteristics .16 4.5.2 Digital I/O level shifter.16 4.5.3 SPI AC characteristics .17 4.5.4 I2C AC characteristics .17 5 Package Characteristics. 18 5.1 Dimensions.18 6 Application information . 19 6.1 Pin Description.19 6.2 Recommended circuit diagram .19 6.3 Recommended PWB layout .20 6.4 Mounting recommendations.21 6.5 Assembly instructions .21 6.6 Tape and reel specifications.21 7 Data sheet references . 22 7.1 Offset.22 7.1.1 Offset calibration error .22 7.1.2 Offset temperature error.22 7.2 Sensitivity .22 7.2.1 Sensitivity calibration error.22 7.2.2 Sensitivity temperature error .23 7.3 Linearity .23 7.4 Noise .24 7.5 Bandwidth.24 7.6 Cross-axis sensitivity .24 7.7 Turn-on time .25 8 Document Change Control. 26 VTI Technologies Oy Myllynkivenkuja 6 P.O. Box 27 FI-01621 FI-01621 Vantaa www.vti.fi Doc.Nr. 82112900.A.02 3/ 26 Rev. A.02 CMR3000-D0X CMR3000-D0X Series 1 General Description 1.1 Introduction CMR3000-D0X CMR3000-D0X is a three axis gyroscope family targeted for high volume products requiring small size, low price and low power consumption. It consists of a 3D-MEMS sensing element and a signal conditioning ASIC in a wafer level package. Block diagram of CMR3000-D0X CMR3000-D0X is shown in Figure 1 below. Sens X Sens Y Sens Z Sens P Drive CSA & Highpass Filter PLL & Drive Bias Phase Detection Calibration & Low-pass Filter ADC Low-pass Filter Low-pass Filter SCK/SCL SPI & I2C i/f Oscillator Reference NonVolatile Memory MOSI/SDA CSB Low-pass Filter Bias MISO Control & INT INT Figure 1. CMR3000-D0X CMR3000-D0X block diagram with digital SPI and I2C interface This document, no. 82112900, describes the product specification (e.g. operation modes, user accessible registers, electrical properties and application information) for the CMR3000-D0X CMR3000-D0X family. The specification for an individual sensor is available in the corresponding data sheet. 1.2 1.2.1 Functional Description Sensing element The sensing element is manufactured using proprietary bulk 3D-MEMS process, which enables robust, stable and low noise & power capacitive sensors. The sensing element consists of a primary resonator and three secondary resonators. Primary resonator is driven by the ASIC and the Coriolis force will couple to the secondary resonators. Detected signal will be converted into a phase difference and then into a voltage in the signal conditioning ASIC. 1.2.2 Interface IC CMR3000 CMR3000 includes an internal oscillator, reference and non-volatile memory that enable the sensor's autonomous operation within a system. The sensing element is interfaced via drive circuitry, charge-sensitive-amplifiers (CSA) and phase detector used for XYZ-angular rate detection. Followed by calibration and filtering in analog domain, the signal is A/D-converted and then digitally filtered. Sensor output is user selectable digital SPI or I2C interface. Angular rate data can be read via the serial bus and in power down mode the device is in-active. Measurement bandwidth can be selected by register command. VTI Technologies Oy Myllynkivenkuja 6 P.O. Box 27 FI-01621 FI-01621 Vantaa www.vti.fi Doc.Nr. 82112900.A.02 4/ 26 Rev. A.02 CMR3000-D0X CMR3000-D0X Series 1.2.3 Factory calibration Sensors are factory calibrated. Trimmed parameters are sensitivity, offset, internal current & voltage references and frequency of the internal oscillator. Calibration parameters will be read automatically from the internal non-volatile memory during sensor startup. 1.2.4 Supported features Supported features are listed in Table 1 below. Table 1. CMR3000-D0X CMR3000-D0X devices' summary. Features Supply voltage I/O voltage Measuring range Resolution Sensitivity Interface Clock 1.2.5 1.2.5.1 CMR3000-D01 CMR3000-D01 2.5 V ­ 3.6 V 1.6 V ­ 3.6 V 2000 dps 0.75 dps 1.33 count/dps SPI max 500 kHz, I2C fast mode 400 kHz Internal Operation modes Power Down In Power Down (PD) mode device's volatile registers keep their contents and the current consumption is minimized. Power down mode is the default mode after start up. 1.2.5.2 Stand By Stand By (SB) mode can be used to start-up the sensor quickly. In SB mode only the primary resonator loop is on with reduced bias current while the other blocks are off. 1.2.5.3 Measurement In Measurement mode (Meas) the sensor offers angular rate information via the digital SPI/I2C interface. Interrupt can be activated via INT-pin, when each xyz-angular rate sample is ready to be read. Measurement bandwidth can be selected through register command. 1.2.6 Interrupt The CMR3000 CMR3000 has a dedicated output pin (INT) to be used as the interrupt for the master controller. Interrupt conditions can be activated and deactivated via the SPI or I2C bus. VTI Technologies Oy Myllynkivenkuja 6 P.O. Box 27 FI-01621 FI-01621 Vantaa www.vti.fi Doc.Nr. 82112900.A.02 5/ 26 Rev. A.02 CMR3000-D0X CMR3000-D0X Series 1.2.7 Operational flow chart CMR3000 CMR3000 power up CMR3000 CMR3000 in power down mode CMR3000 CMR3000 operation mode can 2 be changed via SPI/I C bus Activate CMR3000 CMR3000 operation 2 mode via SPI/I C bus Measurement mode Stand By mode Power Down mode Low pass filtered XYZ angular rate data available No angular rate data available. Primary loop is active. No angular rate data available. All functions de-activated. Measurement Bandwidths: 20Hz, 80Hz Approx 12.5 or 50 ms start-up time (depends on the Measurement Bandwidth) from Stand By to the Measurement mode INT-pin gives interrupt when new data is available Additional configuration option: · INT-pin data ready functionality can be disabled Note: To ensure proper operation, device must be started up in Measurement mode prior changing to Stand By mode. CMR3000 CMR3000 operation in application Figure 2. CMR3000 CMR3000 operational flow chart. VTI Technologies Oy Myllynkivenkuja 6 P.O. Box 27 FI-01621 FI-01621 Vantaa www.vti.fi Doc.Nr. 82112900.A.02 6/ 26 Rev. A.02 CMR3000-D0X CMR3000-D0X Series 2 Reset and power up, Operation Modes, HW functions and Clock 2.1 Reset and power up The CMR3000 CMR3000 has internal power-on reset circuit. It releases the internal reset-signal once the power supplies will be within the specified range. After releasing the internal reset, the CMR3000 CMR3000 will read configuration and calibration data from the non-volatile memory to volatile registers. Then the CMR3000 CMR3000 will make parity check to the read memory content. The STATUS register's PERRbit="0" shows successful memory read operation. Device can be externally reset by writing RESET=1b to CTRL register and then waiting 2 ms for reset to complete. 2.2 Power Down mode The CMR3000-D0X CMR3000-D0X enters the power down mode by default after power-on reset and initialization of the volatile registers. PD can also be set by writing MODE[1:0] = 00b to CTRL register. Output registers will keep their content in the power down mode. 2.3 2.3.1 Measurement Mode Description The CMR3000-D0X CMR3000-D0X is set to a measurement mode by writing MODE[1:0] = 1Xb to CTRL register. Data will be reliable in the output registers after the product specific turn-on time. Sample rate is 2000 Hz. The measurement bandwidth is 80 Hz (MODE[1:0] = 11b) or 20 Hz (MODE[1:0] = 10b). INT-pin gives an interrupt by default when new data is available. 2.3.2 Usage Angular rate data can be read from data output registers X_LSB, X_MSB, Y_LSB, Y_MSB, Z_LSB and Z_MSB. See section 2.5 for INT-pin configuration details. 2.4 Stand By Mode The CMR3000-D0X CMR3000-D0X is set to Stand By mode by writing MODE[1:0] = 01b to CTRL register. No measurement data will be available in the output registers. As the startup-up time from Stand By to Measurement mode is much faster than from Power Down to Measurement mode, Stand By mode can be used to optimize system level power consumption. Due to operation principle, Stand By mode must be preceded by starting up the device in Measurement mode. 2.5 Interrupt function (INT-pin) Interrupt polarity (active high/low) can be configured with CTRL register's INT_LEVEL bit. INT pin is automatically cleared by reading the angular rate output data. INT-pin data ready functionality can be disabled by setting the CTRL register's INT_DIS bit. See section 3.3 for CTRL and INT_STATUS register details. 2.6 Clock The CMR3000 CMR3000 has an internal factory trimmed oscillator and clock generator. VTI Technologies Oy Myllynkivenkuja 6 P.O. Box 27 FI-01621 FI-01621 Vantaa www.vti.fi Doc.Nr. 82112900.A.02 7/ 26 Rev. A.02 CMR3000-D0X CMR3000-D0X Series 3 Addressing Space The CMR3000 CMR3000 register contents and bit definitions are described in more detail in the following sections. 3.1 Register Description The CMR3000 CMR3000 addressing space is presented in Table 2 below. Table 2. List of registers Name Description 00h WHO_AM_I Identification register R 01h REVID ASIC revision ID, fixed in metal R 02h CTRL RW 03h STATUS Configuration (POR, operation modes) Status (POR, EEPROM parity) Reg. type Output Output Conf R Output R Output Output Output Output Output Output Address 04h-08h Mode (R, RW, NV) Reserved 0Ch Angular rate X LSB X_LSB 0Dh X_MSB Angular rate X MSB R 0Eh Y_LSB Angular rate Y LSB R 0Fh Y_MSB Angular rate Y MSB R 10h Z_LSB Angular rate Z LSB R 11h Z_MSB Angular rate Z MSB R 12h-21h Reserved 22h I2C_ADDR 23h-25h I2C device address RW Conf Reserved 26h Product data register PDR 27h-3Fh R output Reserved Address is the register address in hex format. RW ­ Read / Write register, R ­ Read-only register, NV ­ non-volatile register content. 3.2 Non-volatile memory The CMR3000 CMR3000 has an internal non-volatile memory for calibration and configuration data. Memory content will be programmed during production and is not user configurable. Initial configuration values mirrored to volatile registers after reset can be found in the following section 3.3. 3.3 Registers Address: 00h Register name: WHO_AM_I, Identification register Initial Bits Mode Name Description Value 7 R 0 Reserved 6:0 R xxh Address: 01h Register name: REVID, ASIC revision ID Initial Bits Mode Name Value 7:4 R 1h REVMAJ 3:0 R 0h REVMIN VTI Technologies Oy Myllynkivenkuja 6 P.O. Box 27 FI-01621 FI-01621 Vantaa www.vti.fi Doc.Nr. 82112900.A.02 Identification register Description Major revision number Minor revision number (metal mask change) 8/ 26 Rev. A.02 CMR3000-D0X CMR3000-D0X Series Address: 02h Register name: CTRL, Control register Initial Bits Mode Name Value 7 RW 0 RESET 6 RW 0 INT_LEVEL 5 4 RW 0 0 I2C_DIS 3 2:1 RW 0 0 MODE[1:0] 0 RW 0 INT_DIS Description 1 ­ device in reset stage 0 ­ reset cleared 0 ­ Interrupt is active when INT pin is set to logic high 1 ­ Interrupt is active when INT pin is set to logic low reserved 0 ­ I2C interface enabled 1 ­ I2C interface disabled. See section 4.1.3 for details. Reserved. Write `0'. 00 ­ Power down mode, default mode. 01 ­ Stand by mode TBD 10 ­ Measurement mode, BW=20 Hz. 11 ­ Measurement mode, BW=80 Hz. 0 ­ Interrupt enabled: data ready 1 ­ Interrupts disabled Note that after changing MODE bits it may take some time to recover the target operating state. Address: 03h Register name: STATUS, Status register Initial Bits Mode Name Value 7:4 0h 3 R 0 PORST 2:1 0 R 0h 0 PERR Description Reserved 1 means Power-on-Reset state. Reading the register sets always bit to 0. Reserved 0 ­ No EEPROM Parity Error 1 ­ EEPROM Parity Error. Reading this register sets bit to `0' Address: 0Ch Register name: X_LSB, X-channel LSB output register Initial Bits Mode Name Description Value 7:0 R 0h X_LSB See SPI data frame description for more info. Address: 0Dh Register name: X_MSB, X-channel MSB output register Initial Bits Mode Name Description Value 7:0 R 0h X_MSB See SPI data frame description for more info. Address: 0Eh Register name: Y_LSB, Y-channel LSB output register Initial Bits Mode Name Description Value 7:0 R 0h Y_LSB See SPI data frame description for more info. VTI Technologies Oy Myllynkivenkuja 6 P.O. Box 27 FI-01621 FI-01621 Vantaa www.vti.fi Doc.Nr. 82112900.A.02 9/ 26 Rev. A.02 CMR3000-D0X CMR3000-D0X Series Address: 0Fh Register name: Y_MSB, Y-channel MSB output register Initial Bits Mode Name Description Value 7:0 R 0h Y_MSB See SPI data frame description for more info. Address: 10h Register name: Z_LSB, Z-channel LSB output register Initial Bits Mode Name Description Value 7:0 R 0h Z_LSB See SPI data frame description for more info. Address: 11h Register name: Z_MSB, Z-channel MSB output register Initial Bits Mode Name Description Value 7:0 R 0h Z_MSB See SPI data frame description for more info. The bit level description for angular rate data from X_LSB.Z_MSB registers is presented in Table 3 below. The acceleration data is presented in 2's complement format. At 0 dps rate the output is ideally 0h. Table 3. Bit level description in [dps] for angular rate registers of CMR3000-D01 CMR3000-D01. MSB B7 x x B6 x x B5 s +/- B4 d11 1536 LSB B3 d10 768 B2 d9 384 B1 d8 192 B0 d7 96 B7 d6 48 B6 d5 24 B5 d4 12 B4 d3 6 B3 d2 3 B2 d1 1.5 B1 B0 d0 x 0.75 0.375 s = sign bit x= don't care Address: 22h Register name: I2C_ADDR, Device address for I2C bus Initial Bits Mode Name Description Value Reserved 7:6 0 5:0 RW 0Fh ADDR[6:1] 6 MSB bits of the 7-bit device address for I2C bus. LSB bit of the I2C address ADDR[0] is according to MISO pin state. I.e. I2C address can be selected between 1Eh and 1Fh. Register content is non-volatile. Address: 26h Register name: PDR, Product data register Initial Bits Mode Name Value 7:0 R PDR[7:0] VTI Technologies Oy Myllynkivenkuja 6 P.O. Box 27 FI-01621 FI-01621 Vantaa www.vti.fi Doc.Nr. 82112900.A.02 Description Linearization parameters 10/ 26 Rev. A.02 CMR3000-D0X CMR3000-D0X Series 4 Serial Interfaces Communication between the CMR3000 CMR3000 sensor and master controller is based on serial data transfer and a dedicated interrupt line (INT-pin). Two different serial interfaces are available for the CMR3000 CMR3000 sensor: SPI and I2C (Phillips specification V2.1). Selection between these two interfaces is done using the chip select signal. The I2C interface can be also disabled by re-configuring register content. The CMR3000 CMR3000 acts as a slave on both the SPI and I2C bus. 4.1 SPI Interface SPI bus is a full duplex synchronous 4-wire serial interface. It consists of one master device and one or more slave devices. The master is defined as a micro controller providing the SPI clock, and the slave as any integrated circuit receiving the SPI clock from the master. The CMR3000 CMR3000 sensor always operates as a slave device in master-slave operation mode. A typical SPI connection is presented in Figure 3. Figure 3. Typical SPI connection The data transfer uses the following 4-wire interface: MOSI MISO SCK CSB 4.1.1 µC CMR3000 CMR3000 CMR3000 CMR3000 µC µC CMR3000 CMR3000 µC CMR3000 CMR3000 master out slave in master in slave out serial clock chip select (low active) SPI frame format CMR3000 CMR3000 SPI frame format and transfer protocol is presented in Figure 4 below. CSB SCK 1 MOSI A5 MISO `X' 2 A4 3 A3 4 A2 5 A1 6 A0 7 RB/W PORST 8 9 10 11 12 13 14 15 16 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Figure 4. SPI frame format Each communication frame contains 16 bits. The first 8 bits in MOSI line contain info about the register address being accessed and the operation (read/write). The first 6 bits define the 6 bit VTI Technologies Oy Myllynkivenkuja 6 P.O. Box 27 FI-01621 FI-01621 Vantaa www.vti.fi Doc.Nr. 82112900.A.02 11/ 26 Rev. A.02 CMR3000-D0X CMR3000-D0X Series address for the selected operation, which is defined by bit 7 (`0' = read `1' = write), which is followed by one zero bit. The later 8 bits in the MOSI line contain data for a write operation and are `don't-care' for a read operation. CMR3000 CMR3000 samples bits in from MOSI line on the rising edge of SCK and bits out to MISO line on falling edge of SCK. The first bits in MISO line are not defined bit (bit 1), fixed zero bit (bit 2), power reset status (bits 35), fixed zero bit (bit6), fixed one bit (bit7) and fixed zero bit (bit8). The later 8 bits contain data for a read operation. During the write operation, these data bits are zero. For write commands, data is written into the addressed register on the falling edge of 16th SCK pulse. For read commands, data is latched into the internal SPI output register (shift register) on the 8th rising edge of SCK. The output register is shifted out MSB first over MISO output. When the CSB is high state between data transfers, the MISO line is in the high-impedance state. Multiple read operation mode (decrement reading) is supported for angular rate output data registers (0Ch.11h). Reading can be started from any of these registers and address is reduced by one continuously. From register address 0Ch the address jumps to 11h. 4.1.2 4.1.2.1 Examples of SPI communication Example of register read An example of Z-axis angular read command is presented in Figure 5. The master gives the register address to be read via the MOSI line: '11' in hex format and '010001' in binary format, register name is Z_MSB. 7th bit is set to '0' to indicate the read operation. The sensor replies to a requested operation by transferring the register content via MISO line. After transferring the asked Z_MSB register content, the master gives next register address to be read: '10' in hex format and '010000' in binary format, register name is Z_LSB. The sensor replies to the requested operation by transferring the register content MSB first. Figure 5. An example of SPI read communication. 4.1.3 Multiple slave devices in SPI bus Since both SPI and I2C interfaces are enabled by default, certain precautions should be taken care of when the CMR3000 CMR3000 is connected to a SPI bus with multiple slave devices. In case of multiple devices on same SPI bus, it's important to prevent MOSI_SDA pin changes during SCK_SCL pin high state. If the MOSI_SDA pin state is changed when the SCK_SCL pin is in high state, the I2C transmission is engaged, see Figure 6 below. VTI Technologies Oy Myllynkivenkuja 6 P.O. Box 27 FI-01621 FI-01621 Vantaa www.vti.fi Doc.Nr. 82112900.A.02 12/ 26 Rev. A.02 CMR3000-D0X CMR3000-D0X Series Figure 6. MOSI_SDA pin change during SCK_SCL high state engages I2C transmission. In cases with multiple slaves in SPI bus it is recommended that I2C transmission is disabled by setting I2C_DIS bit to '1' in CRTL register. After CMR3000 CMR3000 start up the I2C_DIS bit is always 0 (I2C transmission enabled). 4.1.4 Output register data refresh When the CSB is pulled `0', the latest data is available in the output registers. Output register data refresh is enabled only when CSB is `1'. 4.2 I2C Interface I2C is a 2-wire serial interface. It consists of one master device and one or more slave devices. The master is defined as a micro controller providing the serial clock (SCL), and the slave as any integrated circuit receiving the SCL clock from the master. The CMR3000 CMR3000 sensor always operates as a slave device in master-slave operation mode. When using an SPI interface, a hardware addressing is used (slaves have dedicated CSB signals), the I2C interface uses a software based addressing (slave devices have dedicated bit patterns as addresses). The default I2C device address for CMR3000 CMR3000 is 1Eh or 1Fh (pre-programmed during CMR3000 CMR3000 production). LSB bit of the I2C address is according to MISO pin state. The CMR3000 CMR3000 is compatible to the Philips I2C specification V2.1. Main used features of the I2C interface are: - 7-bit addressing, CMR3000 CMR3000 I2C device address is TBD - Supports standard mode and fast mode - Start / Restart / Stop - Slave transceiver mode - Designed for low power consumption - Multiple read operation mode (decrement reading) · reading of any register decrements data address by one even if only one register is read · from register address 0Ch address jumps to 11h 4.2.1 4.2.1.1 I2C frame format I2C write mode In I2C write mode, the first 8 bits after device address define the CMR3000 CMR3000 internal register address to be written. 4.2.1.2 I2C read mode The read mode operates as described in Philips I2C specification. I2C read operation returns the content of the register which address is defined in I2C read frame. Read data is acknowledged by I2C master. VTI Technologies Oy Myllynkivenkuja 6 P.O. Box 27 FI-01621 FI-01621 Vantaa www.vti.fi Doc.Nr. 82112900.A.02 13/ 26 Rev. A.02 CMR3000-D0X CMR3000-D0X Series 4.2.2 Examples of I2C communication Examples of I2C communication are presented below in Error! Reference source not found. Address byte includes 7 device address bits (1E=0011110b) followed by the R/W bit. Figure 7. I2C format VTI Technologies Oy Myllynkivenkuja 6 P.O. Box 27 FI-01621 FI-01621 Vantaa www.vti.fi Doc.Nr. 82112900.A.02 14/ 26 Rev. A.02 0 0 1 7 bit I2C address 0x1E 1 SDA SCK 0 1 SDA SCK ACK 0 1 D6 D5 D4 1 1 D3 1 1 1 8 bit Y_MSB data from CMR3000 CMR3000 D7 CMR3000 CMR3000 replies 7 bit I2C address 0x1E 0 Master controls the SDA line Read CMR3000 CMR3000 angular rates 7 bit I2C address 0x1E 0 Master controls the SDA line Write CMR3000 CMR3000 CTRL register Start condition from Start condition from Start condition from D2 1 1 1 D1 0 0 0 ACK W CMR W ACK CMR Read (=1) / Write (=0) ACK W CMR D0 ACK 0 0 0 0 0 0 0 0 1 0 0 0 D6 D5 D4 D3 8 bit Y_LSB data from CMR3000 CMR3000 D7 CMR3000 CMR3000 replies 8 bit register address 0x11 (Z_MSB) 0 Master controls the SDA line 8 bit register address 0x02 0 Master controls the SDA line 8 bit register address 0x01 0 Master controls the SDA line D2 0 0 0 D1 0 1 0 ACK ACK CMR ACK CMR D0 ACK 1 0 1 CMR CMR3000 CMR3000 acknowledge SDA master master master Master acknowledge 0 0 0 1 D5 D4 D3 8 bit X_MSB data from CMR3000 CMR3000 D6 CMR3000 CMR3000 replies D7 0 0 7 bit I2C address 0x1E 0 Master controls the SDA line 8 bit data to register, 0x04 0 Master controls the SDA line 0 1 7 bit I2C address 0x1E 0 Master controls the SDA line master master CMR3000 CMR3000 acknowledge Read (=1) / Write (=0) Read (=1) / Write (=0) Restart condition from Restart condition from CMR3000 CMR3000 acknowledge CMR3000 CMR3000 acknowledge Master acknowledge 1 1 D2 1 1 1 D1 0 1 1 0 ACK D0 ACK 0 CMR 0 ACK R Read (=1) / Write (=0) ACK R master 0 1 D6 D5 D4 D3 0 D6 D5 D4 D3 D2 8 bit Z_MSB data from CMR3000 CMR3000 D7 CMR3000 CMR3000 replies 8 bit X_LSB data from CMR3000 CMR3000 D7 0 REVID number from CMR3000 CMR3000 0 CMR3000 CMR3000 replies CMR3000 CMR3000 replies Read (=1) / Write (=0) CMR3000 CMR3000 acknowledge CMR3000 CMR3000 acknowledge Master acknowledge CMR3000 CMR3000 acknowledge Master acknowledge CMR3000 CMR3000 acknowledge Stop condition from CMR3000 CMR3000 acknowledge Master controls the SDA line D1 D2 0 D0 NACK Master D1 0 acknowledge 1 NACK Master D0 ACK Master does not SCK Master does not acknowledge Master acknowledge Doc.Nr. 82112900.A.02 master VTI Technologies Oy Myllynkivenkuja 6 P.O. Box 27 FI-01621 FI-01621 Vantaa www.vti.fi Stop condition from Read CMR3000 CMR3000 asic REVID number Stop condition from master D6 D5 D4 D3 8 bit Z_LSB data from CMR3000 CMR3000 D7 CMR3000 CMR3000 replies D2 D1 D0 CMR3000-D0X CMR3000-D0X Series Figure 8 Bit level I2C format description 15/ 26 Rev. A.02 CMR3000-D0X CMR3000-D0X Series 4.2.3 Output register data refresh Angular rate output registers are refreshed when the address of the output register is written. Use decrement reading to ensure XYZ data from the same moment. 4.2.4 Electrical Characteristics All voltages are reference to ground. Currents flowing into the circuit have positive values. 4.3 Absolute maximum ratings The absolute maximum ratings of the CMR3000 CMR3000 are presented in Table 4 below. Table 4. Absolute maximum ratings of the CMR3000 CMR3000 Parameter Supply voltage (Vdd, DVIO) Voltage at input / output pins ESD (Human body model) Storage temperature Storage / operating temperature Mechanical shock * Exposure to ultrasonic energy (e.g. ultra sonic washing or welding) Value -0.3 to +3.6 -0.3 to (Vdd + 0.3) ±2 -40 . +125 -40 . +85 < 10 000 Unit V V kV °C °C g Not allowed * 1 m drop on concrete may cause >>10000 g shock. 4.4 Power Supply Please refer to the corresponding product datasheet. 4.5 4.5.1 Digital I/O Specification Digital I/O DC characteristics Table 5. DC characteristics of digital I/O pins. No. Parameter Conditions CSB with pull up SCK and MOSI (I2C disabled) with pull down SDA and SCL without pull up Pull up/down resistor 2 VIN = DVIO 2a. Input Leakage Input high voltage 3 Input low voltage 4 Hysteresis 5 Output terminal: MISO, SDA, INT Output high voltage I > -1 mA 7 Output low voltage I < 1 mA 8 Tristate leakage 0 < VMISO < DVIO 9 4.5.2 Symbol RPUD IIN VIH VIL VHYST VOH VOL ILEAK Min Typ Max 160 TBD 0.7*Dvio TBD 0.3*Dvio 0.1*Dvio 0.7*Dvio 0 -0.5 Dvio 0.3*Dvio 0.5 Unit k µA V V V V V µA Digital I/O level shifter All the CMR3000 CMR3000 products have an internal level shifter that can be used to interface e.g. a micro controller using lower supply than the CMR3000 CMR3000. The level shifter is "programmed" by providing the supply voltage of the interfaced device to the DVIO-pin. Please refer to the corresponding product data sheet for details. VTI Technologies Oy Myllynkivenkuja 6 P.O. Box 27 FI-01621 FI-01621 Vantaa www.vti.fi Doc.Nr. 82112900.A.02 16/ 26 Rev. A.02 CMR3000-D0X CMR3000-D0X Series 4.5.3 SPI AC characteristics The AC characteristics of the CMR3000 CMR3000 SPI interface are defined in Figure 9 and in Table 6. TLS1 TCH TCL TLS2 TLH CSB SCK THOL MOSI TSET MSB in TVAL1 MISO DATA in LSB in TVAL2 MSB out TLZ DATA out LSB out Figure 9. Timing diagram for SPI communication. Table 6. AC characteristics of SPI communication. No . Parameter Conditions Symbol Min Typ Max Unit Terminal CSB, SCK 1 Time from CSB (10%) to SCK (90%) (1 TLS1 Tper/2 ns 2 Time from SCK (10%) to CSB (90%) (1 TLS2 Tper/2 ns 3 Time from CSB (90%) to SCK (90%) TLS3 Tper/4 ns 4 Time from SCK (10%) to CSB (10%) TLS4 Tper/4 ns TCL 0.8* Tper/2 Tper/2 ns TCH 0.8* Tper/2 Tper/2 ns Terminal SCK 5 SCK low time 6 SCK high time 7 CL at MISO < 50 pF CL at MISO < 50 pF SCK Frequency fsck = 1/Tper 0.5 MHz Terminal MOSI, SCK 8 9 Time from changing MOSI (10%, 90%) to SCK (90%) Data setup time Time from SCK (90%) to changing MOSI (10%, 90%) Data hold time TSET Tper/4 ns THOL Tper/4 ns Terminal MISO, CSB 10 11 Time from CSB (10%) to stable MISO (10%, 90%) Time from CSB (90%) to high (1 impedance state of MISO . CL at MISO < 50 pF CL at MISO < 50 pF TVAL1 Tper/4 ns TLZ Tper/4 ns CL at MISO < 50 pF TVAL2 1.3*Tp er/4 ns Terminal MISO, SCK 12 Time from SCK (10%) to stable MISO (1 (10%, 90%) . Terminal MOSI, CSB 13 Time between SPI cycles, CSB at high level (90%) 1) Tper is SCK period 4.5.4 TLH 12 µs I2C AC characteristics Please, see Phillips Semiconductors, The I2C bus specification, Version 2.1, January 2000, pp. 3133. VTI Technologies Oy Myllynkivenkuja 6 P.O. Box 27 FI-01621 FI-01621 Vantaa www.vti.fi Doc.Nr. 82112900.A.02 17/ 26 Rev. A.02 CMR3000-D0X CMR3000-D0X Series 5 5.1 Package Characteristics Dimensions The package dimensions are presented in Figure 10 below (dimensions in millimeters [mm]). Figure 10. Package dimensions in mm for reference only. Please check the corresponding data sheet for details. VTI Technologies Oy Myllynkivenkuja 6 P.O. Box 27 FI-01621 FI-01621 Vantaa www.vti.fi Doc.Nr. 82112900.A.02 18/ 26 Rev. A.02 CMR3000-D0X CMR3000-D0X Series 6 6.1 Application information Pin Description CMR3000 CMR3000 pin numbers are presented in Figure 12 below and pin descriptions in Table 7. Figure 11. CMR3000 CMR3000 sensing directions Figure 12. CMR3000 CMR3000 pin numbers Table 7. CMR3000 CMR3000 pin descriptions Pin # 1 2 3 4 5 6 7 8 9 10 6.2 Name CMR3000-D01 CMR3000-D01 DVSS INT MOSI_SDA CSB AVSS AVDD SCK_SCL MISO DVIO DVDD Digital ground Interrupt SPI Serial Data Input (MOSI) / I2C Serial Data (SDA) Chip select / I2C enable Analog ground Analog supply voltage SPI Serial Clock (SCK) / I2C Serial Clock (SCL) SPI Serial Data Output (MISO) / I2C slave address LSB ADDR[0] I/O Supply Digital supply voltage Recommended circuit diagram 1. Connect 100 nF SMD capacitor between each supply voltage and ground level. 2. Use separate regulator for digital IO supply (DVIO). 3. Serial interface (SPI or I2C) logical '1' level is determined by DVIO supply voltage level. Recommended circuit diagrams for the CMR3000 CMR3000 are presented in Figure 13 below. VTI Technologies Oy Myllynkivenkuja 6 P.O. Box 27 FI-01621 FI-01621 Vantaa www.vti.fi Doc.Nr. 82112900.A.02 19/ 26 Rev. A.02 CMR3000-D0X CMR3000-D0X Series I2C SPI 1 INT MOSI CSB 2 3 4 5 DVSS DVDD INT DVIO MOSI_SDA MISO CSB AVSS SCK_SCL AVDD 10 1 VDD 9 DVIO MISO 8 7 INT SDA SCK 6 2 3 4 5 100n 100n DVSS DVDD INT DVIO MOSI_SDA MISO CSB SCK_SCL AVSS 100n AVDD 10 VDD 9 DVIO 8 ADDR[0] 7 SCL 6 100n 100n 100n Figure 13 Recommended circuit diagrams for CMR3000-D0X CMR3000-D0X 6.3 Recommended PWB layout General PWB layout recommendations for CMR3000 CMR3000 products (refer to Figure 13 and Figure 14): 1. Locate 100 nF SMD capacitors right next to the CMR3000 CMR3000 package 2. Ensure low impedance by maximizing the ground plane under the component. Recommended PWB pad layout for CMR3000 CMR3000 is presented in Figure 14 below (dimensions in micrometers, [µm]). Figure 14. Recommended PWB pad layout for CMR3000 CMR3000. Recommended PWB layout for the CMR3000-D0X CMR3000-D0X is presented in Figure 15 below (circuit diagram presented in Figure 13 above). VTI Technologies Oy Myllynkivenkuja 6 P.O. Box 27 FI-01621 FI-01621 Vantaa www.vti.fi Doc.Nr. 82112900.A.02 20/ 26 Rev. A.02 CMR3000-D0X CMR3000-D0X Series Note the symmetrical ground plane under the component. Figure 15. Recommended PWB layout for CMR3000-D0X CMR3000-D0X with SPI interface (not actual size, for reference only). 6.4 Mounting recommendations For the best sensor stability mechanical stresses due to mounting should be minimized. Potential causes of mechanical stress to be avoided are · · · · · · Contact with other structures due to too small mechanical tolerances. Placement under or next to mechanical push button contacts. Locations near hot spots (micro controller, power amplifier etc) due to temperature effects. Mounting close to PWB attachment point e.g. screw or snap. PWB areas that can bend or vibrate. The use of under fill or coating. Please note that under fill or coating the neighboring component should not be in contact with the sensor. Due to sampled signal conditioning strong magnetic or electric fields may cause noise in the sensor output. Therefore mounting near strong magnetic or electric fields is not recommended. 6.5 Assembly instructions The Moisture Sensitivity Level (MSL) of the CMR3000 CMR3000 component is 2 according to the IPC/JEDEC J-STD-020D J-STD-020D. Please refer to the document TN81_CMR3000 CMR3000_Assembly_Instructions for more detailed information about CMR3000 CMR3000 assembly. 6.6 Tape and reel specifications Please refer to the document TN81_CMR3000 CMR3000_Assembly_Instructions for tape and reel specifications. VTI Technologies Oy Myllynkivenkuja 6 P.O. Box 27 FI-01621 FI-01621 Vantaa www.vti.fi Doc.Nr. 82112900.A.02 21/ 26 Rev. A.02 CMR3000-D0X CMR3000-D0X Series 7 Data sheet references 7.1 Offset CMR3000 CMR3000's offset will be calibrated in X = Y = Z = 0 dps. 7.1.1 Offset calibration error Offset calibration error is the difference between the sensor's actual output reading and the nominal output reading in calibration conditions. Error is calculated by Equation 1 Offset X -axisCalibEr = Output X -axis - Output , Sens where OutputX-axisCalibEr is sensor's X-axis calibration error in [dps], OutputX-axis is sensor's X-axis output reading [counts], Output is sensor's nominal output in 0 dps angular rate and Sens sensor's nominal sensitivity [counts/dps]. 7.1.2 Offset temperature error Offset temperature error is the difference between the sensor's output reading in different temperatures and the sensor's calibrated offset value at room temperature. Error is calculated by Equation 2 Offset X -axisTempEr @ T = Output X -axis @ T - Output X -axis @ RT Sens , where OutputX-axisTempEr@T is sensor's X-axis temperature error in [dps] in temperature T, OutputX-axis@T is sensor's X-axis output reading [counts] in temperature T, OutputX-axis@T X-axis output reading [counts] at room temperature RT and Sens sensor's nominal sensitivity [counts/g]. Sensor's angular rate is 0 dps for every measurement point. 7.2 Sensitivity During the sensitivity calibration, sensor is rotated in sensing directions (Figure 11) at ± dps rate. Sensitivity is calculated by Equation 3 SensY -axis = OutputY -axis @ + - OutputY -axis @ - 2 , where SensY-axis is sensor's Y-axis sensitivity in [counts/dps], OutputY-axis@+ sensor's Y-axis output reading [counts] in + dps angular rate and OutputY-axis@- is sensor's Y-axis output reading [counts] in - dps angular rate. 7.2.1 Sensitivity calibration error Sensitivity calibration error is the difference between sensor's measured sensitivity and the nominal sensitivity at room temperature conditions. Error is calculated by Equation 4 SensY - axisCalibEr = VTI Technologies Oy Myllynkivenkuja 6 P.O. Box 27 FI-01621 FI-01621 Vantaa www.vti.fi SensY - axis - Sens 100% , Sens Doc.Nr. 82112900.A.02 22/ 26 Rev. A.02 CMR3000-D0X CMR3000-D0X Series where SensY-axisCalibEr is sensor's Y-axis sensitivity calibration error in [%], SensY-axis sensor's Y-axis sensitivity [counts/dps] at room temperature conditions and Sens is sensor's nominal sensitivity [counts/dps]. 7.2.2 Sensitivity temperature error Sensitivity temperature error is the difference between sensor's sensitivity at different temperatures and the calibrated sensitivity. Error is calculated by Equation 5 SensY - axisTempEr @T = SensY - axis @ T - SensY - axis @ RT SensY - axis @ RT 100% , where SensY-axisTempEr@T is sensor's Y-axis sensitivity temperature error in [%] in temperature T, SensY-axis@T is sensor's measured Y-axis sensitivity [counts/dps] at temperature T and SensY-axis@RT is sensor's measured Y-axis sensitivity [counts/dps ] at room temperature RT. 7.3 Linearity During linearity measurement sensor is rotated in sensing directions and the rate is swept between ±FS. Linearity error is the deviation from the best bit straight line. See Figure 16. Angular rate reading from CMR3000 CMR3000 [dps] CMR3000 CMR3000 linearity error in [dps] at input angular rate -FS +FS CMR3000 CMR3000 output readings Sensor's ideal output Input angular rate [dps] Possible offset error is not included into linearity error Figure 16. CMR3000 CMR3000's linearity error at input angular rate . Linearity error is calculated by Equation 6 LinErZ -axis @ = Output Z -axis @ - Output@ Sens FS 100% , where LinErZ-axis@ is sensor's Z-axis linearity error [%FS] on input angular rate , OutputZ-axis@ is sensor's measured Z-axis output [counts] on input angular rate , Output@ is sensor's nominal output [counts] on input angular rate , Sens is sensor's nominal sensitivity [counts/dps] and FS is sensor's full scale measuring range [dps] (for example for CMR3000-D01 CMR3000-D01 with ±1000 dps setting FS = 1000 dps). VTI Technologies Oy Myllynkivenkuja 6 P.O. Box 27 FI-01621 FI-01621 Vantaa www.vti.fi Doc.Nr. 82112900.A.02 23/ 26 Rev. A.02 CMR3000-D0X CMR3000-D0X Series Sensor's ideal output Output@ (in Equation 6) is calculated by fitting a straight line to measured angular rate from ­FS to FS. 7.4 Noise Output noise nX, nY and nZ in X,Y and Z directions is the measured standard deviation of the output values when the sensor is not moved nor rotated (X = Y = Z = 0 dps) in room temperature. Average noise/axis is calculated by Equation 7 n= ( ) 1 2 2 2 n X + nY + nZ , 3 where n is sensor's noise [dps] per axis, nX is sensor's X-axis noise [dps], nY is sensor's Y-axis noise [dps] and nZ is sensor's Z-axis noise [dps]. 7.5 Bandwidth Signal bandwidth is measured with a rate table by rotating the table between two positions while sweeping the rotating frequency and keeping the angular rate constant. 7.6 Cross-axis sensitivity Cross-axis sensitivity is sum of the alignment and the inherent sensitivity errors. Cross-axis sensitivity of one axis is a geometric sum of the sensitivities in two perpendicular directions. Cross-axis sensitivity [%] of X-axis is given by Equation 8 2 2 S XY + S XZ 100%, Cross X = ± SX where SXY is X-axis sensitivity to Y-axis angular rate [Count/dps], SXZ is X-axis sensitivity to Z-axis angular rate [Count/dps] and SX is sensitivity of X-axis [Count/dps] angular rate. Cross-axis sensitivity [%] of Y-axis is given by Equation 9 2 CrossY = ± 2 SYX + SYZ 100%, SY where SYX is Y-axis sensitivity to X-axis angular rate [Count/dps], SYZ is Y-axis sensitivity to Z-axis angular rate [Count/dps] and SY is sensitivity of Y-axis [Count/dps] angular rate. Cross-axis sensitivity [%] of Z-axis is given by Equation 10 2 2 S + S ZY 100%, CrossZ = ± ZX SZ where SZX is Z-axis sensitivity to X-axis angular rate [Count/dps], SZY is Z-axis sensitivity to Y-axis angular rate [Count/dps] and SZ is sensitivity of Z-axis [Count/dps] angular rate. VTI Technologies Oy Myllynkivenkuja 6 P.O. Box 27 FI-01621 FI-01621 Vantaa www.vti.fi Doc.Nr. 82112900.A.02 24/ 26 Rev. A.02 CMR3000-D0X CMR3000-D0X Series Cross-axis sensitivity of CMR3000 CMR3000 family is measured in rate table over specified measurement range during qualification. Correct mounting position of component is important during the measurement of cross-axis sensitivity. 7.7 Turn-on time Turn-on time is the time when the last of one X, Y, Z axis output readings stabilizes into its final value after measurement mode has been activated. The final value limits in turn-on time measurements is defined to be ±1 % of the sensor's full scale measuring range (for example for CMR3000-D01 CMR3000-D01 ±1000 dps FS = 1000 dps). Turn-on time definition for Z-axis is presented in Figure 17 below. Angular rate Supply voltage reaches the minimum required level CMR3000 CMR3000 starts CMR3000 CMR3000 output inside ±1% FS limits CMR3000 CMR3000 Z-axis output Time scale Turn on time Figure 17. Turn-on time definition for one axis. VTI Technologies Oy Myllynkivenkuja 6 P.O. Box 27 FI-01621 FI-01621 Vantaa www.vti.fi Doc.Nr. 82112900.A.02 25/ 26 Rev. A.02 CMR3000-D0X CMR3000-D0X Series 8 Document Change Control Version Date Change Description 0.1 0.2 06-Nov-09 18-Nov-09 0.3 20-May-10 0.4 0.5 0.6 A.01 A.02 12-Aug-10 20-Sep-10 26-Oct-10 03-Nov-10 21-Dec-10 Initial draft. Datasheet references updated Section 1.2.5.2 removed, section 2.1, 4.1.4 updated, section 4.2.3 added, Tables 1, 2, 3, 4, 7 updated, Figs 2, 12, 16 updated, PDR-register added, CTRL-register content updated X,Y,Z output register addresses table 2 updated, Fig 14 updated Section 1.2.5.2 added, Figure 2 updated. Figure 8 added °/s changed to dps, Fig 5, Fig 10, Table 5 updated Section 4.1.2.1, Fig 5, section 4.1.4, Table 6 updated VTI Technologies Oy Myllynkivenkuja 6 P.O. Box 27 FI-01621 FI-01621 Vantaa www.vti.fi Doc.Nr. 82112900.A.02 26/ 26 Rev. A.02