CMOS-8L 3 Volt, 0.5-Micron CMOS Gate Array Description: Features: NEC's CMOS-8L

CMOS-8L 3 Volt, 0.5-Micron CMOS Gate Array Description: Features: NEC's CMOS-8L is an optimized true 3-Volt technology, targeted

DATA SHEET CMOS-8L 3 Volt, 0.5-Micron CMOS Gate Array Description: Features: NEC's CMOS-8L is an optimized true 3-Volt technology, targeted for applications requiring extensive integration, low power and high speed. The CMOS-8L ASICs are ideal for use in applications like notebooks or handheld devices, engineering workstations (EWS), graphics, telecom and LAN products. The 28 CMOS-8L masters are available in a wide variety of package types and two or three metallization layers in a sea-ofgates architecture. New library blocks such as PLL (PhaseLocked-Loop), GTL (Gunning Transceiver Logic) and PCI interfaces are available. 5 V signal interfacing is possible with special macros. The CMOS-8L libraries are fully compatible with CMOS-6 and CMOS8 libraries. r True 3 V, 0.5 µm (drawn) CMOS process r Very high speed at 3 V operation r Low power consumption r Ultra-high pin count r 5V Signal interface r Variable output drive (1 to 24 mA) r New library blocks like PLL and GTL r Compiled RAM / ROM r Wide range of package options r Supports scan test methodology Product Outline Master (µPD65.) 2 Layer 840 841 842 843 845 846 848 849 850 851 852 853 855 858 Master (µPD65.) 3 Layer 860 861 862 863 865 866 868 869 870 871 872 873 875 878 Gate Count (raw) 10921 20832 30192 40592 52528 61904 81984 102272 120768 148256 202752 255744 342000 488720 148 188 196 228 260 284 Number of pads Note1 Utilisation (Minimum) Toggle frequency (Min.) Delay time 324 364 396 436 508 572 660 788 65% for 2 metal layers, 80% for 3 metal layers 175 MHz Internal gate 0.13 ns (F/O = 1, l = 0 mm); 0.21 ns (F/O = 2, l = 2 mm) Note2 Input buffer 0.40 ns (F/O = 2, l = 2 mm) 1.67 ns (CL = 15 pF) Output buffer Consumed Internal gate Power Input buffer 1.33 µW/MHz/Cell (3.3 V), 0.8 µW/MHz/Cell (3.0 V) 3.87 µW/MHz/Cell (normal buffer) 0.2 mW/MHz/Cell (CL = 15 pF) Output buffer Power supply voltage 3 V ±10%, 3.3 V ±0.3 V Operating temperature -40 to +85°C Interface level Technology 3 V / 5 V CMOS level, TTL level, GTL, PCI Channelless (Sea-of-Gates) 0.5 µm Silicon gate CMOS, 2 or 3 Al-Metal layers Note 1: Including power supply and GND. Number of pins which can be used for signals depends on package Note 2: 2-input NAND power gate The information in this document is subject to change without notice © NEC Electronics (Europe) GmbH CMOS-8L Design Tool Support CrossCheck® Test Option The low power gate array family CMOS-8L is fully supported by NEC's advanced ASIC design environment OpenCAD® - a unified design package for front-to-back-end. This system allows designers to combine tools from the CAE industry's most popular thirdparty vendors and from NEC's offer of powerful proprietary software tools. The OpenCAD® integration system supports tools for schematic capture, logic synthesis, floorplanning, automatic test pattern generation (ATPG), full timing simulation, accelerated fault-grading and advanced placeand-route algorithms. The company's proprietary clock tree synthesis tool can be used to automatically buffer the clock lines to minimize clock skew. The non-linear delay calculator ensures timing accuracy throughout the simulation, synthesis, and silicon stages.These advanced CAD tools help ensure accurate designs. Additional to CMOS-8L NEC offers the CMOS-8LCX family with CrossCheck® test option. This technology gives full observability and controllability for a minimum of additional silicon area. For further information please refer to the CMOS-8LCX Data Sheet. Electrical Characteristics Absolute Maximum Ratings Parameters Power supply voltage Symbol Conditions Ratings VDD 3 V interface Input/Output voltage VI/VO 5 V interface Output current Operating temperature Storage temperature IO IOL(MIN) = IOL(MIN) = IOL(MIN) = IOL(MIN) = IOL(MIN) = IOL(MIN) = 3.0 mA 6.0 mA 9.0 mA 12.0 mA 18.0 mA 24.0 mA Topt Tstg Unit -0.5 to +4.6 -0.5 to +4.6 VI/O < VDD + 0.5 -0.5 to +6.6 VI/O < VDD + 3.0 V 10 20 30 40 60 80 -40 to +85 -65 to +150 V V V mA mA mA mA mA mA °C °C Input/Output Capacitance (Ta = +25 °C, VDD = 0 V) Parameters Input capacitance Output capacitance I/O capacitance 2 Symbol CIN COUT CI/O Conditions f = 1 MHz Unmeasured pins clamped to 0 V MIN. TYP. MAX. Unit 10 10 10 20 20 20 pF pF pF CMOS-8L Recommended Operating Conditions (3.3 V ±0.3 V, 3.0 V ±10%) Parameters Symbol MIN. MAX. Unit VDD VI Ta VIH VIL VIH VIL VP VN VH tr, ts tr, ts 2.7 0 -40 2.0 0 2.0 0 1.7 0.6 3.6 VDD +85 VDD 0.8 5.5 V 0.8 2.7 1.2 0 0 200 10 V V °C V V V V V V V ns ms Power supply voltage Input voltage Ambient temperature High-level input voltage (3 V) Low-level input voltage (3 V) High-level input voltage (5 V) Low-level input voltage (5 V) Positive Trigger voltage Negative trigger voltage Hysteresis voltage Input rise or fall time Input rise or fall time, Schmitt Note: The rise/fall times given for a Schmitt trigger input buffer vary depending on the operating environment. Simultaneous switching of output buffers should be analyzed carefully. AC Characteristics (Ta = -40 to +85°C) Parameters Symbol Toggle frequency ftog Propagation delay tPD Output rise time tr Output fall time tf Conditions Internal toggle F/F (F/O = 2) Internal gate F/O = 1, l = 0 mm F/O = 2, l = 2 mm Internal gate (Power gate) F/O = 2, l = 2 mm Input buffer F/O = 2, l = 2 mm Output buffer (FO01), CL = 15 pF Output buffer (FO01), CL = 15 pF Output buffer (FO01), CL = 15 pF 3.0 V ±10% MIN. TYP. 175 MAX. 3.3 V ±0.3 V MIN. TYP. 175 MAX. Unit MHz 0.20 0.40 0.18 0.33 ns ns 0.29 0.21 ns 0.40 ns 1.92 1.70 ns 1.95 1.76 ns 1.55 1.39 ns 3 CMOS-8L DC Characteristics (VDD = 3.3 V ±0.3 V, Ta = -40 to +85 °C) Parameters Static current consumption * > 350 k gates (65855, 65875) > 150 k gates (65851, 65871) < 150 k gates Off-state output current Input clamp voltage Output short-circuit current Input leakage current Normal input with pull-up (50 k) with pull-up (5 k) with puII-down (50 k) Pull-Up Resistor (50 k) Pull-Up Resistor (5 k) Pull-Down Resistor (50 k) Low output voltage (3/5 V I/F) High output voltage (CMOS) Symbol Conditions IDDS VI = VDD or GND IOZ VIC IOS VO = VDD or GND II = 18 mA VO = 0 V II II II II RPU RPu RPD VOL VI = VDD or GND VI = GND VI = GND VI = VDD MIN. TYP. MAX. Unit 2 1 0.5 300 300 200 ±2 µA 250 ±10-5 -10 -135 30 45 5.5 27.7 ±10 -40 -350 65 82.5 9.4 50.8 -80 -640 130 300.0 32.1 100.0 0.1 µA V mA µA µA µA µA k k k V IOL = 0 mA IOH = 0 mA (3 V I/F) (5 V I/F) VDD - 0.1 VDD - 0.2 V IOL IOL IOL lOL IOL IOL VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V 3.0 6.0 9.0 12.0 18.0 24.0 mA mA mA mA mA mA IOH lOH IOH IOH IOH IOH VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V -3.0 -6.0 -9.0 -12.0 -18.0 -24.0 mA mA mA mA mA mA lOL lOL lOL lOL lOL lOL VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V 1.0 2.0 3.0 6.0 9.0 12.0 mA mA mA mA mA mA IOH IOH IOH IOH IOH VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V -3.0 -3.0 -3.0 -6.0 -6.0 mA mA mA mA mA VOH Low-level output current (3 V I/F) 3.0 mA 6.0 mA 9.0 mA 12.0 mA 18.0 mA 24.0 mA High-level output current (3 V I/F) 3.0 mA 6.0 mA 9.0 mA 12.0 mA 18.0 mA 24.0 mA Low-level output current (5 V I/F) 1.0 mA 2.0 mA 3.0 mA 6.0 mA 9.0 mA 12.0 mA High-level output current (5 V I/F) 1.0 mA 2.0 mA 3.0 mA 6.0 mA 9.0 mA 4 CMOS-8L DC Characteristics (VDD = 3.0 V ±10%, Ta = -40 to +85 °C) Parameters Symbol Conditions IL MIN. VI = VDD or GND TYP. MAX. Unit 2 1 0.5 300 300 200 ±2 µA Static current consumption * > 350 k gates (65855, 65875) > 150 k gates (65851, 65871) < 150 k gates Off-state output current Input clamp voltage Output short-circuit current Input leakage current Normal input with pull-up (50 k) with pull-up (5 k) with puII-down (50 k) Low output voltage (3/5 V I/F) IOZ VIC IOS VO = VDD or GND II = 18 mA VO = 0 V II II II II VOL High output voltage (CMOS) VOH VI = VDD or GND VI = GND VI = GND VI = VDD IOL = 0 mA IOH = 0 mA (3 V I/F) (5 V I/F) VDD - 0.1 VDD - 0.2 V IOL IOL IOL lOL IOL IOL VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V 3.0 6.0 9.0 12.0 18.0 24.0 mA mA mA mA mA mA IOH lOH IOH IOH IOH IOH VOH = 2.2 V VOH = 2.2 V VOH = 2.2 V VOH = 2.2 V VOH = 2.2 V VOH = 2.2 V -3.0 -6.0 -9.0 -12.0 -18.0 -24.0 mA mA mA mA mA mA lOL lOL lOL lOL lOL lOL VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V 1.0 2.0 3.0 6.0 9.0 12.0 mA mA mA mA mA mA IOH IOH IOH IOH IOH VOH = 2.2 V VOH = 2.2 V VOH = 2.2 V VOH = 2.2 V VOH = 2.2 V -3.0 -3.0 -3.0 -6.0 -6.0 mA mA mA mA mA 250 ±10-5 -45 -0.35 45 -100 -1.0 100 µA V mA ±10 -320 -2.2 320 0.1 µA µA mA µA V Low-level output current (3 V I/F) 3.0 mA 6.0 mA 9.0 mA 12.0 mA 18.0 mA 24.0 mA High-level output current (3 V I/F) 3.0 mA 6.0 mA 9.0 mA 12.0 mA 18.0 mA 24.0 mA Low-level output current (5 V I/F) 1.0 mA 2.0 mA 3.0 mA 6.0 mA 9.0 mA 12.0 mA High-level output current (5 V I/F) 1.0 mA 2.0 mA 3.0 mA 6.0 mA 9.0 mA Note: * The static current consumption increases if an I/O block with on-chip pull-up/down resistor or an oscillator is used. The "+" and "-" signs added to the current values indicate their direction (`+' means current into, `-' means out of the device). 5 CMOS-8L Packaging The benefits of NEC's CMOS-8L family are supported by the right choice of packages. The wide range of packages includes thin packages (T-QFP, L-QFP) and QFP with heat- spreader or Copper-leadframes, to improve the thermal characteristics. New packages like PGA or BGA (Ball Grid Array) with high pin count are continuously under development. Package Availability Master (µPD65.) Package 100 QFP (FP) 120 QFP (FP) 144 QFP (FP) 160 QFP (FP) 176 QFP (FP) 208 QFP (FP) 240 QFP (FP) 272 QFP (FP) 304 QFP (FP) Pitch 840 [mm] 860 841 861 842 862 843 863 845 865 846 866 848 868 849 869 850 870 851 871 852 872 853 873 855 875 858 878 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 A - A A - A A A - A A P A A - A A A A A P - A A A A A P - A A P P A P A A P A A P A A A P P A P P A P A P P A A A A P A A A P A A A P A P P P P 256 QFP (FP) 0.40 - - - - A A P P P P P P P P 160 QFP-Hsp 160 QFP-Hsp 176 QFP-Hsp 208 QFP-Hsp 0.65 0.50 0.50 0.50 - - - - - A - A P - A P - P P A A A P A A A A A P 100 T-QFP 144 T-QFP 160 T-QFP 176 T-QFP 208 T-QFP 0.50 0.50 0.50 0.50 0.50 - P - P - - - - - - - - - - - - 144 L-QFP 160 L-QFP 208 L-QFP 0.50 0.50 0.50 P - P - P P P P P P P P P P P P P P P P P P P P P P P 72 PGA 132 PGA 176 PGA 208 PGA 280 PGA 364 PGA 528 PGA - A - A - A - - A - A - A A - A A - A A - A A - P A A P A A P A P 288 B/L PGA 528 B/L PGA - - - - - - - - - - - A A P Note: 6 FP T L Hsp B/L A P = Fine Pitch = Thin package (1 mm thick) = Low profile package (1.4 mm thick), = with integrated Heat Spreader = Butt Lead (surface mount PGA) = available master package combination = master package combination under development or planned; availability must be confirmed by NEC CMOS-8L Block Library The functions of the CMOS-8L blocks are designed to be compatible with those of the CMOS-6 and CMOS-8 family. The CMOS-8L family offers a wide variety of advanced blocks, including combination gates, shift registers, adders and counters. In addition, memory blocks such as RAM and ROM will be provided, and low-power gates are available. The low-power blocks are designed for gate count reduction; the number of cells are fewer than that of the standard block, contributing to lower power consumption and higher efficiency. The signal interface to 5 V logic is supported by special I/O macro blocks. I/O Buffer Buffer Type Input Buffer Options and possible combinations Pull-Up 50 k, 5 k / Pull-Down 50 k / Schmitt Trigger Input/ Fail Safe/ High Fanout (Clock Driver) / PCI (3 V / 5 V) / GTL / TTL Output Buffer, Bidirectional I/O Buffer Drive Ability: 3, 6, 9, 12, 18, 24 mA (3 V) / 1, 2, 3, 6, 9 mA (5 V) / TTL / Open Drain / Tri-State / Low Noise (Slew rate) / PCI (3 V / 5 V) / GTL Memory Blocks Type (Function) High density single port RAM High speed single port RAM High speed dual port RAM Standard ROM Operation Bit range Word range Asynchronous Asynchronous Asynchronous Asynchronous 4 to 40 2 to 128 2 to 128 4 to 32 128 to 4k 4 to 1k 4 to 1k 128 to 8k Block List Block Name Description Interface Blocks F091 H,L level generator F093 Interface block for Oscillator buffer Clock Drivers FCK1 Clock Driver (F/O = 279) FCK2 Clock Driver (F/O = 565) FCK3 Clock Driver (F/O = 864) FCK4 Clock Driver (F/O = 1344) FCK5 Clock Driver (F/O = 1440) Inverters F101 F102 F103 F104 F108 Inverter Inverter Inverter Inverter Inverter Block Name Description Buffers F111 F112 F113 F114 F118 Non-Inverting Buffer (F/O = 10) Non-Inverting Buffer (F/O = 20) Non-Inverting Buffer (F/O = 30) Non-Inverting Buffer (F/O = 40) Non-Inverting Buffer (F/O = 80) Three-State Buffers F531 3-state Buffer with EN F532 3-state Buffer with ENB Delays F130 F131 F132 Delay Gate Delay Gate Delay Gate 7 CMOS-8L Block Name Description NOR Gates F202 2-Input NOR F203 3-Input NOR F204 4-Input NOR F205 5-Input NOR F206 6-Input NOR F208 8-Input NOR F222 2-Input NOR (Power) F223 3-Input NOR (Power) F224 4-Input NOR (Power) OR Gates F212 F213 F214 F215 F216 F232 F233 F234 2-Input OR 3-Input OR 4-Input OR 5-Input OR 6-Input OR 2-Input OR (Power) 3-Input OR (Power) 4-Input OR (Power) NAND Gates F302 2-Input NAND F303 3-Input NAND F304 4-Input NAND F305 5-Input NAND F306 6-Input NAND F308 8-Input NAND F322 2-Input NAND (Power) F323 3-Input NAND (Power) F324 4-Input NAND (Power) AND Gates F312 2-Input AND F313 3-Input AND F314 4-Input AND F315 5-Input AND F316 6-Input AND F332 2-Input AND (Power) F333 3-Input AND (Power) F334 4-Input AND (Power) AND-OR Gates F421 2-Wide, 1-2-input AND-OR-Inverter F422 3-Wide, 1-1-2-input AND-OR-Inverter F423 2-Wide, 1-3-input AND-OR-Inverter F424 2-Wide, 2-2-input AND-OR-Inverter F425 3-Wide, 2-2-2-Input AND-OR-Inverter F426 2-Wide, 3-3-Input AND-OR-Inverter F429 4-Wide, 2-2-2-2-Input AND-OR-Inverter F442 2-Wide, 4-4-Input AND-OR-Inverter F462 3-Wide, 1-2-3-Input AND-OR-Inverter OR-AND Gates F431 2-Wide, 1-2-Input OR-AND-Inverter F432 3-Wide, 1-1-2-Input OR-AND-Inverter F433 2-Wide, 1-3-Input OR-AND-Inverter F434 2-Wide, 2-2-Input OR-AND-Inverter F435 2-Wide, 2-3-Input OR-AND-Inverter F436 2-Wide, 3-3-Input OR-AND-Inverter F454 4-Wide, 2-2-2-2-Input OR-AND-Inverter 8 Block Name Description Exclusive OR Functions F511 Exclusive-OR F512 Exclusive-NOR Adders F521 F523 F526 F527 1-bit Full Adder 4-bit Binary Full Adder Look Ahead Carry Generator 4-bit Full Adder Decoders F561 2 to 4 Decoder F981 2 to 4 Decoder with ENB F982 3 to 8 Decoder with ENB Multiplexers F563 Non-inverting 8 to 1 Multiplexer F564 Non-inverting 4 to 1 Multiplexer F565 Non-inverting 2 to 1 Multiplexer F569 8 to 1 Multiplexer with ENB F570 4 to 1 Multiplexer with ENB F571 2 to 1 Multiplexer with ENB F572 Quad 2 to 1 Multiplexer Parity Generators F581 8-bit Odd Parity Generator F582 8-bit Even Parity Generator Latches F595 F601 F602 F603 F604 F605 F901 F902 RS-Latch D-Latch D-Latch with R D-Latch with RB D-Latch GB D-Latch GB with RB 4-bit Latch 8-bit Latch Flip-Flops F596 F611 F614 F615 F616 F617 F631 F637 F641 F644 F647 F661 F667 F714 F717 Synchronous RS-F/F with Set, Reset D-F/F D-F/F with S, R D-F/F with RB D-F/F with SB D-F/F with SB, RB D-F/F CB D-F/F CB with SB, RB D-F/F (Buffered Out) D-F/F with S, R (Buffered Out) D-F/F with SB, RB (Buffered Out) D-F/F CB (Buffered Out) D-F/F CB SB, RB (Buffered Out) T-F/F with S, R T-F/F with SB, RB CMOS-8L Block Name Description Flip-Flops (Cont.) F737 T-F/F TB with SB, RB F744 T-F/F with S, R (Buffered Out) F747 T-F/F with SB, RB (Buffered Out) F767 T-F/F TB with SB, RB (Buffered Out) F771 JK-F/F (Buffered Out) F774 JK-F/F with S, R (Buffered Out) F777 JK-F/F with SB, RB (Buffered Out) F781 JK-F/F CB (Buffered Out) F787 JK-F/F CB with SB, RB (Buffered Out) F791 T-F/F with S, R, TE F792 T-F/F TB with SB, RB, TEB F922 4-bit D-F/F with R F924 4-bit D-F/F Shift Registers F911 4-bit Shift Register with R F912 4-bit Serial/Parallel Shift Register F913 4-bit Parallel in Shift Register with RB F914 4-bit Shift Register F915 4-bit Shift Register with direct LOADB (Buffered Out) Counters F961 4-bit Sync. Binary Counter with RB (Buffered Out) F962 4-bit Synchronous Binary Up-Counter with RB F963 Presetable Synchronous Up/Down Binary Counter (Dual clock, with Clear) F964 Presetable Synchronous Up/Down Binary Counter Comparator F985 4-bit Magnitude Comparator Function Blocks - Low Power Inverter L101 Inverter (F/O = 10) Buffer L111 Non-Inverting Buffer (F/O = 10) NOR Gates L202 2-Input NOR L203 3-Input NOR L204 4-Input NOR OR Gates L212 2-Input OR L213 3-Input OR L214 4-Input OR NAND Gates L302 2-Input NAND L303 3-Input NAND L304 4-Input NAND L305 5-Input NAND L306 6-Input NAND Block Name Description AND-OR Gates L421 2-Wide, 1-2-input AND-OR-Inverter L422 3-Wide, 1-1-2-input AND-OR-Inverter L423 2-Wide, 1-3-input AND-OR-Inverter L424 2-Wide, 2-2-input AND-OR-Inverter L425 3-Wide, 2-2-2-Input AND-OR-Inverter L426 2-Wide, 3-3-Input AND-OR-Inverter L429 4-Wide, 2-2-2-2-Input AND-OR-Inverter L442 2-Wide, 4-4-Input AND-OR-Inverter L462 3-Wide, 1-2-3-Input AND-OR-Inverter OR-AND Gates L431 2-Wide, 1-2-Input OR-AND-Inverter L432 3-Wide, 1-1-2-Input OR-AND-Inverter L433 2-Wide, 1-3-Input OR-AND-Inverter L434 2-Wide, 2-2-Input OR-AND-Inverter L435 2-Wide, 2-3-Input OR-AND-Inverter L436 2-Wide, 3-3-Input OR-AND-Inverter L454 4-Wide, 2-2-2-2-Input OR-AND-Inverter Exclusive OR Functions L511 Exclusive-OR L512 Exclusive-NOR Decoders L561 2 to 4 Decoder L981 2 to 4 Decoder with ENB L982 3 to 8 Decoder with ENB Multiplexers L571 2 to 1 Multiplexer with ENB L572 Quad 2 to 1 Multiplexer Latches L601 L602 L603 L604 L605 L901 L902 D-Latch D-Latch with R D-Latch with RB D-Latch GB D-Latch GB with RB 4-bit Latch 8-bit Latch Flip-Flops L611 L614 L617 L631 L637 L714 L717 L737 L922 L924 D-F/F D-F/F with S, R D-F/F with SB, RB D-F/F CB D-F/F CB with SB, RB T-F/F with S, R T-F/F with SB, RB T-F/F TB with SB, RB 4-bit D-F/F with R 4-bit D-F/F Shift Registers L911 4-bit Shift Register with R L912 4-bit Serial/Parallel Shift Register L913 4-bit Parallel in Shift Register with RB L914 4-bit Shift Register AND Gates L312 2-Input AND L313 3-Input AND L314 4-Input AND 9 CMOS-8L Block Name Description Scan Path Blocks Flip-Flops S000 S002 S050 S052 S100 S102 S150 S152 D-F/F with S, R (Scan Path) D-F/F (Scan Path) D-F/F with S, R, H (Scan Path) D-F/F with H (Scan Path) JK-F/F with S, R (Scan Path) JK-F/F (Scan Path) JK-F/F with S, R, H (Scan Path) JK-F/F with H (Scan Path) Latches S201 S202 S301 S302 D-Latch with R (Scan Path) D-Latch (Scan Path) D-Latch with R (ATG) D-Latch (ATG) Multiplexer S999 2 to 1 Data Selector (Scan Path) Further Publications This data sheet contains a reduced set of information and operational data for the CMOS-8 gate array family. Additional information is available in NEC's CMOS-8 Design Manual and CMOS-8 Block Library. Please contact your local NEC Design Centre for further informations. 10 CMOS-8L Notes: 11