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CLK48

Catalog Datasheet MFG & Type PDF Document Tags

CLK48

Abstract: only those FFs clocked by CLK48 USB DEMO ­ 6 Defining Fast Setup for CLK48 Input 15 ns input delay (setup) constraint now applied to CLK48 input pin USB DEMO ­ 7 FPGA Express Writes
Xilinx
Original

LAD1 5V

Abstract: LAD1 12v CLOCK Lines Layout/Routing Guidelines.(Pin2:CLK48 & Pin11:LCLK) 1)If possible, please avoid using any , remove the pull-up resistor of pin18 GPIO12/LDRQ#. VCC RXD1 TO ICH VCC CLK48 V33 PCIRST# LAD0 LAD1 LAD2 LAD3 LFRAME# V33 PCICLK SERIRQ CLK48 V33 1 2 3 4 5 6 7 8 9 10 11 , /FSIDE1# GPIO21/FINDEX# GND VCC CLK48 V33 LRESET# LAD0 LAD1 LAD2 LAD3 LFRAME# V33 LCLK
-
Original
IT8761E IT8701F LAD1 5V LAD1 12v IN4001 GPIO20 GPIO-12 ITSA-CG-99602 GPIO26/FDIR GPIO25/FSTEP GPIO24/FWDATA

HC49U

Abstract: TPS2041 ) EXTMEM V CC DP0PUR GND XTAL2 XTAL1/CLK48 SUSPND MODE VF PACKAGE (TOP VIEW) 32 , OFFICE BOX 655303 · DALLAS, TEXAS 75265 SUSPND XTAL1/CLK48 29 26 SIE Interface Logic , MODE is high, the clock on XTAL1/CLK48 is selected as the clock source and 48-MHz oscillator or other , 3, 25 NAME PWRON1 ­ PWRON3 VF 3.3-V supply voltage XTAL1/CLK48 30 I Crystal 1/48-MHz Clock Input. When MODE is low, XTAL1/CLK48 is a 6-MHz crystal input with 50% duty cycle. An
Texas Instruments
Original
TUSB2036 HC49U TPS2041 TPS2044 TUSB2077A TUSB2140B SLLS372 XTAL1/CLK48

CLK48

Abstract: Flat Pack) D D D D D D VF PACKAGE (TOP VIEW) XTAL1/CLK48 EXTMEM SUSPND MODE DP0PUR , XTAL1/CLK48 XTAL2 MODE RESET EXTMEM SIE Interface Logic 6 Serial EEPROM Interface 5 EEDATA , XTAL1/CLK48 is selected as the clock source and 48-MHz oscillator or other on-board clock source can be , (see Table 1) 3.3-V supply voltage I Crystal 1/48-MHz Clock Input. When MODE is low, XTAL1/CLK48 is a 6 , by the ASIC logic. When MODE is high, XTAL1/CLK48 acts as the input of the 48 MHz clock and the
Texas Instruments
Original

CRC-16 and verilog

Abstract: CLK48 PORT INTERFACE Clk12 Clk48 Test_PLLCLK Figure 2: Logic Symbol for USB 1.1 Host Controller 8
OKI Electric Industry
Original
Z0122 Z0100 CRC-16 and verilog
Abstract: Pack) D D D D D D VF PACKAGE (TOP VIEW) XTAL1/CLK48 EXTMEM SUSPND MODE DP0PUR , SIE M 1 U X 0 30 OSC/PLL 29 31 4 26 XTAL1/CLK48 XTAL2 MODE RESET EXTMEM SIE Interface , or oscillator can be used. When MODE is high, the clock on XTAL1/CLK48 is selected as the clock , I Crystal 1/48-MHz clock input. When MODE is low, XTAL1/CLK48 is a 6-MHz crystal input with 50% duty , MODE is high, XTAL1/CLK48 acts as the input of the 48-MHz clock and the internal APLL logic is bypassed Texas Instruments
Original
SLLS372C 48-MH

HC49U

Abstract: M93C46 XTAL2 XTAL1/CLK48 SUSPND MODE VF PACKAGE (TOP VIEW) 32 31 30 29 28 27 26 25 DP0 DM0 , 655303 · DALLAS, TEXAS 75265 SUSPND XTAL1/CLK48 29 26 SIE Interface Logic DP0PUR , MODE is high, the clock on XTAL1/CLK48 is selected as the clock source and 48-MHz oscillator or other , 3, 25 3.3-V supply voltage XTAL1/CLK48 30 I Crystal 1/48-MHz clock input. When MODE is low, XTAL1/CLK48 is a 6-MHz crystal input with 50% duty cycle. An internal APLL generates the 48
Texas Instruments
Original
M93C46

TUSB2140B

Abstract: amplifier with port USB diagram S-PQFP-G For Low-Profile Quad Flat Pack) EXTMEM V CC DP0PUR GND XTAL2 XTAL1/CLK48 , 655303 · DALLAS, TEXAS 75265 SUSPND XTAL1/CLK48 29 26 SIE Interface Logic DP0PUR , oscillator can be used. When MODE is high, the clock on XTAL1/CLK48 is selected as the clock source and 48 , Table 1) VCC 3, 25 NAME PWRON1 - PWRON3 VF 3.3-V supply voltage XTAL1/CLK48 30 I Crystal 1/48-MHz clock input. When MODE is low, XTAL1/CLK48 is a 6-MHz crystal input with 50
Texas Instruments
Original
SLLS372A amplifier with port USB diagram 33 pf capacitor

m93c46

Abstract: tusb2036vfg4 XTAL2 XTAL1/CLK48 SUSPND MODE VF PACKAGE (TOP VIEW) 32 31 30 29 28 27 26 25 DP0 DM0 , 655303 · DALLAS, TEXAS 75265 SUSPND XTAL1/CLK48 29 26 SIE Interface Logic DP0PUR , MODE is high, the clock on XTAL1/CLK48 is selected as the clock source and 48-MHz oscillator or other , 3, 25 3.3-V supply voltage XTAL1/CLK48 30 I Crystal 1/48-MHz clock input. When MODE is low, XTAL1/CLK48 is a 6-MHz crystal input with 50% duty cycle. An internal APLL generates the 48
Texas Instruments
Original
tusb2036vfg4
Abstract: Low-Profile Quad Flat Pack) VF PACKAGE (TOP VIEW) XTAL1/CLK48 EXTMEM SUSPND MODE DP0PUR XTAL2 , XTAL1/CLK48 XTAL2 MODE RESET EXTMEM SIE Interface Logic 6 Serial EEPROM Interface 5 EEDATA , XTAL1/CLK48 is selected as the clock source and 48-MHz oscillator or other on-board clock source can be , (see Table 1) 3.3-V supply voltage I Crystal 1/48-MHz Clock Input. When MODE is low, XTAL1/CLK48 is a 6 , by the ASIC logic. When MODE is high, XTAL1/CLK48 acts as the input of the 48 MHz clock and the Texas Instruments
Original
SGLB002 SGYC003B TUSB2036VF TUSB2036VFR

b 57828

Abstract: 8259 Interrupt Controller DPLS2 VSST VDDT DMNS1 DPLS1 DMNS0 DPLS0 VSST VDDT RREF VDDA XHI XLO/CLK48 VSSA CLK48STOP , PRTPWR0 PWRFLT0N PRTPWR1 PWRFLT1N VDD CLK48STOP VSSA XLO/CLK48 XHI VDDA RREF VDDT VSST DPLS0 , Symbol* Type 77 79 102 104 75 81 PWRFLT0N PWRFLT1N PWRFLT2N PWRFLT3N CLK48 CLK48STOP , CLK48 48 MHz OSC PRTPWR0 PWRFLT0N CLK48STOP 5 Vdc-5 Vdc SWITCHED REGULATOR VBUS = 5 Vdc , ROOT HUB AND HOST SIE RX DPLL LEGACY SUPPORT POWER MNGMNT LOGIC CLK48STOP PMEN
Agere Systems
Original
USS-344 b 57828 8259 Interrupt Controller AD27 30L-15P-BA PB01-114CMPR-2 PB01-114CMPR-1

TUSB2036

Abstract: Low-Profile Quad Flat Pack) VF PACKAGE (TOP VIEW) XTAL1/CLK48 EXTMEM SUSPND MODE DP0PUR XTAL2 , XTAL1/CLK48 XTAL2 MODE RESET EXTMEM SIE Interface Logic 6 Serial EEPROM Interface 5 EEDATA , XTAL1/CLK48 is selected as the clock source and 48-MHz oscillator or other on-board clock source can be , (see Table 1) 3.3-V supply voltage I Crystal 1/48-MHz Clock Input. When MODE is low, XTAL1/CLK48 is a 6 , by the ASIC logic. When MODE is high, XTAL1/CLK48 acts as the input of the 48 MHz clock and the
Texas Instruments
Original
SLLA107 RS-485 SLLA112

CLK48

Abstract: Pack) D D D D D D VF PACKAGE (TOP VIEW) XTAL1/CLK48 EXTMEM SUSPND MODE DP0PUR , SIE M 1 U X 0 30 OSC/PLL 29 31 4 26 XTAL1/CLK48 XTAL2 MODE RESET EXTMEM SIE Interface , or oscillator can be used. When MODE is high, the clock on XTAL1/CLK48 is selected as the clock , I Crystal 1/48-MHz clock input. When MODE is low, XTAL1/CLK48 is a 6-MHz crystal input with 50% duty , MODE is high, XTAL1/CLK48 acts as the input of the 48-MHz clock and the internal APLL logic is bypassed
Texas Instruments
Original
Abstract: Flat Pack) VF PACKAGE (TOP VIEW) XTAL1/CLK48 EXTMEM SUSPND MODE DP0PUR 32 31 3029 2827 , XTAL1/CLK48 XTAL2 MODE RESET EXTMEM SIE Interface Logic 6 Serial EEPROM Interface 5 EEDATA , . When MODE is high, the clock on XTAL1/CLK48 is selected as the clock source and 48-MHz oscillator or , TERMINAL FUNCTIONS (continued) TERMINAL NAME VCC XTAL1/CLK48 XTAL2 NO. 3, 25 30 29 I O I/O DESCRIPTION 3.3-V supply voltage Crystal 1/48-MHz clock input. When MODE is low, XTAL1/CLK48 is a 6-MHz crystal input with Texas Instruments
Original
SLLS372F ISO/TS16949

USB TRANSCEIVER

Abstract: Low-Profile Quad Flat Pack) VF PACKAGE (TOP VIEW) XTAL1/CLK48 EXTMEM SUSPND MODE GND 32 31 , /Resume Logic and Frame Timer SIE M 1 U X 0 30 OSC/PLL 29 31 4 26 XTAL1/CLK48 XTAL2 MODE RESET , XTAL1/CLK48 is selected as the clock source and 48-MHz oscillator or other on-board clock source can be , XTAL1/CLK48 XTAL2 NO. 3, 25 30 29 I O I/O DESCRIPTION 3.3-V supply voltage Crystal 1/48-MHz clock input. When MODE is low, XTAL1/CLK48 is a 6-MHz crystal input with 50% duty cycle. An internal APLL generates
Texas Instruments
Original
USB TRANSCEIVER SLLS372E
Abstract: ) XTAL1/CLK48 EXTMEM SUSPND MODE DP0PUR XTAL2 GND 32 31 30 29 28 27 26 25 DP0 DM0 VCC , /CLK48 XTAL2 MODE RESET EXTMEM SIE Interface Logic 6 Serial EEPROM Interface 5 EEDATA/GANGED , or oscillator can be used. When MODE is high, the clock on XTAL1/CLK48 is selected as the clock , I Crystal 1/48-MHz clock input. When MODE is low, XTAL1/CLK48 is a 6-MHz crystal input with 50% duty , MODE is high, XTAL1/CLK48 acts as the input of the 48-MHz clock and the internal APLL logic is bypassed Texas Instruments
Original
SLLS372B

8259 Interrupt Controller

Abstract: CLK48 VDDT RREF VDDA XHI XLO/CLK48 VSSA CLK48STOP VDD PWRFLT1N PRTPWR1 PWRFLT0N PRTPWR0 SMIN VSS VDD IRQ12 , PWRFLT3N CLK48 CLK48STOP VDDT VSST RREF VDDA VSSA XHI XLO/CLK48 Type Input Input Input Input Input Output , designer if not desired. 3.3 Vdc CLK48 CLK48STOP 5 Vdc 48 MHz OSC PRTPWR0 PWRFLT0N 5 Vdc-5 Vdc , PROCESSOR BLOCK HSIE S/M FIFO DPLL RX MIRQ121 KIRQ1I A20I IRQ1 IRQ12 A20MN SMIN CLK48STOP PMEN LEGACY , MIRQ12I KIRQ1I A20I A20MN IRQ1 IRQ12 VDD VSS SMIN PRTPWR0 PWRFLT0N PRTPWR1 PWRFLT1N VDD CLK48STOP VSSA XLO
Agere Systems
Original
PB-0111

CLK48

Abstract: Pack) D D D D D D VF PACKAGE (TOP VIEW) XTAL1/CLK48 EXTMEM SUSPND MODE DP0PUR , SIE M 1 U X 0 30 OSC/PLL 29 31 4 26 XTAL1/CLK48 XTAL2 MODE RESET EXTMEM SIE Interface , or oscillator can be used. When MODE is high, the clock on XTAL1/CLK48 is selected as the clock , I Crystal 1/48-MHz clock input. When MODE is low, XTAL1/CLK48 is a 6-MHz crystal input with 50% duty , MODE is high, XTAL1/CLK48 acts as the input of the 48-MHz clock and the internal APLL logic is bypassed
Texas Instruments
Original

TUSB2036

Abstract: tusb2036vfg4 S-PQFP-G For Low-Profile Quad Flat Pack) EXTMEM V CC DP0PUR GND XTAL2 XTAL1/CLK48 , DALLAS, TEXAS 75265 SUSPND XTAL1/CLK48 29 26 SIE Interface Logic DP0PUR XTAL2 MODE , device and 6-MHz crystal or oscillator can be used. When MODE is high, the clock on XTAL1/CLK48 is , XTAL1/CLK48 30 I Crystal 1/48-MHz clock input. When MODE is low, XTAL1/CLK48 is a 6-MHz crystal , the ASIC logic. When MODE is high, XTAL1/CLK48 acts as the input of the 48-MHz clock and the internal
Texas Instruments
Original
Abstract: XTAL1/CLK48 XTAL2 3 22 4 21 5 20 6 19 7 18 17 8 NP3 NPINT1 , DP0PUR SUSPND XTAL1/CLK48 XTAL2 MODE RESET EXTMEM EEDATA/GANGED EECLK NP3 NPINT(1- 0 , -MHz crystal or oscillator can be used. When MODE is high, the clock on XTAL1/CLK48 is selected as the clock , DESCRIPTION 3.3-V supply voltage XTAL1/CLK48 30 I Crystal 1/48-MHz clock input. When MODE is low, XTAL1/CLK48 is a 6-MHz crystal input with 50% duty cycle. An internal APLL generates the 48-MHz and 12 Texas Instruments
Original

SLLS372E

Abstract: Low-Profile Quad Flat Pack) VF PACKAGE (TOP VIEW) XTAL1/CLK48 EXTMEM SUSPND MODE GND 32 31 , /Resume Logic and Frame Timer SIE M 1 U X 0 30 OSC/PLL 29 31 4 26 XTAL1/CLK48 XTAL2 MODE RESET , XTAL1/CLK48 is selected as the clock source and 48-MHz oscillator or other on-board clock source can be , XTAL1/CLK48 XTAL2 NO. 3, 25 30 29 I O I/O DESCRIPTION 3.3-V supply voltage Crystal 1/48-MHz clock input. When MODE is low, XTAL1/CLK48 is a 6-MHz crystal input with 50% duty cycle. An internal APLL generates
Texas Instruments
Original
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