NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: only those FFs clocked by CLK48 USB DEMO 6 Defining Fast Setup for CLK48 Input 15 ns input delay (setup) constraint now applied to CLK48 input pin USB DEMO 7 FPGA Express Writes ... | Original |
8 pages, |
CLK48 datasheet abstract |
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| Abstract: Lines Layout/Routing Guidelines.(Pin2:CLK48 & Pin11:LCLK) 1)If possible, please avoid using any , remove the pull-up resistor of pin18 GPIO12/LDRQ GPIO12/LDRQ#. VCC RXD1 TO ICH VCC CLK48 V33 PCIRST# LAD0 LAD1 LAD2 LAD3 LFRAME# V33 PCICLK SERIRQ CLK48 V33 1 2 3 4 5 6 7 8 9 10 11 , GPIO22/FSIDE1 GPIO22/FSIDE1# GPIO21/FINDEX GPIO21/FINDEX# GND VCC CLK48 V33 LRESET# LAD0 LAD1 LAD2 LAD3 LFRAME# V33 ... | Original |
2 pages, |
A20M CLK48 JP15 GPIO-12 GPIO14 IT8701F IT8761E LAD1 5V IN4001 LAD1 12v datasheet abstract |
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| Abstract: DPLS2 VSST VDDT DMNS1 DPLS1 DMNS0 DPLS0 VSST VDDT RREF VDDA XHI XLO/CLK48 VSSA CLK48STOP , PRTPWR0 PWRFLT0N PRTPWR1 PWRFLT1N VDD CLK48STOP VSSA XLO/CLK48 XHI VDDA RREF VDDT VSST DPLS0 , * Type 77 79 102 104 75 81 PWRFLT0N PWRFLT1N PWRFLT2N PWRFLT3N CLK48 CLK48STOP Input , CLK48 48 MHz OSC PRTPWR0 PWRFLT0N CLK48STOP 5 Vdc-5 Vdc SWITCHED REGULATOR VBUS = 5 Vdc , HUB AND HOST SIE RX DPLL LEGACY SUPPORT POWER MNGMNT LOGIC CLK48STOP PMEN ... | Original |
8 pages, |
USS-344 AD27 8259 Interrupt Controller USS-344 abstract |
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| Abstract: ) EXTMEM V CC DP0PUR GND XTAL2 XTAL1/CLK48 SUSPND MODE VF PACKAGE (TOP VIEW) 32 , OFFICE BOX 655303 · DALLAS, TEXAS 75265 SUSPND XTAL1/CLK48 29 26 SIE Interface Logic , MODE is high, the clock on XTAL1/CLK48 is selected as the clock source and 48-MHz oscillator or other , 3, 25 NAME PWRON1 PWRON3 VF 3.3-V supply voltage XTAL1/CLK48 30 I Crystal 1/48-MHz Clock Input. When MODE is low, XTAL1/CLK48 is a 6-MHz crystal input with 50% duty cycle. An ... | Original |
20 pages, |
TUSB2140B TUSB2077A TUSB2036 TPS2044 TPS2041 m93c46 HC49U SLLS372 TUSB2036 abstract |
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| Abstract: For Low-Profile Quad Flat Pack) EXTMEM V CC DP0PUR GND XTAL2 XTAL1/CLK48 SUSPND , 655303 · DALLAS, TEXAS 75265 SUSPND XTAL1/CLK48 29 26 SIE Interface Logic DP0PUR , oscillator can be used. When MODE is high, the clock on XTAL1/CLK48 is selected as the clock source and , /CLK48 30 I Crystal 1/48-MHz clock input. When MODE is low, XTAL1/CLK48 is a 6-MHz crystal input , ASIC logic. When MODE is high, XTAL1/CLK48 acts as the input of the 48-MHz clock and the internal APLL ... | Original |
21 pages, |
TUSB2140B TUSB2077A TUSB2036 TPS2044 TPS2041 SLLS372A M93C46 HC49U amplifier with port USB diagram TUSB2036 abstract |
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| Abstract: PORT INTERFACE Clk12 Clk48 Test_PLLCLK Figure 2: Logic Symbol for USB 1.1 Host Controller 8 ... | Original |
48 pages, |
Z0122 Z0100 Z0122 abstract |
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| Abstract: XTAL2 XTAL1/CLK48 SUSPND MODE VF PACKAGE (TOP VIEW) 32 31 30 29 28 27 26 25 DP0 DM0 , 655303 · DALLAS, TEXAS 75265 SUSPND XTAL1/CLK48 29 26 SIE Interface Logic DP0PUR , XTAL1/CLK48 is selected as the clock source and 48-MHz oscillator or other on-board clock source can be , supply voltage XTAL1/CLK48 30 I Crystal 1/48-MHz clock input. When MODE is low, XTAL1/CLK48 , clocks used internally by the ASIC logic. When MODE is high, XTAL1/CLK48 acts as the input of the 48-MHz ... | Original |
23 pages, |
TUSB2140B TUSB2077A TUSB2036 TPS2044 SLLS372C M93C46 HC49U TUSB2036 abstract |
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| Abstract: For Low-Profile Quad Flat Pack) EXTMEM V CC DP0PUR GND XTAL2 XTAL1/CLK48 SUSPND , DALLAS, TEXAS 75265 SUSPND XTAL1/CLK48 29 26 SIE Interface Logic DP0PUR XTAL2 MODE , or oscillator can be used. When MODE is high, the clock on XTAL1/CLK48 is selected as the clock , permanently attached (see Table 1) VCC 3, 25 3.3-V supply voltage XTAL1/CLK48 30 I Crystal 1/48-MHz clock input. When MODE is low, XTAL1/CLK48 is a 6-MHz crystal input with 50% duty cycle. ... | Original |
21 pages, |
TUSB2140B TUSB2077A TUSB2036 TPS2044 TPS2041 M93C46 HC49U tusb2036vfg4 SLLS372B TUSB2036 abstract |
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| Abstract: XTAL2 XTAL1/CLK48 SUSPND MODE VF PACKAGE (TOP VIEW) 32 31 30 29 28 27 26 25 DP0 DM0 , 655303 · DALLAS, TEXAS 75265 SUSPND XTAL1/CLK48 29 26 SIE Interface Logic DP0PUR , XTAL1/CLK48 is selected as the clock source and 48-MHz oscillator or other on-board clock source can be , supply voltage XTAL1/CLK48 30 I Crystal 1/48-MHz clock input. When MODE is low, XTAL1/CLK48 , clocks used internally by the ASIC logic. When MODE is high, XTAL1/CLK48 acts as the input of the 48-MHz ... | Original |
23 pages, |
TUSB2140B TUSB2077A TUSB2036 TPS2044 HC49U tusb2036vfg4 SLLS372C m93c46 TUSB2036 abstract |
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| Abstract: (JEDEC - S-PQFP-G For Low-Profile Quad Flat Pack) VF PACKAGE (TOP VIEW) XTAL1/CLK48 EXTMEM , /Resume Logic and Frame Timer SIE M 1 U X 0 30 OSC/PLL 29 31 4 26 XTAL1/CLK48 XTAL2 MODE RESET , /CLK48 is selected as the clock source and 48-MHz oscillator or other on-board clock source can be used. , XTAL1/CLK48 XTAL2 NO. 3, 25 30 29 I O I/O DESCRIPTION 3.3-V supply voltage Crystal 1/48-MHz clock input. When MODE is low, XTAL1/CLK48 is a 6-MHz crystal input with 50% duty cycle. An internal APLL generates ... | Original |
20 pages, |
TUSB2036 SLLS372E TUSB2036 abstract |
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| Abstract: D A T A A C Q U I S I T I O N 8-Bit, 20 MSPS ADC with industry standard pinout The TLC5510 TLC5510 is an 8-bit, 20 MSPS ADC in the industry standard pinout that combines video speed, low power and high accuracy. Implemented with a multi-stage, semi-flash architecture the TLC5510 TLC5510 provides significantly lower power consumption and cost than traditional flash architectures, while maintaining conversion rates of 20 MSPS and Differential Non Linearity (DNL) accuracy of �5 LSB. The TLC5510 TLC5510 is ... | Original |
1 pages, |
TLC5510 HI1175 cxd1175 "pin compatible" CXD1175 CXD1175 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| Defining Fast Setup for CLK48 Input www.datasheetarchive.com/files/xilinx/spring97/usb_demo/sld007.htm |
Xilinx | 21/04/1997 | 0.97 Kb | HTM | sld007.htm |
| Setup for CLK48 Input FPGA Express Writes Constraints Into Design Netlist www.datasheetarchive.com/files/xilinx/spring97/usb_demo/index.htm |
Xilinx | 21/04/1997 | 1.02 Kb | HTM | index.htm |
| 1181-WR 1181-WR 1181-WR 1181-WR# ISP1181-RD ISP1181-RD ISP1181-RD ISP1181-RD# CLK-48M OE1 GND4 CLOCK 5 VCC 8 Y1 48MHz R8 0R VCC C12 0.1uF CLK-48M CP LD -V CC 1 www.datasheetarchive.com/download/93942534-622091ZC/isp1181pc_schematic.zip (ISP1181PC_Schematic.pdf) |
Philips | 11/03/2004 | 68.81 Kb | ZIP | isp1181pc_schematic.zip |
| AD17 C4 CLK48 L3 GPI21 GPI21 GPI21 GPI21 G3 LA21 www.datasheetarchive.com/files/intel/products one/design/intarch/techinfo/430tx/pinout.htm |
Intel | 04/05/1999 | 72.73 Kb | HTM | pinout.htm |
| CLK48 L03 OSC V11 TEST www.datasheetarchive.com/files/intel/products one/design/intarch/techinfo/430tx/tstablty.htm |
Intel | 04/05/1999 | 121.78 Kb | HTM | tstablty.htm |
| :7], REQ[A:C]#, APICREQ#, IRQ[1, 3:7, 9:12, 14:15], PIRQ[A:D], SERIRQ, CLK48, PCICLK, OSC, PDD[15 , CLK48, PCICLK, OSC, PDD[15:0], PDDREQ, PIORDY, SDD[15:0], SDDREQ, SIORDY, OC[1:0]#, PCIREQ www.datasheetarchive.com/files/intel/products one/design/intarch/techinfo/430tx/elecpix4.htm |
Intel | 04/05/1999 | 366.08 Kb | HTM | elecpix4.htm |
| _CBUS_PWRON , FT_CBUS_RXLED, FT_CBUS_TXLED, FT_CBUS_TXRXLED, FT_CBUS_SLEEP, FT_CBUS_CLK48, FT _CBUS_PWRON , FT_CBUS_RXLED, FT_CBUS_TXLED, FT_CBUS_TXRXLED, FT_CBUS_SLEEP, FT_CBUS_CLK48, FT _CBUS_PWRON , FT_CBUS_RXLED, FT_CBUS_TXLED, FT_CBUS_TXRXLED, FT_CBUS_SLEEP, FT_CBUS_CLK48, FT _CBUS_PWRON , FT_CBUS_RXLED, FT_CBUS_TXLED, FT_CBUS_TXRXLED, FT_CBUS_SLEEP, FT_CBUS_CLK48, FT _CBUS_PWRON , FT_CBUS_RXLED, FT_CBUS_TXLED, FT_CBUS_TXRXLED, FT_CBUS_SLEEP, FT_CBUS_CLK48, FT www.datasheetarchive.com/download/63991159-117293ZC/ftd2xx_net.xml |
FTDI | 23/05/2012 | 75.1 Kb | XML | ftd2xx_net.xml |
| Selection results for Consumer Multimedia, 650 results shown. "Type number","Series","PACKAGE","Category","hFE min","POLARITY","Ptot max","hFE max","VCEO max","Complement","IOmax","Input Resistor","fT RATIO","No. of Pins","FUNCTION","Memory Size","REMARKS","Operating Type","I/Opins","RAM","Timers","PWMs","Memory Type","Reset Active Low or High","Seria www.datasheetarchive.com/download/7491827-649165ZC/27117_e.csv |
Philips | 13/06/2005 | 868.37 Kb | CSV | 27117_e.csv |
| Wait_0 SUBS R6, R6, #1 ; Delay ~100 ms @ proc clk 48 MHz ; Number of cycles to delay Wait_1 SUBS R6, R6, #1 ; Delay ~10 ms @ proc clk 48 www.datasheetarchive.com/download/56892061-30216ZC/rl-arm_gs_examples.zip (LPC2300.s) |
ARM | 20/05/2010 | 22570.37 Kb | ZIP | rl-arm_gs_examples.zip |
| Wait_0 SUBS R6, R6, #1 ; Delay ~100 ms @ proc clk 48 MHz ; Number of cycles to delay Wait_1 SUBS R6, R6, #1 ; Delay ~10 ms @ proc clk 48 www.datasheetarchive.com/download/56892061-30216ZC/rl-arm_gs_examples.zip (LPC2300.s) |
ARM | 20/05/2010 | 22570.37 Kb | ZIP | rl-arm_gs_examples.zip |