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Part : NS-CLK21 Supplier : OMRON Manufacturer : Avnet Stock : - Best Price : $1084.00 Price Each : $1341.00
Part : NSJW-CLK21-V1 Supplier : OMRON Manufacturer : Avnet Stock : - Best Price : $673.8900 Price Each : $833.2900
Part : ECLK2125 Supplier : Siemens Manufacturer : Allied Electronics & Automation Stock : - Best Price : $22.21 Price Each : $23.00
Part : ECLK2150 Supplier : Siemens Manufacturer : Allied Electronics & Automation Stock : - Best Price : $97.44 Price Each : $102.57
Part : NS-CLK21 Supplier : OMRON Manufacturer : Heilind Electronics Stock : - Best Price : - Price Each : -
Part : NSJW-CLK21-V1 Supplier : OMRON Manufacturer : Heilind Electronics Stock : - Best Price : - Price Each : -
Part : CQM1HCLK21 Supplier : OMRON Manufacturer : Master Electronics Stock : 2 Best Price : $1087.10 Price Each : $1087.10
Part : NS-CLK21 Supplier : OMRON Manufacturer : Sager Stock : - Best Price : $1123.85 Price Each : $1242.15
Part : NSJW-CLK21-V1 Supplier : OMRON Manufacturer : Sager Stock : - Best Price : $698.25 Price Each : $771.75
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CLK21 Datasheet

Part Manufacturer Description PDF Type
CLK-215S Synergy Microwave DOUBLE -BALANCED STARVED L.O. MIXER Original
CLK-215S Synergy Microwave Mixers Double Balanced (LO +7 dBm) Original

CLK21

Catalog Datasheet MFG & Type PDF Document Tags

manchester verilog decoder

Abstract: philips application manchester = Time= 50,rst=0,clk2=1,mdi=1,md , =0,clk2=1,mdi=0,md
Philips Semiconductors
Original
AN070 manchester verilog decoder philips application manchester Verilog implementation of a Manchester Encoder/Decoder manchester encoder an070 manchester code verilog

manchester code verilog

Abstract: philips application manchester = Time= 50,rst=0,clk2=1,mdi=1,md , =0,clk2=1,mdi=0,md
Philips Semiconductors
Original

manchester verilog decoder

Abstract: MD1010 =0 Time= 49,rst=0,clk2=0,mdi=1 ,md=0000000000,sync_puise=0,valid_md=0 Time= 50,rst=0,clk2=1 ,mdi=1 ,md , =0000000011,sync_pulse=0,valid_md=0 Time= 250,rst=0,clk2=1 ,mdi=1 ,md=0000000111 ,sync_pulse=0,valid_md=0 Time= 300,rst , =0000000111 ,sync_puise=0,valid_md=0 Time= 350,rst=0,clk2=1 ,mdi , =0,valid_md=0 Time= Time= 650,rst=0,clk2=1 ,mdi
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OCR Scan
MD1010 DK20-9.5/110/124

KS0083

Abstract: width Set up time D before CLK21 Hold time D after CLK2i Clock margin time 1 Ifrom CLK11 to CLK21] Clock margin time 2 NOTE 1 (from CLK21 to CLK11 ) Clock margin time 3 (from CLK2t to C L K 11 ) Clock rise fall , Hold time D after CLK2A Clock margin time 1 (from CLK1I to CLK21) Clock margin time 2 NOTE 1 ifrom C , 2 NOTE 1 (from CLK21 to C LK U J Clock margin time 3 (from CLK2t to C LK I t) C I o c k rise fall
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OCR Scan
KS0083 KS0083/84 80-CHANNEL KS0084 KS0103 KS0104

82C231

Abstract: Unicorn Microelectronics . 8 14 19 ns t2 RAS inactive from CLK21 10 19 25 ns t3 Column address valid from CLK21 8 15 20 ns t4 Column address invalid from CLK21 9 18 24 ns t5 CAS active from CLK21 8 14 19 ns t6 CAS inactive from CLK21 10 19 25 ns t7 RDY active from CLK2J 11 20 30 ns t8 RDY inactive from CLK2j 13 22 32 ns t9 WÃ' active from CLK2 4 8 15 20 ns tio WÃ' inactive from CLK21 9 16 21 ns til ROMCS active from CLK2 J 8 15 20 ns tl2 ROMCS inactive from CLK21 9 16 21 ns tl3 RAS active from ATMR1 6 10 17 ns tl4
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OCR Scan
UM82C231 82C231 Unicorn Microelectronics um82c232 refresh logic M16I45 82c232 Q-32- 33-I5 IRQ13

FI-X30H

Abstract: lq315t3lz24 30 1 TOLERANCE: HS1 NC 30 NC 29 U/D 28 R/L 27 NC 26 TX3+ 25 TX324 GND8 23 CLK+ 22 CLK21 GND7 20 TX2+ 19 TX218 NC 17 TX1+ 16 TX115 GND6 14 TX0+ 13 TX012 GND5 11 NC 10 NC 9 GND4 8 GND3 7 GND2 6 GND1 5 5VLCD4 4 5VLCD3 3 5VLCD2 2 5VLCD1 1 FI-X30H JAE +10mm -10mm TX0+ TX1+ R/L TX2+ TX3+ GND7 CLK+ GND5 GND3 GND1 5VLCD2 5VLCD1 CN2 TX02 1 TX14 3 U/D 6 5 TX28 7 TX310 9 GND8 12 11 CLK14 13 GND6 16 15 18
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Original
DF-40DS-1 lq315t3lz24 LQ315T3 lvds 26 pin for jae 30 pin JAE LVDS 30 PIN LVDS 30 pin cable DF13-40DS-1 30AWG LQ315T3LZ24 SVH-1920 C6490400

74148 pin configuration

Abstract: KS0083 time D after CLK21 th 50 Clock margin time 1 (from CLKU to CLK2J-) tei 20 ns Clock margin time , before CLK2A tsu 70 Hold time D after CLK2-1 th - 50 Clock margin time 1 (from CLK11 to CLK2Ã
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OCR Scan
74148 pin configuration 74148 PIN DIAGRAM 7 segment digital clock circuit SC80 pin diagram of 74148 74142 NOTE 100QFP 47ISC47 3SC44 HSC42 0GS07

laptop motherboard resistors

Abstract: 775 MOTHERBOARD CIRCUIT diagram POWER SUPPLY (+5V DC) REFCLK2 18 Output REFERENCE CLOCK output #2. Produces 7.159 MHz clock CLK21 19 , â¡ DGN'D H CL.K22 â¡ CLK21 â¡ REFCI.K2 â¡ A VDD â¡ PD- â¡ SCLK1 Decoding Tables for AV9129 , 1.844 CLOCK#2 CLOCK#3 SCLK22 SCLK21 SCLK20 (Pin 26) (Pin 27) (Pin 28) CLK22-5 CLK21 (Pins 20.23-25
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OCR Scan
AV9128 laptop motherboard resistors 775 MOTHERBOARD CIRCUIT diagram ALL LAPTOP MOTHERBOARD CIRCUIT DIAGRAM laptop motherboard circuit diagram UL 486 tables AV9128/9 AV9127 AV9129-06 AV9129-23

775 MOTHERBOARD CIRCUIT diagram

Abstract: AV9127 ) REFCLK2 18 Output REFERENCE CLOCK output #2. Produces 7.159 MHz clock CLK21 19 Output CLOCK2 output #1 , c 7 1J NC 22 â¡ VDD DGND c 8 Ã" ON 21 â¡ DGND CLK3 L 9 20 Il CI.K22 CLK42 C 10 1-9 Il CLK21 , 28) CLK22-5 CLK21 (Pins 20.23-25) (Pin 19) 0 o n 66.63 33.32 0 0 1 50.11 25.06 0 1 0 40.09 20.05
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OCR Scan
AV9128-24 14.318 crystal AV9129-08 AAN02 AV9128- V9129- AV9129-

CLK19

Abstract: CB683 CLK1 CLK2 VSS VDD2 CLK3 CLK4 VSS VDD3 CLK5 CLK6 SDATA CLK20 CLK21 VDD10 VDD CIN1
International Microcircuits
Original
CB683 CLK19 CLK12 CLK10 CLK22 VDD11 CLK24

D2877

Abstract: C1HS % CLK 11 50% CLK21 50% CLK1T 10% CLK2T 10% CLK 90% CLKIT 10% CLK11 50% CLKIT 0.8 V SPC1 nsc , : 2 V SPCT 50% CLK21 0.8/2 V D0-D1 5 0.8 V ADST tSPCa 'SPCii
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OCR Scan
D2877 C1HS coprocesor TIC 2260 AD12 TI32082W-2 TI32016T TI32032T AD0-AO15

AT17256

Abstract: UNSIGNED SERIAL DIVIDER using vhdl std_logic_vector (15 downto 0) ); end component; signal clk21 : s td jo g ic ; AN076 1998 Jul 21 553 , sw_out , map (rst,clk21 ,p_f,lcd_out) ; end v1 ; Appendix 6 - Philips CPLD Applications - LCD driver - F , unsigned (9 downto 0) ); end component; signal clk21 : std jo g ic ; signal signal signal signal signal , cnt_out
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OCR Scan
AT17256 UNSIGNED SERIAL DIVIDER using vhdl UNSIGNED SERIAL DIVIDER using verilog XPLA1 AT-2 PZ3960 PZ3128 PZ5000 PZ3000

CB683AAB

Abstract: CLK19 CLK1 CLK2 VSS VDD2 CLK3 CLK4 VSS VDD3 CLK5 CLK6 SDATA CLK20 CLK21 VDD10 VDD CIN1 , ) CLK23 (Active = 1, Forced low = 0) CLK24 (Active = 1, Forced low = 0) CLK21 (Active = 1, Forced low =
International Microcircuits
Original
CB683AAB IMICB683AAB
Abstract: CLK21 C 2 VDD1 0 C 3 VDD C 4 CIN1 E 5 SC LK E 6 SDATA C 7 CIN2 CIN3 vss VDD11 CLK24 CLK23 , 49 Description CLK22 (Active CLK23 (Active CLK24 (Active CLK21 (Active CLK20 (Active CLK19 -
OCR Scan

acer adapter circuit diagram

Abstract: cs8221 neat the AT bus state machine clock, BCLK (internai) will not be derived from CLK21N. This qiock input , sequences 1 and 2, I ALE is generated from CLK21N. AF16 is sampled to be low in sequence 2. ALE and AT bus , = CLK21N/4 Figure 1.2 Clock Selection Block Diagram RESET3 is also activated by the 82C211 when a , CLK2IN. ATCLK and CLK21N can be selected under program con- 19 Asynchronous mode 1. PROCCLK = CLK2IN , 82C21~iy Under Normal mode: PROCCLK = CLK21N BCLK = CLK2IN/2 SYSCLK = CLK2IN/4 Since the CPU state
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OCR Scan
CS8221 82C206 acer adapter circuit diagram cs8221 neat 80286 chipset neat chipset CHIPS TECHNOLOGIES CHIPset for 80286 T-SZ-33-05 AT/286 84-PIN

yg 2822

Abstract: RAS 0510 Clock margin time 1 (from CLK1 i to CLK2J) tei 20 Clock margin time 2 NOTE 1 (from CLK21 to , 1i to CLK2i) tei 20 Clock margin time 2 NOTE 1 (from CLK21 to C LKU ) tC2 200
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OCR Scan
yg 2822 RAS 0510 Waukesha 6670 82C631 2021G chipset 82c206 2-221-B CHIPS/280 CHIPS/250 CHIPS/230 CHIPS/450

chipset 82c206

Abstract: 82C206 USB clock is CLK19. 1000 USB clock is CLK21. 1001 USB clock is BRG9. 1010 USB clock is BRG10 , CLK21 011 Time Stamp 1 clock source is BRG11 100 Time Stamp 1 clock source is External RTC clock2 On , clock source is CLK21 011 Time Stamp 2 clock source is BRG11 100 Time Stamp 2 clock source is External , clock source is CLK21 011 QUICC Engine Timer clock source is BRG11 100 QUICC Engine Timer clock source
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OCR Scan
ARCHITECTURE OF 80286 bios chip manufacturer 82c206 ipc LIM EMS 4.0 iAPX 88 Book 82C212 P82C211/212/215/206 PLCC-84 F82C211/212/215/206 PFP-100
Abstract: downto 0) ); end component ; signal clk21 : std_logic ; 1998 Jul 21 19 AN076 Philips , ; clk21 , clk21 : std_logic ; signal cmp_out : std_logic_vector (9 downto 0) ; signal decod_out , ) ; clk_out -
OCR Scan
KS0083/64 KS0083/S4 60-QFP-UUA 64-QFP-1420D Q0220 0D220

UCC71

Abstract: UCCM . 8 14 19 ns t2 RAS inactive from CLK21 10 19 25 ns t3 Column address valid from CLK21 8 15 20 ns t4 Column address invalid from CLK21 9 18 24 ns t5 CAS active from CLK21 8 14 19 ns t6 CAS inactive from CLK21 10 19 25 ns t7 RDY active from CLK2J 11 20 30 ns t8 RDY inactive from CLK2j 13 22 32 ns t9 WÃ' active from CLK2 4 8 15 20 ns tio WÃ' inactive from CLK21 9 16 21 ns til ROMCS active from CLK2 J 8 15 20 ns tl2 ROMCS inactive from CLK21 9 16 21 ns tl3 RAS active from ATMR1 6 10 17 ns tl4
Freescale Semiconductor
Original
MPC8360E MPC8569E MSC8144 MPC8568E UCC71 UCCM bmrx IEEE1588v2 MPC8360E user manual MSC815

AT17256

Abstract: UNSIGNED SERIAL DIVIDER using vhdl POWER SUPPLY (+5V DC) REFCLK2 18 Output REFERENCE CLOCK output #2. Produces 7.159 MHz clock CLK21 19 , â¡ DGN'D H CL.K22 â¡ CLK21 â¡ REFCI.K2 â¡ A VDD â¡ PD- â¡ SCLK1 Decoding Tables for AV9129 , 1.844 CLOCK#2 CLOCK#3 SCLK22 SCLK21 SCLK20 (Pin 26) (Pin 27) (Pin 28) CLK22-5 CLK21 (Pins 20.23-25
Philips Semiconductors
Original
7Pin din Connector qfp 32 k2511 phillips handbook PZ3320
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