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CLK14M

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: , ANA1, ANA2, IREFOT1, IREFOT2, VREF1, VREF2, COMP1, COMP2 (2) DIN[8:1], CLK14M, CLK10M, HDI, VDI , [32:9], DEVICE, MIRRO, SUPER, INMODE, WBHL, DOSL, SSET [2:1], OMODE [4:1], RES (2) DIN[8:1], CLK14M , , DOSL, SSET [2:1], OMODE [4:1], RES (2) DIN [8:1], CLK14M, CLK10M, HDI, VDI, HREF53, ENS, DATAS, CLKS , 57 OMODE2 I 58 OMODE3 I 59 OMODE4 I 60 HREF53 I 61 CLK14M I , ), fixed at high level, C.SYNC (LC99053 pin 54) 64 CLK14M I 65 VDD (logic) P HTCLK SANYO Electric
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SQFP100 DIN32 EN5787 LC99063-LF2 LC9997M/FL 3181B-SQFP100
Abstract: , CLKOUT, ANA1, ANA2, IREFOT1, IREFOT2, VREF1, VREF2, COMP1, COMP2 (2) DIN[8:1], CLK14M, CLK10M, HDI, VDI , ], CLK14M, CLK10M, HDI, VDI, HREF53, ENS, DATAS, CLKS, REGRES SANYO Electric Co.,Ltd. Semiconductor , , INMODE, WBHL, DOSL, SSET [2:1], OMODE [4:1], RES (2) DIN [8:1], CLK14M, CLK10M, HDI, VDI, HREF53, ENS , OMODE4 I 60 HREF53 I 61 CLK14M I 62 VDI I 63 HDI I Function , (LC99053 pin 55) or HTCLK (LC99053 pin 51), fixed at high level, C.SYNC (LC99053 pin 54) 64 CLK14M SANYO Electric
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Abstract: Clock generator 1/3 Host Clock (HCLK) Frequency set at power-up by 3 strap inputs Frequency available: 50, 66 and 80 MHz ISA Clock (ISACLK) Frequency can be selected by software Frequency available: CLK14M/2 or PCICLK/4 PCI Clock (PCICLK) Frequency set at power-up by a strap input Frequency available: HCLK/2 or HCLK/3 Single 14MHz input required !!! ® 05/03/00 1 / 44 Clock generator 2/3 Dot Clock (DCLK) Frequency selectable by software Frequency range from 8 to 135 MHz Internally STMicroelectronics
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CLK14M/2 OSC14M 318MH OSC14M/2
Abstract: , CKO (11) .DHT1, DHT2 (12) .DS1, DS2 (13) .AGCC2, IRSTA (14) .CLK14M, CLP1, CLP2, FLD, HD , CLK14M HD VD FLD VDD KISYU HR VR VSS SELMET1 SELMET2 EXT 1 EXT2 EXT3 EXT4 V DD I/O P 0 I O I 0 I I 0 , CCDSCAN SSGSCAN CLK14M HD VD 0 1 1 0 0 0 12 FLD O 13 14 15 16 17 18 19 20 21 22 23 24 25 -
OCR Scan
DHT2 drive control damp iris LC99012A JK5201A LC99012A-S 3190-SQFP64 9947G 9948G LC9949G
Abstract: Clock generator 1/3 Host Clock (HCLK) Frequency set at power-up by 3 strap inputs Frequency available: 50, 66 and 75 MHz ISA Clock (ISACLK) Frequency can be selected by software Frequency available: CLK14M/2 or PCICLK/4 PCI Clock (PCICLK) Frequency set at power-up by a strap input Frequency available: HCLK/2 or HCLK/3 Single 14MHz input required !!! ® 03/30/00 1 / 44 Clock generator 2/3 Dot Clock (DCLK) Frequency selectable by software Frequency range from 8 to 135 MHz Internally STMicroelectronics
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Abstract: Clock generator 1/3 Host Clock (HCLK) Frequency set at power-up by 3 strap inputs Frequency available: 100 and 133 MHz ISA Clock (ISACLK) Frequency can be selected by software Frequency available: CLK14M/2 or PCICLK/4 PCI Clock (PCICLK) Frequency set at power-up by a strap input Frequency available: HCLK/2 or HCLK/3 or HCLK/4 Single 14MHz input required !!! ® 05/03/00 1 / 44 Clock generator 2/3 Dot Clock (DCLK) Frequency selectable by software Frequency range from 8 to 135 MHz STMicroelectronics
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Abstract: Clock generator 1/3 Host Clock (HCLK) Frequency set at power-up by 3 strap inputs Frequency available: 66, 75 and 90 MHz ISA Clock (ISACLK) Frequency can be selected by software Frequency available: CLK14M/2 or PCICLK/4 PCI Clock (PCICLK) Frequency set at power-up by a strap input Frequency available: HCLK/2 or HCLK/3 Single 14MHz input required !!! ® 05/02/00 1 / 44 Clock generator 2/3 Dot Clock (DCLK) Frequency selectable by software Frequency range from 8 to 135 MHz Internally STMicroelectronics
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Abstract: Clock generator 1/3 Host Clock (HCLK) Frequency set at power-up by 3 strap inputs Frequency available: 50, 66 and 80 MHz ISA Clock (ISACLK) Frequency can be selected by software Frequency available: CLK14M/2 or PCICLK/4 PCI Clock (PCICLK) Frequency set at power-up by a strap input Frequency available: HCLK/2 or HCLK/3 Single 14MHz input required !!! ® 03/30/00 1 / 44 Clock generator 2/3 Dot Clock (DCLK) Frequency selectable by software Frequency range from 8 to 135 MHz Internally STMicroelectronics
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Abstract: (12) .DS1, DS2 (13) .AGCC2, IRSTA (14) .CLK14M, CLP1, CLP2, FLD, HD, NSUB1, NSUB2, VD (15 , 7 CCDSCAN I 58 IRSTA O 8 SSGSCAN I 57 AGCC2 O 9 CLK14M O , mode High: C.SYNC non-interlaced mode 9 CLK14M O LC9947G/9949G: 14.31818 MHz LC9948G SANYO Electric
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LC9947G SQFP64 block diagram of iris scan 22 pin ccd iris scan CCD IMAGE 5281A CCD 22 pin SQFP-64
Abstract: , A N A2, IR EFO T1, IR EFO T2, V R EF1, V R EF2, C O M P Ì, C O M P2 (2) DIN [8:1], CLK14M , C , SSET [2: 1] device DIN [32 : 9] D IN [8 : 1] HREF53 MIRRO NB HL HDI VDI CLK14M -
OCR Scan
99063-L LC9997M LK10M 99053-Z
Abstract: Vcc2V5_1 Vcc3V3 100nF C55 15k R15 2 2 CLK_14M Date: Size A2 Title , Vcc2V5_3 CLK_14M PLLVDD CRM_CKM Vcc_ANALOG 1 JP4 47uF + C4 620R R5 JP5 Fujitsu
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Hsync Vsync csync 74ALS1034 MD55 CREMSON-STARTERKIT-CRM PAL AM 16v8 MD56 FUJ23B
Abstract: . This is the output of the audio timer. CLK14M: 14 MHz Clock. This input drives the internal logic in , PARPEN SER1CSN PAR TDI VSS VDD TDO CLK1M CLK14M WR0076N KYBDCSN FDCPCSN AUDIO INTR , CA2 CREFRESHN CLK14M TESTN CA5 CA 4 CA7 CA6 CA9 CA 8 CLKIM CAUPPERN PPSTBN CIOCHKN -
OCR Scan
AZ9051 AZ9031 floppy disk chip Bull Micral of America CLK16U RD0076n 03BC-03BF
Abstract: 205 VDD18 VSS16 CLK14M TEST2 CPUCLK2 TEST1 SELCLK TEST0 CPUCLK1 VDD17 STBYCLK PWI6 PWI5 , ) input at start-up and suspended operation 254 CLK14M 248 CPUCLK1 252 CPUCLK2 250 , removed: VDD1 group pins CLK14M, KBA20M, PWI1 to PWI6, NIRQ8, NEXSMI, NKBCPRST Input threshold -
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MN5520A MN5521 MN871107 486SX/DX/ LS612 128-K
Abstract: . 15 1.4.25 CLK14M , voltage FSC Input high voltage FSC Input low voltage CLK14M Output High Voltage CLK14M Output Low , serial SMBus should operate at a minimum 10 kHz and maximum 100 kHz clock rate. 1.4.25 CLK14M 14 MHz , digital output signal to the SCH. It is derived form the master clock CLK14M divided by 437. The RTC Dialog Semiconductor
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DA6001 144LD
Abstract: inputs (Normally keep these at "L" level.) STBYCLK CLK14M CPUCLK1 CPUCLK2 SELCLK O I 1 IS Operating clock , group pins CLK14M, KBA20M, PWI1 to PWI6, NIRQ8, NEXSMI, NKBCPRST v, I li V dd- V ddi Input -
OCR Scan
04A05 G01552 LGA288-C-1717 MN5220A 2SST00 92ELR
Abstract: PCI_CLKI I PCI_CLKO O ISA_CLK, ISA_CLK2X O CLK14M O HCLK I/O DEV_CLK O GCLK2X I/O DCLK I/O , . CLK14M ISA bus synchronisation clock. This is the buffered 14.318 Mhz clock to the ISA bus. This clock STMicroelectronics
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82C206 PBGA388 3SD11 40-pin panellink bios stpc 66MHz bt ramdac chipset 82c206 64-BIT 135MH
Abstract: PCI_CLKO O ISA_CLK, ISA_CLK2X O CLK14M O HCLK* I/O DEV_CLK* O GCLK2X I/O DCLK I/O VDD_xxx_PLL , buffered version of this output. CLK14M ISA bus synchronisation clock. This is the buffered 14.318 Mhz STMicroelectronics
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JEIDA 3 68-pin MD-45 MD10 MD11 TTL LS 7407 STPCI0166BTC3 STPCI0180BTC3 STPCI0166BTI3 STPCI0180BTI3
Abstract: ] .vlbus2 .clk32k .clk14m clocks 24 25 [] [] [] 27 i54:100K c0 154 Rh 203 , [0.7] datah [8.15] nc* clocks.clk14m Note: Use xtal here if the clk14m is not accurate Digital Systems Research Center
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CV 203 F65550B ct65550 cmps 10 PT86C718A2 F65550 RS232
Abstract: ISA_CLK, ISA CLK2X CLK14M HCLK DEV_CLK G CLK2X DCLK M EM O RY INTERFACE M A [11 :0] RAS#[3:0] CAS#[7:0] M , SIGNAL DESCRIPTIONS BASIC CLOCKS AND RESETS CLK14M ISA bus synchronisation clock. This is the buffered , AD16 Pin name PW ERG D SYSR S ETO # XTALI XTALO PCLCLKI PCI_CLKO ISA_CLK IS A C L K 2 X CLK14M HCLK -
OCR Scan
388-P I0166BTC I0175BTC I0180BTC I0110BTC3 I0112BTC
Abstract: SYSRSTO#* O XTALI I XTALO O PCI_CLKI* I PCI_CLKO O ISA_CLK, ISA_CLK2X O CLK14M O HCLK* I/O , multiplexor control lines for the Interrupt Controller Interrupt input lines. CLK14M ISA bus synchronisation STMicroelectronics
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4mbyte flash eprom ae1 tft T-51-
Abstract: Clock generator 1/3 Host Clock (HCLK) Frequency set at power-up by 3 strap inputs Frequency available: 50, 66 and 80 MHz ISA Clock (ISACLK) Frequency can be selected by software Frequency available: CLK14M/2 or PCICLK/4 PCI Clock (PCICLK) Frequency set at power-up by a strap input Frequency available: HCLK/2 or HCLK/3 Single 14MHz input required !!! ® 05/03/00 1 / 44 Clock generator 2/3 Dot Clock (DCLK) Frequency selectable by software Frequency range from 8 to 135 MHz Internally -
OCR Scan
SBP9989 SBP9964 SBP9900A P9900A/SB P9989 P9964C
Abstract: PCI_CLKI* I PCI_CLKO O ISA_CLK, ISA_CLK2X O CLK14M O HCLK* I/O DEV_CLK* O GCLK2X I/O DCLK I , Interrupt input lines. CLK14M ISA bus synchronisation clock. This is the buffered 14.318 MHz clock to the -
OCR Scan
MN5520 i486 DX2 nbs16 NRAS11 LGA-28 D01552 FP256-P-2840 288-C
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