CLC428 DS012710-1 DS012710-2 DS012710-3 DS012710 DS012710-35 CLC428AJP - Datasheet Archive
Dual Wideband, Low Noise, Voltage Feedback Op Amp General Description The National CLC428 is a very high speed dual op amp that
CLC428 CLC428 Dual Wideband, Low Noise, Voltage Feedback Op Amp General Description The National CLC428 CLC428 is a very high speed dual op amp that offers a traditional voltage-feedback topology featuring unity gain stability and slew enhanced circuitry. The CLC428 CLC428's ultra low noise and very low harmonic distortion combine to form a very wide dynamic range op amp that operates from a single (5 to 12V) or dual ( ± 5V) power supply. Each of the CLC428 CLC428's closely matched channels provides a 160MHz unity gain bandwidth with an ultra low input voltage noise density (2nV/ ). Very low 2nd/3rd harmonic distortion (-62dB) make the CLC428 CLC428 a perfect wide dynamic range amplifier for matched I/Q channels. With its fast and accurate settling (16ns to 0.1%), the CLC428 CLC428 is also an excellent choice for wide dynamic range, anti-aliasing filters to buffer the inputs of hi-resolution analog-to-digital converters. Combining the CLC428 CLC428's two tightly matched amplifiers in a single eight-pin SOIC reduces cost and board space for many composite amplifier applications such as active filters, differential line drivers/receivers, fast peak detectors and instrumentation amplifiers. To reduce design times and assist in board layout, the CLC428 CLC428 is supported by an evaluation board and a SPICE simulation model available from National. n Settling time: 16ns to 0.1% n Supply voltage range: ± 2.5 to ± 5 or single supply n High output current: ± 70mA Applications n n n n n n General purpose dual op amp Low noise integrators Low noise active filters Diff-in/diff-out instrumentation amp Driver/receiver for transmission systems High speed detectors I/Q channel amplifiers Channel Matching Features n n n n Wide unity gain bandwidth: 160MHz Ultra low noise: 2.0nV/ Low Distortion: -78dBc 2nd (2MHz) Low Distortion: -62/-72dBc (10MHz) DS012710-1 DS012710-1 Typical Application 5-Decade Integrator Frequency & Phase Response DS012710-2 DS012710-2 DS012710-3 DS012710-3 © 2001 National Semiconductor Corporation DS012710 DS012710 www.national.com CLC428 CLC428 Dual Wideband, Low Noise, Voltage Feedback Op Amp September 2001 CLC428 CLC428 Connection Diagram DS012710-35 DS012710-35 Pinout DIP & SOIC Ordering Information Package Temperature Range Industrial Part Number Package Marking NSC Drawing 8-pin plastic DIP -40°C to +85°C CLC428AJP CLC428AJP CLC428AJP CLC428AJP N08E 8-pin plastic SOIC -40°C to +85°C CLC428AJE CLC428AJE CLC428AJE CLC428AJE M08A www.national.com 2 Storage Temperature Range Lead Temperature (soldering 10 sec) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage Short Circuit Current Common-Mode Input Voltage Differential Input Voltage Maximum Junction Temperature -65°C to +150°C +300°C Operating Ratings ± 7V (see note 6) ± VCC ± 10V +150°C Thermal Resistance Package MDIP SOIC (JC) 60°C/W 40°C/W (JA) 115°C/W 115°C/W Electrical Characteristics VCC = ± 5 V, AV = +2V/V, Rf =100, Rg = 100, RL = 100; unless specified. Symbol Parameter Ambient Temperature Conditions CLC428AJ CLC428AJ Typ Min/Max Ratings (Note 2) Units +25°C +25°C 0 to +70°C -40 to +85°C Frequency Domain Response Gain Bandwidth Product VOUT < 0.5VPP 135 100 80 70 MHz -3dB Bandwidth, AV = +1 VOUT < 0.5VPP VOUT < 0.5VPP VOUT < 5.0VPP VOUT < 0.5VPP 160 120 90 80 MHz 80 50 40 35 MHz 40 25 22 20 MHz dB AV = +2 Gain Flatness Peaking DC to 200MHz 0.0 0.6 0.8 1.0 Rolloff DC to 20MHz 0.05 0.5 0.7 0.7 dB DC to 20MHz 0.2 1.0 1.5 1.5 deg Rise and Fall Time 1V Step 5.5 7.5 9.0 10.0 ns Settling Time 2V Step to 0.1% 16 20 24 24 ns Overshoot 1V Step 1 5 10 10 % Slew Rate 5V Step 500 300 275 250 V/µs 2nd Harmonic Distortion 1VPP, 10MHz -62 -50 -45 -43 dBc 3rd Harmonic Distortion 1VPP, 10MHz -72 -60 -56 -56 dBc Voltage 1MHz to 100MHz 2.0 2.5 2.8 2.8 nV/ Current 1MHz to 100MHz 2.0 3.0 3.6 4.6 pA/ Input Referred, 10MHz -62 -58 -58 -58 Linear Phase Deviation Time Domain Response Distortion And Noise Response Equivalent Input Noise Crosstalk dB Static, DC Performance Open-Loop Gain 60 56 50 50 dB Input Offset Voltage (Note 3) 1.0 2.0 3.0 3.5 mV 5 - 15 20 µV/°C Average Drift Input Bias Current (Note 3) 1.5 Average Drift 65 µA 600 700 nA/°C 3 5 5 µA 5 Per Channel, RL = 3 25 50 nA/°C 60 55 55 dB 63 Common-Mode Rejection Ratio - 66 Power Supply Rejection Ratio (Note 4) Supply Current (Note 3) 40 - 0.3 Input Offset Current 25 150 Average Drift 57 52 52 dB 11 12 13 15 mA www.national.com CLC428 CLC428 Absolute Maximum Ratings (Note 1) CLC428 CLC428 Electrical Characteristics (Continued) VCC = ± 5 V, AV = +2V/V, Rf =100, Rg = 100, RL = 100; unless specified. Symbol Parameter Conditions Typ Min/Max Ratings (Note 2) Units Miscellaneous Performance Input Resistance Input Capacitance Common-Mode 500 250 125 125 k Differential-Mode 200 50 25 25 k Output Resistance Output Voltage Range Input Voltage Range Common-Mode 2.0 3.0 3.0 3.0 pF Differential-Mode 2.0 3.0 3.0 3.0 pF 0.05 Closed-Loop RL = RL = 100 Common- Mode Output Current 0.1 0.2 0.2 ± 3.8 ± 3.5 ± 3.7 ± 70 ± 3.5 ± 3.2 ± 3.5 ± 50 ± 3.3 ± 2.6 ± 3.3 ± 40 ± 3.3 ± 1.3 ± 3.3 ± 20 V V V mA Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" specifies conditions of device operation. Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Note 3: J-level: spec. is 100% tested at +25°C, sample tested at +85°C. Note 4: J-level: spec. is 100% tested at +25°C. Note 5: Specifications guaranteed using 0.5VPP but tested at 0.1 VPP. Note 6: Output is short circuit protected to ground, however maximum reliability is obtained if output current does not exceed 160mA. Typical Performance Characteristics (TA = +25°, AV = +2, VCC = ± 5V, Rf =100, RL = 100, un- less specified) Non-Inverting Frequency Response Inverting Frequency Response DS012710-4 DS012710-4 Frequency Response vs. Load Resistance DS012710-5 DS012710-5 Frequency Response vs. Output Amplitude DS012710-6 DS012710-6 www.national.com DS012710-7 DS012710-7 4 (TA = +25°, AV = +2, VCC = ± 5V, Rf =100, RL = 100, unless specified) (Continued) Frequency Response vs. Capacitive Load Gain Flatness & Linear Phase Deviation DS012710-9 DS012710-9 DS012710-8 DS012710-8 Maximum Output Voltage vs. Load Channel-to-Channel Crosstalk DS012710-10 DS012710-10 Open-Loop Gain & Phase DS012710-11 DS012710-11 2nd and 3rd Harmonic Distortion DS012710-12 DS012710-12 DS012710-13 DS012710-13 5 www.national.com CLC428 CLC428 Typical Performance Characteristics CLC428 CLC428 Typical Performance Characteristics (TA = +25°, AV = +2, VCC = ± 5V, Rf =100, RL = 100, unless specified) (Continued) 2nd Harmonic Distortion vs. Output Voltage 3rd Harmonic Distortion vs. Output Voltage DS012710-14 DS012710-14 Closed-Loop Output Resistance DS012710-15 DS012710-15 Equivalent Input Noise DS012710-17 DS012710-17 DS012710-16 DS012710-16 2-Tone, 3rd Order Intermodulation Intercept Pulse Response (VOUT = 100V) DS012710-18 DS012710-18 www.national.com DS012710-19 DS012710-19 6 (TA = +25°, AV = +2, VCC = ± 5V, Rf =100, RL = 100, unless specified) (Continued) Pulse Response (VOUT = 2V) Settling Time vs. Capacitive Load DS012710-20 DS012710-20 DS012710-21 DS012710-21 Short-Term Settling Time CMRR and PSRR DS012710-22 DS012710-22 DS012710-23 DS012710-23 Typical DC Errors vs. Temperature DS012710-24 DS012710-24 7 www.national.com CLC428 CLC428 Typical Performance Characteristics CLC428 CLC428 Application Division Low Noise Design Ultimate low noise performance from circuit designs using the CLC428 CLC428 requires the proper selection of external resistors. By selecting appropriate low valued resistors for Rf and Rg, amplifier circuits using the CLC428 CLC428 can achieve output noise that is approximately the equivalent voltage input noise of 2.0 nV/ multiplied by the desired gain (AV). Each amplifier in the CLC428 CLC428 has an equivalent input noise resistance which is optimum for matching source impedances of approximately 1k. Using a transformer, any source can be matched to achieve the lowest noise design. For even lower noise performance than the CLC428 CLC428, consider the CLC425 CLC425 or CLC426 CLC426 at 1.05 and 1.6nV/ , respectively. DC Bias Currents and Offset Voltages Cancellation of the output offset voltage due to input bias currents is possible with the CLC428 CLC428. This is done by making the resistance seen from the inverting and non-inverting inputs equal. Once done, the residual output offset voltage will be the input offset voltage (Vos) multiplied by the desired gain (Av). Comlinear Application Note OA-7 offers several solutions to further reduce the output offset. Output and Supply Considerations With ± 5V supplies, the CLC428 CLC428 is capable of a typical output swing of ± 3.8V under a no-load condition. Additional output swing is possible with slightly higher supply voltages. For loads of less than 50, the output swing will be limited by the CLC428 CLC428's output current capability, typically 80mA. Output settling time when driving capacitive loads can be improved by the use of a series output resistor. See the plot labeled 'Settling Time vs. Capacitive Load' in the Typical Performance section. Layout Proper power supply bypassing is critical to insure good high frequency performance and low noise. De-coupling capacitors of 0.1µF should be placed as close as possible to the power supply pins. The use of surface mounted capacitors is recommended due to their low series inductance. A good high frequency layout will keep power supply and ground traces away from the inverting input and output pins. Parasitic capacitance from these nodes to ground causes frequency response peaking and possible circuit oscillation. See OA-15 OA-15 for more information. National suggests the 730038 (through-hole) or the 730036 (SOIC) dual op amp evaluation board as a guide for high frequency layout and as an aid in device evaluation. Analog Delay Circuit (All-Pass Network) The circuit in Figure 1 implements an all-pass network using the CLC428 CLC428. A wide bandwidth buffer (CLC111 CLC111) drives the circuit and provides a high input impedance for the source. As shown in Figure 2, the circuit provides a 13.1ns delay (with R = 40.2, C = 47pF). Rf and Rg should be of equal and low value for parasitic insensitive operation. www.national.com DS012710-25 DS012710-25 FIGURE 1. DS012710-26 DS012710-26 FIGURE 2. Delay Circuit Response to 0.5V Pulse The circuit gain is +1 and the delay is determined by the following equations. (1) Td = 1 d 360 df ; (2) where Td is the delay of the op amp at AV=+1. The CLC428 CLC428 provides a typical delay of 2.8ns at its -3dB point. Full Duplex Digital or Analog Transmission Simultaneous transmission and reception of analog or digital signals over a single coaxial cable or twisted-pair line can reduce cabling requirements. The CLC428 CLC428's wide bandwidth and high common-mode rejection in a differential amplifier configuration allows full duplex transmission of video, telephone, control and audio signals. In the circuit shown in Figure 3, one of the CLC428 CLC428's amps is used as a 'driver' and the other as a difference 'receiver' amplifier. The output impedance of the 'driver' is essentially zero. The two R's are chosen to match the characteristic impedance of the transmission line. The 'driver' op amp gain can be selected for unity or greater. Receiver amplifier A2 (B2) is connected across R and forms differential amplifier for the signals transmitted by driver A2 (B2). If the coax cable is lossless and Rf equals Rg, receiver A2 (B1) will then reject the signals from driver A1 (B1) and pass the signals from driver B1 (A1). 8 A resistive divider made from the 143 and 60.4 resistors was chosen to reduce the loop-gain and stabilize the network. The CLC428 CLC428 composite integrator provides integration over five decades of operation. R and C set the integrator's gain. Figure 6 shows the frequency and phase response of the circuit in Figure 5 with R = 44.2 and C = 360pF. (Continued) DS012710-29 DS012710-29 FIGURE 3. The output of the receiver amplifier will be: (3) Care must be given to layout and component placement to maintain a high frequency common-mode rejection. The plot of Figure 4 shows the simultaneous reception of signals transmitted at 1MHz and 10MHz. DS012710-34 DS012710-34 FIGURE 6. Positive Peak Detector The CLC428 CLC428's dual amplifiers can be used to implement a unity-gain peak detector circuit as shown in Figure 7. Q1 DS012710-31 DS012710-31 DS012710-36 DS012710-36 FIGURE 4. FIGURE 7. Five Decade Integrator A composite integrator, as shown in Figure 5, uses the CLC428 CLC428 dual op amp to increase the circuits' usable frequency range of operation. The transfer function of this circuit is: The acquisition speed of this circuit is limited by the dynamic resistance of the diode when charging Chold. A plot of the circuit's performance is shown in Figure 8 with a 1MHz sinusoidal input. (4) DS012710-33 DS012710-33 FIGURE 5. DS012710-37 DS012710-37 FIGURE 8. 9 www.national.com CLC428 CLC428 Application Division CLC428 CLC428 Application Division To build a boost circuit, use the design equations Eq. 6 and Eq. 7. (Continued) A current source, built around Q1, provides the necessary bias current for the second amplifier and prevents saturation when power is applied. The resistor, R, closes the loop while diode D2 prevents negative saturation when Vin is less than VC. A MOS-type switch (not shown) can be used to reset the capacitor's voltage. The maximum speed of detection is limited by the delay of the op amps and the diodes. The use of Schottky diodes will provide faster response. Adjustable or Bandpass Equalizer A 'boost' equalizer can be made with the CLC428 CLC428 by summing a bandpass response with the input signal, as shown in Figure 9. (6) Select R2 and C using Eq. 6. Use reasonable values for high frequency circuits - R2 between 10 and 5k, C between 10pF and 2000pF. Use Eq. 7 to determine the parallel combination of Ra and Rb. Select Ra and Rb by either the 10 to 5k criteria or by other requirements based on the impedance Vin is capable of driving. Finish the design by determining the value of K from Eq. 8. (7) Figure 10 shows an example of the response of the circuit of Figure 9, where fo is 2.3MHz. The component values are as follows: Ra =2.1K, R2 = 68.5, R2 = 4.22k, R = 500, KR = 50, C = 120pF. DS012710-38 DS012710-38 FIGURE 9. The overall transfer function is shown in Eq. 5. (5) DS012710-43 DS012710-43 FIGURE 10. www.national.com 10 CLC428 CLC428 Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin SOIC NS Package Number M08A 8-Pin MDIP NS Package Number N08E 11 www.national.com CLC428 CLC428 Dual Wideband, Low Noise, Voltage Feedback Op Amp Notes LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Email: email@example.com www.national.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: firstname.lastname@example.org Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: email@example.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.