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Part : CLB-033-27ENN-W-A/03 Supplier : Carling Technologies Manufacturer : Avnet Stock : - Best Price : $2.4169 Price Each : $4.4737
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CLB-033-27ENN-W-A/03

Catalog Datasheet MFG & Type PDF Document Tags

RAM32M

Abstract: RAM64X1D function generator has the A inputs connected to a second read-only port address and the WA inputs shared , DI2 A[6:1] WA[6:1] CLK WE O6 DOD[0] O5 DOD[1] DPRAM32 C[5:1] 5 ADDRC[4:0] 5 DI1 DI2 A[6:1] WA[6:1] CLK WE O6 DOC[0] O5 DOC[1] DPRAM32 B[5:1] 5 ADDRB[4:0] 5 DI1 DI2 A[6:1] WA[6:1] CLK WE O6 DOB[0] O5 DOB[1] DPRAM32 A[5:1] 5 ADDRA[4:0] 5 DI1 DI2 A[6:1] WA[6:1] CLK WE O6 DOA[0] O5 DOA[1
Xilinx
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RAM32M RAM64X1D SRLC32E RAM128X1D RAM256X1S SRL32 UG364

virtex 6 XC6VSX475T

Abstract: XC6VLX75T function generator has the A inputs connected to a second read-only port address and the WA inputs shared , DI2 A[6:1] WA[6:1] CLK WE O6 DOD[0] O5 DOD[1] DPRAM32 C[5:1] 5 ADDRC[4:0] 5 DI1 DI2 A[6:1] WA[6:1] CLK WE O6 DOC[0] O5 DOC[1] DPRAM32 B[5:1] 5 ADDRB[4:0] 5 DI1 DI2 A[6:1] WA[6:1] CLK WE O6 DOB[0] O5 DOB[1] DPRAM32 A[5:1] 5 ADDRA[4:0] 5 DI1 DI2 A[6:1] WA[6:1] CLK WE O6 DOA[0] O5 DOA[1
Xilinx
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virtex 6 XC6VSX475T XC6VLX75T shift register by using D flip-flop XC6VLX195T XC6VLX365T XC6VSX475T

SRLC32E

Abstract: SRL32 read-only port address and the WA inputs shared with the first read/write port address. Spartan-6 FPGA , ) WCLK WED DPRAM32 DI1 DI2 A[6:1] WA[6:1] CLK WE O6 DOD[0] O5 DOD[1] DPRAM32 C[5:1] 5 ADDRC[4:0] 5 DI1 DI2 A[6:1] WA[6:1] CLK WE O6 DOC[0] O5 DOC[1] DPRAM32 B[5:1] 5 ADDRB[4:0] 5 DI1 DI2 A[6:1] WA[6:1] CLK WE O6 DOB[0] O5 DOB[1] DPRAM32 A[5:1] 5 ADDRA[4:0] 5 DI1 DI2 A[6:1] WA[6:1] CLK WE O6 DOA[0
Xilinx
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UG384 CQ 346 xc6slx75 spartan-6 XC6SLX45 cq 443 DSP48A1

ug384

Abstract: CQ 346 connected to a second read-only port address and the WA inputs shared with the first read/write port , ] ADDRD[4:0] 5 (CLK) (WE) WCLK WED DPRAM32 DI1 DI2 A[6:1] WA[6:1] CLK WE O6 DOD[0] O5 DOD[1] DPRAM32 C[5:1] 5 ADDRC[4:0] 5 DI1 DI2 A[6:1] WA[6:1] CLK WE O6 DOC[0] O5 DOC[1] DPRAM32 B[5:1] 5 ADDRB[4:0] 5 DI1 DI2 A[6:1] WA[6:1 , ] WA[6:1] CLK WE O6 DOA[0] O5 DOA[1] ug384_07_042309 Figure 8: Spartan-6 FPGA
Xilinx
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vhdl code for spartan 6 ternary content addressable memory VHDL SPARTAN 6 structure of clb xc6slx45t SPARTAN 6 xc6slx45 pin configuration
Abstract: voltage 2.0 V|L T,N Low-level input voltage -0.3 Vcc + 0.8 V 250 ns Input , Operating Conditions, all delay parameters increase by 0.3% per aC. 2. Although the present (1996) devices , 0.29 ns (-2). ms 4-368 1 1 4 1 7 5 1 0DD7fl71 ED-5 June 1,1996 (Version 1.0) K X IL IN X -
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XC3100L XC4000 XC3100A XC3000A XC3000L XC3000
Abstract: HG62S Series High-Speed CMOS Gate Array 0 H IT A C H I* Features Description The HG62S series free-channel gate arrays utilize a 0.8-/un CMOS process with triple metal intercon­ nect technology. The series consists of 6 master slices ranging from 26,054 to 250,000 raw gates. The internal gate delay is as low as 0.3 ns/gate for ultrahigh-speed operation. The macrocells are functionally , : fanout; Al: line length): â'" Internal (2-input power NAND, FO = 2, Al = 2 mm): 0.3 ns typ â'" Input -
OCR Scan
HG62E/F HG62S125 HG62S250 HG62S058 HG62S079 HG62S026
Abstract: . . . . . . . . . . . . . . . . . . . . . . . . 11 Write Enable (WA and WB) . . . . . . . . . . . . , RBA1 8-Gbit EA2 2nd RBA2 8-Gbit ALA, CLA, RA WPA, WA EA3 3rd I/OA0-I/OA7 8 , EA3 EA4 RA WA ALA CLA WPA EB1 EB2 EB3 EB4 RB WB ALB CLB WPB I/OA0 - I/OA7 RBA1 RBA2 RBA3 RBA4 64 , RA WA WPA RBA1 to RBA4 I/OB0 - I/OB7 CLB ALB EB1 to EB4 RB WB WPB RBB1 to RBB4 VDD VSS NC DU , EB3 VDD VSS EB2 EB4 RA WA WPA VSS RBA2 ALA CLA I/OA3 I/OA2 RBA3 I/OA1 I/OA0 A RBA4 B C NC D E F G H Numonyx
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NAND64GW3FGA

transistor tt 2222

Abstract: equivalent for transistor tt 2222 name of the form RAM16_S[wA]_S[wB] calls out the dual-port primitive, where the integers wA and wB specify the total data path width at ports wA and wB, respectively. Thus, a RAM16_S9_S18 is a dual-port , Block RAM Port Signal Definitions Representations of the dual-port primitive RAM16_S[wA]_S[wB] and , -3 FPGA Family: Functional Description RAM16_wA_wB WEA ENA SSRA CLKA ADDRA[rA­1:0] DIA[wA­1:0] DIPA[3:0] DOPA[pA­1:0] DOA[wA­1:0] WEB ENB SSRB CLKB ADDRB[rB­1:0] DIB[wB­1:0] DIPB[3:0
Xilinx
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DS099-2 transistor tt 2222 equivalent for transistor tt 2222 TT 2222 Horizontal Output Transistor pins out tt 2222 Datasheet W10B TT 2222 XC3S50 DS099-1 DS099-3 DS099-4
Abstract: (WA and WB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.7 Write , VDD EA1 1st RBA1 8-Gbit EA2 2nd RBA2 8-Gbit ALA, CLA, RA WPA, WA I/OA0-I , . Description Logic diagram VDD EA1 EA2 EA3 I/OA0 - I/OA7 EA4 RA RBA1 WA ALA CLA WPA , Input RA Read Enable Input WA Write Enable Input WPA Write Protect Input , EB2 WB D E VSS VSS WPB VDD NC CLA WA B C RBA3 WPA VDD CLB A Numonyx
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NAND64GW3FGA

Abstract: NUMonyx NAND64G . . . . . . . . . . . . . . . . . . . . . . . . 11 Write Enable (WA and WB) . . . . . . . . . . . . , RBA1 8-Gbit EA2 2nd RBA2 8-Gbit ALA, CLA, RA WPA, WA EA3 3rd I/OA0-I/OA7 8 , EA3 EA4 RA WA ALA CLA WPA EB1 EB2 EB3 EB4 RB WB ALB CLB WPB I/OA0 - I/OA7 RBA1 RBA2 RBA3 RBA4 64 , RA WA WPA RBA1 to RBA4 I/OB0 - I/OB7 CLB ALB EB1 to EB4 RB WB WPB RBB1 to RBB4 VDD VSS NC DU , EB3 VDD VSS EB2 EB4 RA WA WPA VSS RBA2 ALA CLA I/OA3 I/OA2 RBA3 I/OA1 I/OA0 A RBA4 B C NC D E F G H
Numonyx
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NUMonyx NAND64G 64Gbit NAND64G

am2064

Abstract: 4558 pin configuration *®T 1 tí U92 A D E-206-009A HG62G Series High-Speed CMOS Gate Array HITACHI Description The HG62G series free-channel gate arrays are fabricated with 0.8 |am CMOS process and double metal interconnect technology. The HG62G series consists of 4 master slices ranging from 14,540 to 34,797 raw gates with high I/O pin counts. Internal gate delay time is as low as 0.3 ns per gate and , ). 0.3 ns typ. â'" Input buffer (FO = 2, A1 = 2 m m ).0.8 ns typ. â'" Output
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OCR Scan
am2064 4558 pin configuration AM2018 burndy qile68p-410t surround circuit using ic 4558 pin diagram burndy ms 2064/A AW-WCP-10M-5/89-0P

HG62G

Abstract: HG62G027 RCLK A15 A14 ] A13 ALL A12 > OTHER PINS A11 J LCA A10 RESET A9 D7 AS D6 A7 D5 A6 D4 A5 03
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OCR Scan
HG62G027 HG62G019 KZL 99 DE-206-009A

am2064

Abstract: XC2064 RECEPTACLE [ CIRCUIT NUMBERS (£_ . MOL EX 1625 J (4.8) [Hi .78 ( 19.7) B MOUNTING EARS (WHEN SPECIFIED) SEE DETAIL A OR B _ .20 (5.0) â 78 ( 19.8) H RECEPTACLE HOUSING SHOWN WITH STANDARD EARS 1625 I PLUG I, CIRCUIT NUMBERS 1 I I udl~ s-: i Cl.B) n â  76 (19.8) r" If v MOUNTING EARS (WHEN SPECIFIED) SEE DETAIL A OR B n) _ .89_ (22.6) Tfifl _ (T.8) _ .20 (5.0) .75 (19.1) rWrUSrnn (3.68)' PLUG HOUSING SHOWN WITH STANDARD EARS N (METRIC) INCH UM.ESS 0THERII1SE SPECIFIED TOLERANCES: ANGULAR i VBS
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OCR Scan
XC2064 burndy 44-PIN 48-PIN 68-PIN 84-PIN
Abstract: Restrictions section. 05,03,01,FF ; C2, (C0+C2), (C1+C2), (C0+C1+C2) FB,F9,F7,F5 ; C3, (C0+C3), (C1+C3 , representation or wa r- versions of this application note, or if you have que sranty regarding this design or -
OCR Scan
U8I88 SD-1625-5- 16255X1 I625-5P I625-5R I625-5PI

implementation of 16-tap fir filter using fpga

Abstract: FIR FILTER implementation xilinx TA = 25 VOD1, VOD2 ­0.3 +15 V V 1, V 2 ­0.3 +8 V V 1L, V 2L ­0.3 +8 V V R ­0.3 +8 V V CLB ­0.3 +8 V dpi V SEL ­0.3 +8 V V TG1-V TG3 ­0.3 +8 V TA 0 +55 Tstg ­40 , ) 44.0±0.3 9.25±0.3 12 22 1 0.4 ±0.3 1st valid pixel 11 1 2.0 37.5 4 4 0.46±0.1
Xilinx
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implementation of 16-tap fir filter using fpga FIR FILTER implementation xilinx circuit diagram of half adder XC4003PC84 fir filter applications FIR FILTER xilinx XC4000-4

NEC CCD MFP

Abstract: ic 6264 VOD1, VOD2 -0.3 +15 V V 1, V 2 -0.3 +8 V V 1L, V 2L -0.3 +8 V V R -0.3 +8 V V CLB -0.3 +8 V V SEL1, V SEL2 -0.3 +8 V V TG -0.3 +8 V TA 0 +55 Tstg -40 +70 1 , MIN. 2.5 3.0 - V lx·s SE_R - 0.3 - SE_G - 0.33 - lx·s
NEC
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NEC CCD MFP ic 6264 s187 V100 PD8874 PD8873 PD8874CY-A DIP10 S18773JJ1V0DS00 S10800

NEC CMOS GATE d65

Abstract: "Analog Shift Register" 03 C3 Notes: Unprogrammed !OBs have a default pull-up. This prevents an undefined pad level for , â'" B3 1 A RESET^ C11 1.3 kQ â'" W-â'" QÚuL II I IL r %1 k a à 1.3kÂ
NEC
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PD8875 NEC CMOS GATE d65 nec Rgb ccd sensor D17-D19 NEC T6 PD8875CY-A 400RGB S18949JJ1V0DS00 S10799 22C-1CCD-PKG20
Abstract: 00 00 00 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 330 A22 E00 B10 111 60E , following software is required to process this d esign: LD sF, 03 ;return flag JP sub_routine , . Xilinx, Inc. does not make any representation or wa rranty regarding this design or any item based on this design. Xilinx disclaims all express and implied wa rranties, including but not limited to the -
OCR Scan
ATT3000 ATT3042132-P ATT3090 164-P ATT3090175-P

XC4005PC84C

Abstract: XC4000 4.7 5.0 5.5 V V 1L, V 2L, V 3L, V 4L -0.3 0 0.3 V V RBH 4.5 5.0 5.5 V V RBL -0.3 0 0.5 V V CLBH 4. 5 5.0 5.5 V V CLBL -0.3 0 0.5 V Dpi V SELH 4.5 5.0 5.5 V Dpi V SELL -0.3 0 0.5 V V TG1H-V TG3H 4.5 5.0 5.5 V V TG1L-V TG3L -0.3 0
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XC4005PC84C XC4005PC84
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