CLA70000 DS2462 CLA60000 CLA71000 CLA72000 CLA73000 CLA74000 CLA75000 CLA76000 - Datasheet Archive

 

High Density CMOS Gate Arrays DS2462 Recent advances in CMOS processing technology and improvements in design architecture have

 

CLA70000 CLA70000 Series High Density CMOS Gate Arrays DS2462 DS2462 Recent advances in CMOS processing technology and improvements in design architecture have led to the development of a new generation of array-based ASIC products with vastly improved gate integration densities. This family of CLA70000 CLA70000 1 micron CMOS arrays brings considerable advantages to the design of next generation systems combining high performance and high complexity. Features · · · · · · · · · · Low power channelless arrays from 5,000 to 250,000 available gates (5µW / gate / MHz) 1 micron (0.8 micron effective) twin well epitaxial process Typical gate delays of 400 ps (NAND2 , Fanout=2) Comprehensive cell library including DSP, JTAG/BIST and compiled memory cells (ROM blocks to 64K bits and RAM blocks to 16K bits) Extensive Range of Plastic and Ceramic Packages for both Surface Mount and Through Board Assembly Flexible I/O structure allows user to define power pad locations Fully supported on industry standard workstations and in-house software High drive output stages with slew rate control Supports JTAG and BIST test philosophies (IEEE 1149-1 Test Procedures) MIL 883C compliant product available (paragraph 1.2.1) ISSUE 3.1 March 1992 Overview The CLA70000 CLA70000 gate array family is Zarlink Semiconductors' sixth generation CMOS gate array product. The family consists of nine arrays implemented on the latest generation (1 micron) twin well epitaxial CMOS process. The process in conjunction with the advanced layout and route software, offers extremely high packing densities. The array architecture is based upon the earlier well proven CLA60000 CLA60000 series with the emphasis being placed on high speed, high packing density, and provision of comprehensive cell libraries. The cell libraries encompass new DSP and other specialized macros. Full design support is available for major industry standard ASIC design software tools, as well as Zarlink Semiconductor's proprietary PDS2 design environment. Design support is provided by Zarlink Semiconductor's design centers, each offering a variety of design routes, which may be customized to individual customer requirements. Product Details The CLA70000 CLA70000 array series is shown below with typical figures given for usable gates. Actual gate utilization is dependent on circuit structure, giving a range of 40 -70% for two layer metallisation. DEVICE NUMBER I/O AND POWER PADS GATE COMPLEXITY ESTIMATED USABLE GATES CLA70000 CLA70000 CLA71000 CLA71000 CLA72000 CLA72000 CLA73000 CLA73000 CLA74000 CLA74000 CLA75000 CLA75000 CLA76000 CLA76000 CLA77000 CLA77000 CLA78000 CLA78000 44 68 84 100 120 160 200 256 304 5K 12K 19K 27K 39K 70K 110K 182K 256K 2.5K 6K 9.5K 13.5K 17.5K 31.5K 49.5K 82K 115K CLA70000 CLA70000 Series Core Cell Arrangement · Supports compact macros · Allows high density routing VSS VDD Supply Supply A four transistor group (2 NMOS and 2 PMOS) (fig.1) forms the basic cell of the core array. This array element is repeated in a regular fashion over the complete core area to give an homogenous `Full Field' (sea of gates) array. This lends itself to hierarchical design, allowing pre-routed user defined subcircuits to be repeated anywhere on the array. The core cell structure together with all associated cell libraries have been carefully designed to maximize the number of nets which may be routed through the cell. This enables optimal routing of both data flow and control signal distribution schemes thus giving very high overall utilization factors. This feature is of particular benefit in designs using highly structured blocks such as memory or arithmetic functions. Programmable contacts VSS VSS Supply Supply I/O Buffer Arrangement · · Programmable Slew rate Control on all Outputs · Figure 1 - Diagrammatic representation of Array Core Cell Several hundred different I/O cell combinations Excellent Latchup and ESD immunity The I/O buffers are the interface to external circuitry and are therefore required to be robust and flexible. Both inputs and outputs incorporate electrostatic discharge (ESD) protection structures which can withstand in excess of 2KV, and are highly resistant to latch-up due to the epitaxial process. In addition the construction concepts used for the I/O cells provide the designer with several hundred different options of I/O cell configuration. The CLA70000 CLA70000 I/O buffers (fig.2) contain all the components for static protection, CMOS and TTL compatible input stages, and a wide variety of intermediate and output drive configurations. Included are Schmitt triggers, tristate controls, and slew rate controlled output buffers. All I/O buffer locations can be configured as supply pads (VDD and VSS). Slew rate control of output drivers is a useful feature when multiple high drive outputs need to be switched simultaneously, as may occur on driving capacitive loads such as buses. Using regular output buffers with their inherently fast edge speed can lead to significant power supply noise transients, with possible mis-operation as a result. To overcome this problem. The CLA70000 CLA70000 family includes a set of slew rate controlled output drivers, which use proprietary design techniques to control the turn-on of the output transistors (di/dt). These cells provide a significant benefit in the trade off between switching current magnitude and the number of supply pads required. SLEW RATE CONTROL I/O BLOCK IB1 IB2 IB3 IB4 IB5 INPUT DATA D slew rate controlled driver P N P OPT3 N PIN OP1 OP2 IP 50 pF 2.5 Volts 2.5 Volts IBSK1, IBSK2 and IBSK3 have been characterised to give the correct timing when connected to the OPT* cells. Fig 2. Slew Control & I/O Block 2 Bonding Pad I/O BLOCK CLA70000 CLA70000 Series Power Supply Distribution · Three power rings for good noise immunity · Optimized for efficient routing · User defined placement of Power and Ground pads Supply to Core Logic The power supply distribution scheme for the CLA70000 CLA70000 arrays (fig.3) has the flexibility to meet varying applications needs. Three separate power rings are used, one each for the internal core logic, intermediate buffer cells, and large output driver cells. Noise generated in the low impedance output drivers is isolated from the core logic and buffer areas. The distribution of the supply rails can be automatically positioned by the layout software which allows greater design flexibility and optimisation. The power supply rings may be connected either to separate pad locations or combined at a single location. All I/O cell pads may be configured as either power or ground, giving complete flexibility to the designer. Process Technology · Advanced 1 micron twin well process with epitaxial substrate · Class 10 six inch wafer fabrication facility · High density low power process Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Output Voltage ESD protection Current per pad Storage Temperature Ceramic Plastic Min -0.5 -0.5 -0.5 2.0 Max 7.0 Vdd + 0.5 Vdd + 0.5 100 -65 -40 150 125 VSS } Supply to VDD } Intermediate Buffers VDD } Supply to VSS } I/O Buffers Figure 3 - Power Supply Organisation The CLA70000 CLA70000 arrays are built using the Zarlink Semiconductor 1 micron drawn CMOS process, which is the third generation of our `V' series process family. Manufacture is at Class10, 6-inch fabrication facility. The process is a twin well, self aligned oxide-isolated technology on an epitaxial substrate, with an effective channel length of 0.8 micron, giving low defect density, high reliability, and inherently low power dissipation. The process has excellent immunity to latchup, and ESD, and exhibits stable performance characteristics ideal for all commercial, industrial and military applications. Recommended Maximum Operating Limits Units V V V K Volts mA °C °C Operation outside these absolute maximum ratings may permanently damage device characteristics and may affect Parameter Supply Voltage Input Voltage Output Voltage Operating Temperature Commercial Grade Industrial Grade Military Grade Min Max Units 3.0 Vss Vss 5.5 Vdd Vdd V V V 0 -40 -55 70 85* 125* °C °C °C * 125°C maximum junction temperature for plastic devices. *Subject to a maximum junction temperature of 150°C for ceramic devices. 3 CLA70000 CLA70000 Series Manufacturing Facilty Cell Library · Computer aided manufacturing · Comprehensive range of cells · Digital testers with large pinout capacity · Specialized DSP and BIST sub-libraries · Vibration free for reliable manufacture · Compatible with Megacell and CLA60000 CLA60000 The CLA70000 CLA70000 product is manufactured near Plymouth, England in the latest purpose built facility for sub-micron process geometries. The factory uses the latest automated equipment for 6 inch wafers and Computer Aided Manufacturing techniques to ensure production efficiency. Wafer fabrication is carried out in Class 10, or better, clean room conditions in a vibration free environment to assure the lowest possible defect level. In addition to the world class wafer facility there are excellent probe and final test areas equipped with the latest analog and digital testers capable of handling complex test vectors and large pinouts. This large investment shows Zarlink Semiconductors' commitment to all the market areas needing state-of-the-art CMOS ASICS. Cell Library Logic Array Cells BUF ST1 DELAY Buffer driver Schmitt trigger Delay cell 2INV INV2 INV4 INV8 Dual driver Inverter, dual drive Inverter, quad drive Inverter, octal drive NAND2 ND3 NAND3 2NAND3 NAND4 NAND5 NAND6 NAND8 2 input NAND gate 3 input NAND gate 3 input NAND gate + inverter Dual 3 input NAND gate 4 input NAND gate 5 input NAND gate 6 input NAND gate 8 input NAND gate NOR2 NR3 NOR3 2NOR3 NOR4 NOR5 NOR6 NOR8 2 input NOR gate 3 input NOR gate 3 input NOR gate + inverter Dual 3 input NOR gate 4 input NOR gate 5 input NOR gate 6 input NOR gate 8 input NOR gate A2O21 A2O21 O2A21 O2A21 2A2O21 2A2O21 2O2A21 2O2A21 2ANOR 2ONAND 2 input AND to 2 input NOR gate + inverter 2 input OR to 2 input NAND gate + inverter Dual 2 input AND to 2 input NOR gate Dual 2 input OR to 2 input NAND gate 2 input ANDs to 2 input NOR gate 2 input ORs to 2 input NAND gate 4 A very comprehensive cell library is available for the CLA70000 CLA70000 series. It contains sub libraries which may be used in specific applications areas such as Digital Signal Processing (DSP) and Built In Self Test (BIST). More details on these specialized libraries can be found in applications notes or the design manual. The 1.4 micron (drawn) CMOS array (CLA60000 CLA60000) cell library may be converted to the equivalent cells on the CLA70000 CLA70000 to allow system upgrades. Equivalent cells are also available for the corresponding MVA70000 MVA70000 Megacell to enable an easy transition to a standard cell product to minimize silicon area or to add analog functions. A2O31 A2O31 O2A31 O2A31 A3O21 A3O21 O3A21 O3A21 A4O21 A4O21 O4A21 O4A21 A2041 A2041 O2A41 O2A41 3A2O31 3A2O31 3O2A31 3O2A31 O2A2O21 O2A2O21 A2O2A21 A2O2A21 2 input AND to 3 input NOR gate 2 input OR to 3 NAND gate 3 input AND to 2 input NOR gate 3 input OR to 2 input NAND gate 4-input ANDs to 2 input NOR gate 4-input ORs to 2 input NAND gate 2-input AND to 4 input NOR gate 2-input ORs to 4 input NAND gate 3 2-input ANDs to 3 input NOR gate 3 2-input ORs to 3 input NAND gate 2 input OR to 2 input AND to 2 input NOR gate 2 input AND to 2 input OR to 2 input NAND gate EXOR EXNOR EXOR2 EXNOR2 EX2 EXN2 EXOR3 EXNOR3 EXPRIM Exclusive OR gate + NAND gate + inverter Exclusive NOR gate + NOR gate + inverter 2 input exclusive OR gate 2 input exclusive NOR gate Exclusive OR gate + inverter Exclusive NOR gate + inverter 3 input exclusive OR gate 3 input exclusive NOR gate 2 input exclusive OR gate primitive HADD SUM SUM2 CARRY CARRY2 FADD BMF1 BMF2 Half adder + inverter Sum block Sum block Carry block + NOR gate Carry block + inverter Full adder + NOR gate Full adder 1 Full adder 2 MUX2TO1 MUX4TO1 MUX8TO1 MUXI2TO1 2 to 1 multiplexer 4 to 1 multiplexer 8 to 1 multiplexer 2 to 1 inverting multiplexer CLA70000 CLA70000 Series MUXI4TO1 MUXI8TO 1 4 to 1 inverting multiplexer 8 to 1 inverting multiplexer CLKA 2CLKA CLKAP CLKAM CLKB CLKBP CLKE1 CLKE2 CLKE3 Basic clock driver Dual basic clock driver Basic clock driver + inverter Basic clock driver + inverter Large clock driver + inverter Large clock driver + inverter Clock driver with enable Clock driver with enable Clock driver with enable TM 2TM BDR Buffered transmission gate Transmission gate for 2 to 1 multiplexing Internal bus driver DL DL2 DLRS DLARS DF DFRS MDF MDFRS Data latch Data latch Data latch with set and reset Data latch with set and reset Master-slave D type flip flop Master-slave D type flip flop with set & reset Multiplexed master-slave D type flip flop Multiplexed master-slave D type flip flop with set & reset Multiplexed m/s D type flip flop Multiplexed m/s D type flip flop with set & reset IBGATE IBCLKB IBDF IBDFA IBSK1 IBSK2 IBSK3 IBTRID IBTRID1 IB2BD NAND2/NOR2 gates Large clock driver Master-slave D type flip flop Master-slave D type flip flop Driver with slewed outputs Driver with slewed outputs Driver with slewed outputs Tri-state driver Tri-state driver with slewed outputs + 2 inverters Tri-state driver with slewed outputs + 2 inverters Tri-state driver with slewed outputs + 2 inverters Dual high powered inverters DRV3 DRV6 Clock driver Clock driver IBTRID2 IBTRID3 M3DF M3DF JK JKRS JBARK JBARKRS J-K flip-flop J-K flip-flop with set & reset JBAR-K flip-flop JBAR-K flip-flop with set & reset BDL BDLRS JBARKRS BDF BDFRS Buffered data latch Buffered data latch with set & reset Buffered data latch with set & reset Buffered master-slave D type flip-flop Buffered master-slave D type flip-flop with set & reset BMDF Buffered mux. master-slave D type flip-flop BMDFRS Buffered mux. m/s D type with set & reset BJBARK Buffered J-K flip-flop BJBARKRS Buffered J-K flip-flop with set & reset TRID Tristate driver GND VDD Ground Cell VDD Cell Intermediate Buffer Cells IBCCMOS1 IBCCMOS2 IBTTL1 IBBTL2 IBST1 IBST2 CMOS input buffer + large 2 input NAND gate CMOS input buffer + data latch TTL input buffer + large 2 input NAND gate TTL input buffer + data latch Input Schmitt buffer with CMOS switching levels Input Schmitt buffer with 2V switching levels Pad Input Cells IPNR IPR1P IPR1M IPR2P IPR2M IPR3P IPR3M IPR4P IPR4M Input cell with no pull up or down resistors Input cell with 1KOhm pull up resistor Input cell with 1KOhm pull down resistor Input cell with 2KOhm pull up resistor Input cell with 2KOhm pull down resistor Input cell with 4KOhm pull up resistor Input cell with 4KOhm pull down resistor Input cell with 75KOhm pull up resistor Input cell with 75kOhm pull down resistor Oscillator Cells (crystal) to be defined Pad Output Cells OP1 OP2 OP3 OP6 OP12 Smallest drive output cell Small drive output cell Standard drive output cell Medium drive output cell Large drive output cell OP5B OP11B OP11B Standard drive non-inverting output cell Large drive non-inverting output cell OPT1 OPT2 OPT3 OPT6 OPT12 OPT12 Smallest drive tri-state output cell Small drive tri-state output cell Standard drive tri-state output cell Medium drive tri-state output cell Large drive tri-state output cell OP4B OP10B OP10B Standard drive non-inverting tri-state output cell Large drive non-inverting tri-state output cell OPOD1 OPOD2 OPOD3 OPOD6 OPOD12 OPOD12 Smallest drive open-drain output cell Small drive open-drain output cell Standard drive open-drain output cell Medium drive open-drain output cell Large drive open-drain output cell 5 CLA70000 CLA70000 Series Test Control Cells OPOD11B OPOD11B Standard drive non-inverting open-drain output cell Large drive non-inverting open-drain output cell OPOS1 OPOS2 OPOS3 OPOS6 OPOS12 OPOS12 Smallest drive open-source output cell Small drive open-source output cell Standard drive open-source output cell Medium drive open-source output cell Large drive open-source output cell OPOS5B Standard drive non-inverting open-source output cell Large drive non-inverting open-source output cell JTAP PDS BIST JTAG Interface Controller JTCLK PDS-BIST Clock Gating and Buffer Cell JTIDREG OPOD5B PDS-BIST JTAG Identification Register Test Register Component Cells JTDUT Test register data bit (transparent) with update latch JTDUF Test register data bit (transparent)] with update latch JTDDT Test register data bit (transparent) Power Supply Cells JTDDF Test register data bit (transparent) OPVP OPVM OPVPB OPVMB OPVPBB JTCUT Test register data bit (clocked) with update latch JTCUF Test register data bit (clocked) with update latch JTCDT Test register data bit (clocked) JTCDF Test register data bit (clocked) JTCT Test register local controller JTBF16 JTBF16 Test register driver 4-19 databits JTBF16 JTBF16 Test register driver 20-34 databits OPOS11B OPOS11B OPVMBB IBVP IBVM IBVPB IBVMB IBVPBB IBVMBB LAVP LAVM LAGND LAVDD VDD power pad (outputs) GND power pad (outputs) VDD power pad (outputs) : break in VDD GND power pad (outputs) : break in GND VDD power pad (outputs) : break in VDD & GND GND power pad (outputs) : break in VDD & GND VDD power pad (buffers) GND power pad (buffers) VDD power pad (buffers) : break in VDD GND power pad (buffers) : break in GND VDD power pad (buffers) : break in VDD & GND GND power pad (buffers) : break in VDD & GND Power pad for logic array | | | CLA70000 CLA70000 PDS-BIST (JTAG/IEEE1149-1 JTAG/IEEE1149-1) Library Test Register Cells JTRDU4,8,16,24,32 4,8,16,24,32 bit Transparent Test registers with Update Latches JTRDD4,8,16,24,32 4,8,16,24,32 bit Transparent Test registers JTRCU4,8,16,24,32 4,8,16,24,32 bit Clocked Test registers with Update Latches JTRCD4,8,16,24,32 4,8,16,24,32 bit Clocked Test Registers CLA70000 CLA70000 DSP Macrocell Library Ripple Carry Adders ADR1 ADR3 ADR8 ADR16 ADR16 ADR24 ADR24 ADR32 ADR32 High Speed Carry Select Adders ADS1 ADS3 ADS8 ADS16 ADS16 ADS24 ADS24 ADS32 ADS32 1bit adder 4 bit adder 8 bit adder 16 bit adder 24 bit adder 32 bit adder Carry Select Adders (Reduced Area) ADT8 ADT16 ADT16 ADT24 ADT24 6 1bit adder 4 bit adder 8 bit adder 16 bit adder 24 bit adder 32 bit adder 8 bit adder 16 bit adder 24 bit adder CLA70000 CLA70000 Series ADT32 ADT32 32 bit adder Subtractor Blocks BMB16X12 BMB16X12 Single pipeline multiplier (16 x 12 bits) ADSU4 ADSU8 ADSU16 ADSU16 ADSU24 ADSU24 ADSU32 ADSU32 BMC24X24 BMC24X24 Mixed mode multiplier (24 x 24 bits) BTHE1 BTHD1 BTHD2 Booth encoder Non-Inverting Booth decoder Inverting Booth decoder 4 bit subtractor add-on 8 bit subtractor add-on 16 bit subtractor add-on 24 bit subtractor add-on 32 bit subtractor add-on Shifters Arithmetic Right (Padded with MSB) SHA4 SHA8 SHA16 SHA16 SHA24 SHA24 SHA32 SHA32 4 stage arithmetic right shifter 8 stage arithmetic right shifter 16 stage arithmetic right shifter 24 stage arithmetic right shifter 31 stage arithmetic right shifter Many of the macro functions perform similar functions to the standard TTL and CMOS logic families. The user is warned, however, that the logic functions may differ slightly and is therefore recommended to refer to the design manual rather than assume an exact functional copy. The PDS simulator uses the constituent microcell models for circuit analysis. The macrocells are constructed from basic microcells and are placed and routed to give optimum use of chip area. Shifters Barrel Right (Padded with LSB Data Exiting Shifter) SHB4 SHB8 SHB16 SHB16 SHB24 SHB24 SHB32 SHB32 4 stage barrel right shifter 8 stage barrel right shifter 16 stage barrel right shifter 24 stage barrel right shifter 31 stage barrel right shifter MACRO FUNCTION Adders ADA4 ADG4 4 bit binary full adders with fast carry Look ahead carry generator Counters Shifters Logic Right/Left (Padded with Zero's) SHL4 SHL8 SHL16 SHL16 SHL24 SHL24 SHL32 SHL32 4 stage logic right shifter 8 stage logic right shifter 16 stage logic right shifter 24 stage logic right shifter 31 stage logic right shifter Logic Units (8 Function) FGLO4 FGLO8 FGLO16 FGLO16 FGLO24 FGLO24 FGLO32 FGLO32 4 logic bit unit 8 logic bit unit 16 logic bit unit 24 logic bit unit 32 logic bit unit Arithmetic Units (8 Function) FGAR4 FGAR8 FGAR16 FGAR16 FGAR24 FGAR24 FGAR32 FGAR32 4 bit logic unit 8 bit logic unit 16 bit logic unit 24 bit logic unit 32 bit logic unit CLA70000 CLA70000 DSP Macrocell Library Multiplers and Associated Cells BMA8X8 BMA16X16 BMA16X16 BMA24X24 BMA24X24 CNA4 CNB4 CNC4 CND4 CND4A CNE4 CNF4 CNG4 BCD counter/4 bit latch decoder/driver 4 bit counter latch 4 bit synchronous counter 4 bit binary up/down Synchronous counter 4 bit binary up/down counter with reset 4 bit decade counter 4 bit binary synchronous counter 4 bit binary counter Decoders DRA3T8 DRA4T16 DRA4T16 DRA4T16A DRA4T16A DRB3T8 DRB3T8 DRD2T4 DRF4T10 DRF4T10 DRG4T10 DRG4T10 DRH4T10 DRH4T10 DRI10 DRI10 DRJ7 DRK7 DRL7 3 line to 8 line decoder/demultiplexer 4 line to 16 line decoder/demultiplexer 4 line to 16 line decoder/demultiplexer no enable 3 line to 8 line decoder/demultiplexer with address registers 3 line to 8 line decoder/demultiplexer with address latches 2 line to line decoder 4 line to 10 line BCD decoder 4 line to 10 line excess 3 to decimal decoder 4 line to 10 line excess gray to decimal decoder decoder BCD to decimal decoder/driver BCD to 7 segment decoder/driver BCD to 7 segment decoder/driver BCD to 7 segment decoder/driver Mixed mode multiplier (8 x 8 bits) Mixed mode multiplier (16 x 16 bits) Mixed mode multiplier (32 x 32 bits) 7 CLA70000 CLA70000 Series Encoders ENA8T3 ENB10T4 ENB10T4 8 line to 3 line priority encoder 10 line to 4 line priority encode SRB8A SRC8 SRD4 SRE4 2 bit PISO shift register without clear 8 bit PISO shift register with clear 8 bit SIPO shift register with clear 4 bit PIPO shift register with JKbar input 8 bit shift and store register with tristate outputs 4 bit bidirectional universal shift register 4 bit parallel access shift register 5 bit shift register SRF8 Flip-Flop FFA8 FFB6 FFC4 FFD8 SRG4 8 bit bistable latches 6 bit D-type flip-flop with clear 4 bit D-type flip-flop with clear & complimentary outputs Octal D-type flip-flop with clear SRJ4 SRK5 Process Monitor ALU/Functional Generator PERF FGA5 4 bit ALU/function generator BIST * 4 bit magnitude comparators RGBIT RGTBIT RGDIAG RGCTL RGHOLD MLA10 MLA10 Decade rate multiplier * (early built in self test cells) see CLA7BIST Library MLB4X4 4 by 4 binary multiplier with tristate outputs CLA70000 CLA70000 Paracell Library 7 bit Wallace trees with tristate outputs Memory Cells Adders MCA4 Multiplers MLW7 RBRAM Multiplexors MXA8T1 MXB4T1 MXB4T1A MXC2T1 MXC2T1A MXD4T1 MXE4T1 MXF2T1 8 line to 1 line data selector / multiplexer Dual 4 line to 1 line data selector / multiplexers Dual 4 line to 1 line data selector / multiplexer with inverted tristate outputs Quad 2 to 1 data selector / multiplexers Quad 2 to 1 selector (inverted outputs) 4 to 1 multiplexor with strobe 4 to 1 multiplexor with strobe 2 to 1 multiplexeor with storage Parity Generator PGA9 9 bit odd/even parity generator/checker Shift Registers SRA2 SRA4 SRA8 SRA8A SRB2 SRB4 SRB8 8 2 bit POS shift register with clear 4 bit POS shift register with clear 8 bit SIPO shift register with clear 8 bit SIPO shift register without clear 2 bit PISO shift register with clear 4 bit PISO shift register with clear 2 bit PISO shift register with clear ROROM Performance monitor Test register (one bit) Test register (one monitor bit) Diagnostic control unit Test register controller Test register hold circuitry RAM MAX 16384 bits per block WORDS 2:128, bits 1:128 (min:max) ROM MAX 65536 bits per block WORDS 2:2048, bits 2:64 (min:max) CLA70000 CLA70000 Series Design Support and Interfaces · · Design center engineer assigned to every customer circuit To check and agree on all performance, packaging, specifications and design timescales. Flexible design route approach · Review 2: Full turnkey service capability Design and layout support for CLA70000 CLA70000 arrays is available from various centers worldwide each of which is connected to our Headquarters via high speed data links. A design center engineer is assigned to each customer's circuit, to ensure good communication , and a smooth and efficient design flow. It should be noted that sign-off simulation against the 'golden' simulator is also supported at our local design centers. Zarlink Semiconductor offers a variety of formal design routes as illustrated in the table below. Differing interface methods allow for varying levels of involvement in a manner which complements individual customer design styles, whilst maintaining our responsibility to ensure first time working devices. As part of the design process Zarlink Semiconductor operates a thorough design audit procedure to verify compliance with customer specification and to ensure manufacturability. The procedure includes four separate review meetings, with the customer, held at key stages of the design. Review 1: Held at the beginning of the design cycle Held after Logic Simulation but prior to Layout Checks to ensure satisfactory functionality, timing performance, and adequate fault coverage. Review 3: Held after Layout and Post Layout Simulation Verification of satisfactory design performance after insertion of actual track loads. Final check of all device specifications before prototype manufacture. Review 4: Held after Prototype Delivery Confirm that devices meet all specifications and are suitable for full scale production. Design Tools The focus of the Zarlink Semiconductor design tool methodology is that of maintaining an open CAD system with all interfaces standardized via EDIF 2.0 . This enables us to provide full support for a variety of 3rd party ASIC design tools and facilitates rapid updating of associated libraries. It also provides an interface to the Zarlink Semiconductor (PDS2) CAD SUPPORT Design Routes THIRD PARTY SOFTWARE PDS IN-HOUSE SOFTWARE TURNKEY SERVICE Schematic Capture CUSTOMER CUSTOMER GPS Logical Design CUSTOMER CUSTOMER GPS GPS CUSTOMER or GPS GPS GPS GPS GPS CUSTOMER CUSTOMER CUSTOMER GPS GPS GPS OPTIONS Design Review 1 Design Review 2 Physical Design Design Review 3 Prototype Manufacturing Prototype Evaluation Design Review 4 Production 9 CLA70000 CLA70000 Series design system, which offers a total design environment including behavioral and functional level modelling. Specifications Thermal Management Third Party Software Support · Lower power CMOS for better thermal management Design Kits for major industry standard ASIC design software tools · Improved reliability · All libraries include fully detailed timing information · Power packages available · EDIF 2.0 Interface · Post layout back annotation available The increase in speed and density available through CMOS process geometry reduction, results in a corresponding increase in power dissipation. SemiCustom designers now have the ability to design circuits of 100,000 gates and over, and chip power consumption is (or should be) a very important concern. · Zarlink Semiconductor supports a wide range of third party design tools including IKOS, Mentor, Verilog, and Viewlogic at the time of printing. Please check with our Sales Offices for the most recent additions. The design kits offer fully detailed timing information for all cell libraries, netlist extraction utilities, and post layout back annotation capability where applicable. An example of a workstation design flow is shown in fig 5 below. Please contact your local Zarlink Semiconductor's sales office for further information about support of particular tools. PDS ENVIRONMENT WORKSTATION ENVIRONMENT Schematic Symbols Schematic Capture CLA Libraries ERC & Netlist Translation Back Annotation Simulation Models Simulation Test Vector Generation MLE Place & Route To minimize this problem Zarlink Semiconductor's CLA70000 CLA70000 arrays offer low power factors and a selection of power packages. Dissipation of 5 µW per gate per Mhz gate power and 1µW per gate load, is lower than most competitive arrays, with the reduced junction temperatures having the added advantage of improved performance and reliability. CLA70000 CLA70000 POWER DISSIPATION CALCULATION Design Verification Vector Translation Test Program Generation Figure 5 - Workstation Design Flow PDS2 - The Zarlink Semiconductor ASIC Design System s Behavioral, Functional, and Gate Level Modelling s VHDL and Third Party Links s Supports Hierarchical Design Techniques s EDIF 2.0 Interface PDS2 is Zarlink Semiconductor's own proprietary ASIC design system. It provides a fully-integrated, technology independent VLSI design environment for all Zarlink Semiconductor CMOS SemiCustom products. PDS2 runs on Digital Equipment Computers and is self configuring according to the available machine resources. It comprises design capture (schematic capture or VHDL), testability analysis, logic simulation, fault simulation, auto place and route, and back annotation. The system offers full support for hierarchical design techniques, maintained from design capture through to layout, as well as advanced design management tools. PDS2 may be used either at a Zarlink Semiconductor Design Center or under licence at the customer's premises. A three day training course is available for first time users. 10 The logic core of 100K plus gates is the dominant factor in power dissipation at this complexity. It is essential to offer ultra low power core logic to maintain an acceptable overall chip power budget. CLA70000 CLA70000 series power dissipation for any array can be estimated by following the example (calculated for the CLA76XXX CLA76XXX) below. Number of available gates Assume percent gates used Number of used gates (110102 X 0.4) Assume 15% of gates switching during. each clock cycle (44045 X 0.15) Power dissipation/gate/Mhz (gate fanout typically 2 loads) 110112 40% 44045 Total core dissipation/Mhz (6607 X 0.007) 46.2 mW Number of available I/O pads 200 Percent of I/O pads used as Outputs Number of I/O pads used as Outputs Number of output buffers switching each clock cycle (20%) 40% 80 Dissipation/output buffers/Mhz/pF Output loading 25µW 50 pF Power/output buffer/Mhz Total output buffer dissipation/Mhz 1.25mW 20mW Total Power dissipation/Mhz 66.2mW 6607 7µW 16 Estimated dissipation of the circuit at the frequencies below is Total Power at 10 Mhz clock rate Total Power at 25Mhz clock rate 0.66W 1.65W CLA70000 CLA70000 Series AC Characteristics for Selected Cells The CLA70000 CLA70000 technology library contains all the timing information for each cell in the design library. This information is accessible to the simulator, which calculates propagation delays for all signal paths in the circuit design. The simulator can automatically derate timings according to the various factors such as: For initial assessments of feasibility, path delay multipliers can be estimated by referring to the following graphs in conjunction with the appropriate delays in the tables. Supply voltage variation (from nominal 5V) Junction temperature Processing tolerance - manufacturing spreads Gate fanout - logic loading on gate outputs Interconnection wiring - net loading on gate outputs Delay Multiplier (normalised to 25°C) Normalised Delay Multiplier Vs temperature 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -60 -10 40 90 140 Temperature °C Figure 6 Delay Multiplier (normalised to 5V) Normalised Delay Multiplier Vs Voltage 1.6 1.4 1.2 1 0.8 3 3.5 4 4.5 5 5.5 Voltage FIgure 7 11 CLA70000 CLA70000 Series AC Charcteristics Worst case propagation Delay (ns) Typical INTERNAL CORE CELLS Name Cells Description Propagation Symbol Commercial Delay (ns) Fanout Fanout =2 0.84 0.18 0.47 0.56 tpLH 0.39 1.01 1.29 0.30 0.79 1.04 tpLH 0.50 1.30 1.81 0.22 0.57 0.80 Master Slave tpLH 0.54 1.40 1.60 D-Type Flip-Flop DF 0.70 tpHL NOR2 0.27 tpHL NAND2 tpLH 1 4 tpHL INV2 2 tpHL 0.55 1.44 1.55 Invertor Dual Drive 1 2-Input NAND Gate 1 2-Input NOR Gate 1 Worst case propagation Delay (ns) Typical INTERMEDIATE BUFFER CELLS Cells Description Commercial Delay (ns) Name Propagation Fanout Symbol Fanout =2 IBDF IBCMOS1 - - - 4 tpLH 0.34 0.88 1.02 tpHL 0.27 0.71 0.84 Master Slave D-type tpLH 0.48 1.24 1.44 Flip-Flop IBGATE 2 tpHL 0.50 1.31 1.42 CMOS input buffer with 2 input NAND gate tpLH 0.60 1.58 1.68 tpLH 0.45 1.17 1.21 Large 2 Input NAND Gate +2 Input NOR Typical Propagation OUTPUT BUFFER CELLS Worst case propagation Delay (ns) Commercial Delay (ns) Name Cells OP3 - OP6 OP12 - - Description Symbol Standard Output Buffer Medium Output Buffer Large Output Buffer Fanout =10pF 10pF 50pF tpLH 0.73 1.90 6.49 tpHL 0.49 1.27 4.40 tpHL 0.50 1.30 3.59 tpLH 0.33 0.85 2.42 tpLH 0.38 0.99 2.14 tpHL 0.25 0.66 1.50 Note : Commercial worst case is 4.5V, 70°C operating Industrial worst case is 4.5V, 85°C operating 12 Fanout 10pF CLA70000 CLA70000 Series DC Electrical Characteristics All characteristics at Commercial Grade voltage and temperature (note1) Characteristic Symbol Min. Max. Conditions V Low Level Input Voltage V IL TTL Inputs (IBTTL1/IBTTL2) 0.80 CMOS Inputs (IBCMOS1/IBCMOS2) 1.00 V High Level Input Voltage VIH TTL Inputs (IBTTL1/IBTTL2) CMOS Inputs (IBCMOS1/IBCMOS2) Input Hysterisis (IBST1) Units Typ. 2.00 V DD -1.00 V Rising Falling VT+ 3.09 V IL to VIH Rising VT- 1.89 V IH to VIL Falling VT+ 1.72 V IL to VIH Input Current CMOS/TTL Inputs VT- 1.10 V IH to VIL (without resistor) IIN (IBST2) -1.00 +1.00 µA Inputs with 1K ohm resistor ±2.20 ±11.00 mA V IN=V DD OR VSS Inputs with 2K ohm resistor ±1.10 ±5.50 mA V IN=V DD OR VSS Inputs with 4K ohm resistor ±0.56 ±2.75 mA V IN=V DD OR VSS ±275.00 µA V IN=V DD OR VSS ±5.00 ±2.50 ±1.25 ±18.00 Inputs with 75K ohm resistor ±66.00 Resistor values nominal (note2) V IN=V DD OR VSS v High Level Output Voltage V OH All Outputs V DD -1.00 VDD -0.05 IOH =-1.00µA Low drive cell OP2/OPOS2/OPT2 V DD -1.00 VDD -0.50 IOH =-2.00mA Standard drive cell OP3/OPOS3/OPT3 V DD -1.00 VDD -0.50 V DD -1.00 VDD -0.50 V -1.00 VDD -0.50 IOH =-4.00mA Smallest drive cell OP1/OPOS1/OPT1 Medium drive cell OP6/OPOS6,OPT6 Large drive cell OP12/OPOS12/OPT12 OP12/OPOS12/OPT12 IOH =-6.00mA IOH =-12.00mA DD VDD -0.50 Low Level Output Voltage v IOH =-24.00mA VOL All Outputs 0.40 IOL=1.00µA Low drive cell OP2/OPOD2/OPT2 0.20 0.40 IOL=2.00mA Standard drive cell OP3/OPOD3/OPT3 0.20 0.40 IOL=4.00mA Medium drive cell OP6/OPOD6,OPT6 0.20 0.40 IOL=6.00mA Large drive cell OP12/OPOD12/OPT12 OP12/OPOD12/OPT12 0.20 0.40 IOL=12.00mA Tristate Output Leakage Current 0.20 VSS+0.05 Smallest drive cell OP1/OPOD1/OPT1 1.00 -1.00 Output short Circuit Current IOZ Standard output OP3/OPT3/OPOD3 IOS IOL=24.00mA (Note 3) OP3/OPT3/OPOS3 µA mA 270.00 67.00 37.00 135.00 V DD=MAX V out=V DD 150.00 75.00 Operating Supply Current (per gate) (note4) IDDOP V OH=V SS or VDD µA/MHz V DD=MAX V out =OV 1.00 pF Output Capcitance CI 5.00 pF Any Inputs (note 5) Bidirectional Pin Capacitance C OUT 5.00 pF Any Outputs (note 5) C I/O 7.00 Input Capacitance Any I/O Pin (note 6) Notes 1) 2) 3) Commercial grade is 0 - 70 °C, 5V ± 10% power supply voltage Resistor value spreads (Min-Max): Low Value (Rtyp 1K) 0.5-2K ohm High Value (Rtyp 4K) 2K-8K ohm Low Value (Rtyp 2K) 1.0-4K ohm High Value (Rtyp 75K) 20K-250K 20K-250K ohm Standard driver output OP3 etc. Short circuit current for other outputs will scale. Not more than one output may be shorted at a time for a maximum duration of one second. 4) 5) 6) Excluding peripheral buffers. Excludes package leadframe capacitance or bi-directional pins. Excludes package. PACKAGING 13 CLA70000 CLA70000 Series · Wide range of surface mount and through board packages · Ceramic equivalents to most plastic packages - for fast prototyping · Ongoing commitment to new package development Production quantities of the CLA70000 CLA70000 family are available in industry-standard ceramic and plastic packages according the codes shown below. Prototype samples are normally supplied in ceramic only. DC DILMON Dual in Line, Multilayer ceramic. Brazed leads Metal Sealed Lid. Through Board DG CERDIP Dual In Line, Ceramic body, Alloy leadframe, Glass Sealed, Through Board DP PLASDIP Dual In Line, Copper or Alloy leadframe, Plastic Moulded. Through Board AC P.G.A. Pin Grid Array, Multilayer Ceramic. Metal Sealed lid. Through Board AC (P) POWER P.G.A. As above with cavity down and Cu/W heat plate MP SMALL OUTLINE (S.O.) Dual In Line, 'Gullwing' Formed Leads. Plastic Moulded Surface Mount LC LCC Leadless Chip Carrier. Multilayer Ceramic. Metal Sealed Lid. Surface Mount HC LEADED CHIP CARRIER GC LEADED CHIP CARRIER Quad Multilayer Ceramic. Brazed J Formed Leads. Metal Sealed Lid. Surface Mount Quad Multilayer Ceramic. Brazed Leads. Metal Sealed Lid. Surface Mount GC (P) POWER LEADED CHIP CARRIER As above with cavity down, and Cu/W heat plate HG QUAD CERPAC Quad Ceramic Body, `J' Formed Leads. Glass Sealed. Surface Mount. GG CERAMIC QUAD FLATPACK Quad Ceramic Body, `Gullwing' Formed Leads. Glass Sealed. Surface Mount. HP PLCC GP PQFP Quad Plastic Leaded Chip Carrier. `J' Formed Leads. Plastic Moulded. Surface Mount Plastic Quad Flat Pack. `Gullwing' Formed Leads. Plastic Moulded. Surface Mount Packaging Options The package style and pin count information is intended only as a guide. Detailed package specification are available from Zarlink Semiconductor Design Centers on request. Available packages are being continuously updated, so if a particular package is not listed, please enquire through your Zarlink Semiconductor Sales Representative. CLA70000 CLA70000 Array Package Guide KEY AVAILABLE ARRAY / PACKAGE COMBINATIONS. - - PLASTIC QUAD FLAT PACK (GP) 70 GP44 71 1734 1734 72 73 74 75 76 70 78 71 1735 1735 72 73 74 GG52 GP64 1756 1756 1755 GP80 1733 1733 1643 1643 1644 1644 1644 1730 1730 1773 1773 1740 1740 1771 1675 1675 1675 1736 1736 76 1773 1740 75 1800 GG80 1710 1800 GG64 1751 GP120 GP120 CERAMIC QUAD FLAT PACK (GG) GG44 GP52 GP100 GP100 77 PROTOTYPES ONLY GG100 GG100 1729 GG120 GG120 GP144 GP144 1758 GG144 GG144 1770 GP160 GP160 1715 GG160 GG160 1769* 14 1715 1737 1769 77 78 CLA70000 CLA70000 Series PLASTIC SMALL OUTLINE (MP) 70 71 72 73 74 75 76 CERAMIC SMALL OUTLINE (MC) 77 70 78 71 MP16L MP16L 1575 MC16 1583 MC20 1587 MC24 1768 MC28 75 76 77 78 77 78 1699 MP28 74 1698 MP24 73 1697 MP20 72 1700 CO-FIRED CERAMIC LEADED CHIP CARRIER (HC) PLASTIC LEADED CHIP CARRIER (HP) 70 71 HP28 1613 1613 HP44 1490 1490 1490 1659 1659 1659 HC68 1660 1660 HC84 HP68 HP84 72 73 74 75 76 77 78 1630 1625 1625 1621 1626 1626 74 75 76 CERAMIC LEADLESS CHIP CARRIER (LC) 1562 1562 1564 1564 1564 LC68 1433 1433 1567 1567 LC84 1455 1455 HG84 77 1630 1560 HG68 76 1624 1630 71 1562 75 73 1560 HG44 74 1624 HC44 73 72 70 HG28 72 71 HC28 GLASS SEALED CERAMIC LEADED CHIP CARRIER (HG) 70 78 70 71 72 75 TBD GC132 GC132 74 1668 77 1450 1454 1454 78 70 73 74 75 76 76 77 GC132 GC132 TBD TBD 1763 TBD TBD 1762 TBD TBD 1739 TBD TBD TBD 1669 1680 TBD TBD 71 72 73 74 GC172 GC172 TBD GC196 GC196 72 73 74 75 76 78 CERAMIC DUAL IN LINE (DC) PLASTIC DUAL IN LINE (DP) 71 78 1365 GC256 GC256 70 77 75 1672 GC196 GC196 72 POWER CERAMIC LEADED CHIP CARRIER (GC) 1662 GC172 GC172 76 1450 LC44 73 71 LC28 CERAMIC LEADED CHIP CARRIER (GC) 70 77 70 78 71 72 DC16 1396 1321 1321 DC28 1348 1348 1525 DC40 1620 1620 1485 DC48 1470 1470 78 1620 1485 77 1348 1524 76 1321 1522 75 1396 DC24 74 1427 DC22 73 1470 DP16 1558 DP22 1513 1513 DP24 1516 1517 1517 DP28 1522 1522 DP40 1524 DP48 1485 15 CLA70000 CLA70000 Series POWER CERAMIC PIN GRID ARRAY (AC) CERAMIC PIN GRID ARRAY (AC) ` 70 AC68 AC84 AC100 AC100 71 72 1462 1462 1479 73 74 75 76 77 78 71 72 73 74 75 76 AC84 1479 TDB AC120 AC120 78 1692 1481 1466 1467 1483 AC180 AC180 1484 1469 TDB TDB TDB 1764 Quality and Reliability · Statistical process control used in manufacture · Regular sample screening and reliability testing · Screening to MIL and Industrial standards available Quality and reliability are built into the product by statistical control of all processing operations and by minimizing random uncontrolled effects in all manufacturing operations. Process management involves full documentation of procedures, recording of batch-by-batch data, using traceability procedures and provision of appropriate equipment and facilities to perform sample screening and conformance testing on finished product. A common information management system is used to monitor the manufacturing of Zarlink CMOS and Bipolar processes. All products benefit from the use of this integrated monitoring system throughout all manufacturing operations leading to high quality standards for all technologies. TBD 1693 TBD AC208 AC208 AC144 AC144 AC257 AC257 77 AC144 AC144 1480 AC132 AC132 16 70 TBD TBD TBD For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. 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