CL-GD6420 CL-GD6410 CL-GD6340 CL-GD6420-B RAMDAC14 MEMCS16 CLK32K CLGD6420 - Datasheet Archive

 

Data Book FEATURES s Single-chip VGA controller s Pin-compatible with the CL-GD6410 in 2-DRAM applications High-Resolution LCD

 

CL-GD6420 CL-GD6420 Data Book FEATURES s Single-chip VGA controller s Pin-compatible with the CL-GD6410 CL-GD6410 in 2-DRAM applications High-Resolution LCD VGA Controller for Notebook Computers s Up to 1 Mbyte (2, 4, or 8) 256K x 4 DRAM Video Memory s Extended resolution up to 1024 x 768 with 256 colors on CRT (interlaced video with 45 MHz clock) s Simultaneous display on LCD panel and CRT The CL-GD6420 CL-GD6420 is a single-chip VGA controller optimized for use in high-end notebook computers, where high-resolution CRT capabilities and high performance are critical design objectives. The CL-GD6420 CL-GD6420 is based on the proven architecture of the CL-GD6410 CL-GD6410, one of the industry's most popular LCD VGA controllers. The CL-GD6420 CL-GD6420 adds a scaleable video memory capability, and can support two, four, or (in Revision B components) eight 256K x 4 DRAMs. Like the CL-GD6410 CL-GD6410, the CL-GD6420 CL-GD6420 has an on-chip RAMDAC, direct-connect ISA (PC AT) bus interface, and direct-connect LCD interface. s IBM ® VGA hardware-compatible s Integrates RAMDAC s Integrates LCD panel interface - Control and data buffering - Power sequencing logic s Direct connection to ISA (PC AT) bus up to 10 MHz s Frame-Accelerator technology for low-active power s Standby and Suspend Modes to save power - Internal standby counter - Software suspend or hardware standby pin s Expanded operational range: 5V ± 10% s 64-shade grayscale on monochrome STN LCD s s s s s OVERVIEW - NTSC sum-to-gray color mapping - Multiple sum-to-gray weighting options Enhanced flicker-reduction algorithms for 4 MHz and quick-response LCDs Direct connection to 512-color TFT LCD panels - Single-controller design for STN monochrome and TFT color LCDs Graphics expansion and compression maps CRT modes to fixed-resolution LCD 8- or 16-bit CPU interface Packaged in 160-pin (EIAJ-standard) QFP package - Pinout optimized for efficient board layout By using the Cirrus Logic Frame-Accelerator technique, the CL-GD6420 CL-GD6420 is able to provide a high vertical refresh rate for dual-scan LCD panels while operating at approximately one-half the clock speed of non-accelerated LCD controller solutions. This provides a significant reduction in full-active power consumption, extending the battery life of notebook computers. Standby and Suspend Modes are supported in the hardware of the CL-GD6420 CL-GD6420, to enable multiple levels of system power management. Standby Mode can be (cont. next page) System Block Diagram VIDEO MEMORY 256K x 4 DRAM FRAME-ACCELERATOR DRAM 5 4 3 BIOS 2 1 0 BUS CL-GD6420 CL-GD6420 ANALOG CRT 160-Pin QFP 5 4 3 2 1 0 14 MHz CLOCK SYN MONOCHROME LCD OR ACTIVE-MATRIX LCD July 1993 OVERVIEW (cont.) initiated by software, or by a programmable on-chip timer with accuracy to within 15 seconds. Standby Mode can also be initiated by a separate Standby Pin. Suspend Mode can be initiated by software. The CL-GD6420 CL-GD6420 provides 64 shades of gray on monochrome LCD panels. Duty-cycle modulation, combined with improved dynamic pattern-management algorithms, provide 16 shades of gray at 640 x 480 resolution with minimum perceivable flicker, even on 4 MHz and fast-response (`mouse-quick') LCD panels. Grayscale enhancement provides additional apparent shades of gray on the LCD for 640 x 480 x 256 color extended mode operation. Pixel-doubling and stippling techniques provide increased grayscale in the VGA high-color Mode 13. In all cases the Cirrus Logic grayscale provides an appearance of linear step functions, making smooth transitions from black, through the grayscale, to white. With a direct connection to 512-color TFT LCD panels, the CL-GD6420 CL-GD6420 provides a single-controller solution for 64 grayscale monochrome and 256-simultaneous-color portable computers. Extended color mode support allows 640 x 480 resolution with 256 colors on TFT LCD panels. For color STN LCD panels, the CL-GD6420 CL-GD6420 provides a direct interface to the CL-GD6340 CL-GD6340, Cirrus Logic's color LCD interface controller. The CL-GD6420 CL-GD6420 panel interface includes programmable panel parameters, which allow a controller design to be optimized for excellent display quality on a variety of panels. On-chip power sequencing logic controls both the initial power-up to the panel, as well the resume power-up from Standby or Suspend Modes. The CL-GD6420 CL-GD6420 supports SimulSCANTM operation, a technique introduced by Cirrus Logic for achieving simultaneous CRT and LCD operation. SimulSCAN allows the portable computer to become a key part of presentation environments for sales force automation, field service and educational organizations. SimulSCAN supports both single- and dual-scan LCDs, and both fixed and multifrequency analog CRTs. Resolution mapping converts CRT resolutions to the LCD's fixed display size. The monochrome LCD may be operated in reverse video (`page-white') simultaneously with normal CRT operation. CL-GD6420 CL-GD6420 Extended Graphics Mode Support Summary CL-GD6420 CL-GD6420 Revision and Video Memory Monochrome LCD Modes Color LCD Modes Multifrequency CRT Modes CL-GD6420 CL-GD6420 with two 256K x 4 DRAMs 640 x 480 x 16 gray with grays enhancement 640 x 480 x 16 colors 640 x 480 x 16 colors CL-GD6420-B CL-GD6420-B with eight 256K x 4 DRAMs 640 x 480 x 16 gray with grayscale enhancement 640 x 480 x 256 colors 640 x 480 x 256 colors, 800 x 600 x 16 colors, 800 x 600 x 256 colors, 1024 x 768 x 16* colors, 1024 x 768 x 256* colors NOTE: * denotes an Interlaced Mode. CL-GD6420 CL-GD6420 Notebook VGA Controller Table of Contents Section Page Section Page 1. PIN INFORMATION .4 5. ELECTRICAL SPECIFICATIONS .27 1.1 Pin Diagram 4 2. DETAILED PIN DESCRIPTION .5 3. FUNCTIONAL DESCRIPTION.11 5.1 5.2 5.3 5.4 Absolute Maximum Ratings27 CL-GD6420 CL-GD6420 DC Specifications (Digital)28 CL-GD6420 CL-GD6420 DC Specifications (RAMDAC)29 DAC Characteristics29 3.1 3.2 3.3 3.4 6. AC TIMING CHARACTERISTICS .30 6.1 Index of Timing Information31 7. CL-GD6420 CL-GD6420 REGISTERS .59 3.5 3.6 3.7 Functional Operation11 CRT Display Modes12 Flat Panel Display Modes12 Intelligent Power Management and Sequencing12 Internal RAMDAC14 RAMDAC14 CL-GD6420 CL-GD6420 Configuration16 CL-GD6420 CL-GD6420 DRAM Configuration17 7.1 7.2 7.3 VGA Register Port Map61 Register Delta List Between the CL-GD6420 CL-GD6420 Rev. A and Rev. B.61 Extended Register Descriptions62 4. VGA REGISTERS .18 8. SAMPLE PACKAGE .140 4.1 Video Graphics Array-Compatible Register Table18 CL-GD6420 CL-GD6420 Extension Register Table20 CL-GD6420 CL-GD6420 Flat Panel Extension Register Table23 CL-GD6420 CL-GD6420 Memory Map Summary Table24 Modes Supported During CRT Display Table25 Modes Supported During LCD Display Table26 8.1 160-Pin Quad Flat Pack (QFP, EIAJ)140 9. TYPICAL APPLICATION.141 4.2 4.3 4.4 4.5 4.6 July 1993 10. ORDERING INFORMATION.142 10.1 Cirrus Logic Numbering Guide142 Figures Figure Page Figure 3­1 RAMDAC Block Diagram14 Figure 3­2 CL-GD6420 CL-GD6420 DRAM Configuration17 List of Waveforms, Figures 6­1 to 6­2631 DATA BOOK 3 CL-GD6420 CL-GD6420 Notebook VGA Controller 1. PIN INFORMATION The CL-GD6420 CL-GD6420 is available in a 160-pin quad flat pack device configuration, shown below. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 CL-GD6420 CL-GD6420 160-Pin QFP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 BIOS-ROMEN*/SSCLK BIOS-A[13] BIOS-A[14] VCC BIOS-A[15] Reserved STANDBY* AVSS IREF BLUE GREEN Reserved Reserved RED AVDD (ANALOG) AEN RESET BALE REF* MEMW* MEMR* IOWR* IORD* SBHE* GND DIR DSELH* D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] D[8] D[9] D[10] D[11] D[12] M2D[5] M2D[6] M2D[7]/PD7 FRA4/PUD0 FRA5/PUD1 FRA6/PUD2 FRA7/PUD3 FRA8/PUD4 PWG PO1/OE[1]* PO2/WE[1]* MEMCS16 MEMCS16* IOCHRDY Reserved CRTINT CS A[16] A[17] A[18] A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] GND A[9] A[10] A[11] A[12] A[13] A[14] A[15] D[15] D[14] D[13] VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 M0D[5]/MID[0] M0D[4] M0D[3] M0D[2] M0D[1] M0D[0] GND AA[0] AA[1] AA[2] AA[3] VCC AA[4] AA[5] AA[6] AA[7] AA[8] OE[0]* WE[0]* CLKPW* RAS*[0] RAS*[1] CAS*[0] CAS*[1] AB[0] AB[1] AB[2] AB[3] VCC AB[4] AB[5] AB[6] AB[7] AB[8] GND M2D[0] M2D[1] M2D[2] M2D[3] M2D[4] 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 M0D[6]/MID[1] M0D[7]/MID[2] FRWE* FRCAS* FRRAS* FROE* FRAD3/SW1 FRAD2/SW2 FRAD1/SW3 FRAD0/SW4 GND SQCLK CLKSEL[0] CLKSEL[1] CLKSEL[2] CLKSEL[3] OSC CLK32K CLK32K FC[1]/FPVEE FC[0]/FPVCC MOD/P8/INTERNAL* LFS/PVSYNC LLCLK/DE/PHSYNC FPVDCLK BLANK* VSYNC HSYNC P[7] P[6] GND P[5] P[4] P[3] P[2] P[1] P[0] VDCLK FPHDE FPVDE GND 1.1 Pin Diagram 4 DATA BOOK July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller 2. DETAILED PIN DESCRIPTION The following conventions are used in the pin assignment: (I) indicates input; (O) indicates output; (TO) indicates tri-state output; (AO) indicates analog output, (AI) indicates analog input; (PW) indicates power; (*) indicates active-low. Name Pin No. Type Description CS 16 I CHIP SELECT: When high, this indicates that the CLGD6420 CLGD6420 is selected for memory accesses. A[18:16] A[15:9] A[8:0] 19:17 36:30 28:20 I CPU ADDRESS INPUTS. D[15:0] 37:39 41:53 I/O CPU DATA I/O. DSELH* 54 O DATA SELECT HIGH BYTE: This enables the CPU data bus upper-byte buffer when needed. DIR 55 O CPU DATA BUS BUFFER DIRECTION: When low, this indicates a CPU read. (DIR is used only when CPU data has to be buffered). SBHE* 57 I BYTE HIGH ENABLE: This signal is sampled only if 16-Bit Mode is enabled; otherwise, 8-bit bus operations are assumed. IORD* 58 I I/O READ: This indicates that an I/O read cycle is taking place. IOWR* 59 I I/O WRITE: This indicates that an I/O write cycle is taking place. MEMR* 60 I MEMORY READ: This indicates that a memory read cycle is taking place. MEMW* 61 I MEMORY WRITE: This indicates that a memory write cycle is taking place. REF* 62 I REFRESH: This indicates a memory refresh cycle and will cause the CL-GD6420 CL-GD6420 to ignore memory accesses on the bus. BALE 63 I ADDRESS LATCH ENABLE: A high indicates a valid memory address. July 1993 DATA BOOK 5 CL-GD6420 CL-GD6420 Notebook VGA Controller 2. Detailed Pin Description (cont.) Name Pin No. Type Description RESET 64 I SYSTEM RESET: This input is normally connected to the system reset bus signal and is used as a hardware reset signal for the CL-GD6420 CL-GD6420. AEN 65 I ADDRESS ENABLE: This is a host CPU bus signal that distinguishes between DMA and non-DMA bus cycles. The signal is high for a DMA cycle, and will cause the CL-GD6420 CL-GD6420 to ignore IORD* and IOWR*. MEMCS16 MEMCS16* 12 TO MEMCS16 MEMCS16*: This output is an acknowledge for 16-bit-wide accesses and is generated by the CL-GD6420 CL-GD6420 only if the 16bit Peripheral Mode is enabled, and a valid memory address range has been decoded. IOCHRDY 13 TO IOCHRDY: This signal is driven low to lengthen memory cycles. CRTINT 15 TO CRTINT: Indicates the start of a vertical retrace, normally connected to one of the interrupt inputs on the PC bus. AA[8:0] AA[3:0] 137:133 131:128 O VIDEO MEMORY `A' ADDRESS BUS: This bus contains the row/column address information required by the DRAMs in Video Memory Planes 0 and 1. This bus carries different addresses than the AB Bus in text modes. AB[8:4] AB[3:0] 154:150 148:145 O VIDEO MEMORY `B' ADDRESS BUS: This bus contains the row/column address information required by the DRAMs in Video Memory Planes 2 and 3. This bus carries different addresses than the AA Bus in text modes. OE[0]* 138 O VIDEO MEMORY OUTPUT ENABLE BANK 0: For two and four DRAM configurations. WE[0]* 139 O VIDEO MEMORY WRITE ENABLE BANK 0: For two and four DRAM configurations. PO1/OE[1]* 10 O PROGRAMMABLE OUTPUT #1/VIDEO MEMORY OUTPUT ENABLE/WRITE ENABLE BANK 1: For eight-DRAM configurations. PO2/WE[1]* 11 O PROGRAMMABLE OUTPUT #1/VIDEO MEMORY OUTPUT ENABLE/WRITE ENABLE BANK 1: For eight DRAM configurations. 6 DATA BOOK July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller 2. Detailed Pin Description (cont.) Name Pin No. Type CLKPW* 140 O CLOCK CHIP POWER CONTROL: Active low, can be used to control external transistor logic connected to clock synthesizer power pins. This signal is active in Suspend Mode. RAS*[1:0] CAS*[1:0] 142:141 144:143 O VIDEO MEMORY RAS*: RAS*[0] to AA Bus, RAS*[1] to AB Bus. CAS*[1:0] 143:144 O VIDEO MEMORY CAS*: CAS*[0] to AA Bus, CAS[*1] to AB Bus. M0D[7]/MID[2] 119 I/O VIDEO MEMORY DATA PIN: Planes 0 and 1, Bit 7. MONITOR ID BIT 2. The state of this pin is sampled at reset and latched into ER9C[7]. M0D[6]/MID[1] 120 I/O VIDEO MEMORY DATA PIN: Planes 0 and 1, Bit 6. MONITOR ID BIT 1. The state of this pin is sampled at reset and latched into ER9C[6]. M0D[5]/MID[0] 121 I/O VIDEO MEMORY DATA PIN: Planes 0 and 1, Bit 5. MONITOR ID BIT 0. The state of this pin is sampled at reset and latched into ER9C[5]. M0D[4:0] 126:122 I/O VIDEO MEMORY DATA PINS: Planes 0 and 1, Bits 4:0. M2D[7]/PD7 3 I/O VIDEO MEMORY DATA PINS: Planes 2 and 3, Bit 7. PULL DOWN # 7: The state of this pin is sampled at reset and latched into ER99[7]. M2D[6:0] 2, 1, 160:156 I/O VIDEO MEMORY DATA PINS: Planes 2 and 3, Bits 6:0. FRWE* 118 O FRAME-ACCELERATOR WRITE ENABLE*. FRCAS * 117 O FRAME-ACCELERATOR CAS*. FRRAS* 116 O FRAME-ACCELERATOR RAS*. FROE* 115 O FRAME-ACCELERATOR OE*. FRAD3/SW1 114 I/O FRAME-ACCELERATOR MULTIPLEXED ADDRESS/DATA[3] multiplexed with Switch 1. FRAD2/SW2 113 I/O FRAME-ACCELERATOR MULTIPLEXED ADDRESS/DATA[2] multiplexed with Switch 2. July 1993 Description DATA BOOK 7 CL-GD6420 CL-GD6420 Notebook VGA Controller 2. Detailed Pin Description (cont.) NAME PIN NO. TYPE DESCRIPTION FRAD1/SW3 112 I/O FRAME-ACCELERATOR MULTIPLEXED ADDRESS/DATA[1] multiplexed with Switch 3. FRAD0/SW4 111 I/O FRAME-ACCELERATOR MULTIPLEXED ADDRESS/DATA[0] multiplexed with Switch 4. FRA4/PUD0 4 I/O FRAME-ACCELERATOR ADDRESS [4] multiplexed with Pull-Up or Pull-Down 0. FRA5/ PD1 5 I/O FRAME-ACCELERATOR ADDRESS [5] multiplexed with Pull-Down 1. FRA6/PD2 6 I/O FRAME-ACCELERATOR ADDRESS [6] multiplexed with Pull-Down 2. FRA7/PUD3 7 I/O FRAME-ACCELERATOR ADDRESS [7] multiplexed with Pull-Up or Pull-Down 3. FRA8/PUD4 8 I/O FRAME-ACCELERATOR ADDRESS [8] multiplexed with Pull-Up or Pull-Down 4. PWG 9 I POWER GOOD INPUT: This signal initiates flat panel power sequencing when power is applied or removed from the CL-GD6420 CL-GD6420. FPVDE 82 O FLAT PANEL VERTICAL DISPLAY ENABLE for special panels. FPHDE 83 O FLAT PANEL HORIZONTAL DISPLAY ENABLE for special panels. VDCLK 84 O VIDEO CLOCK: This is the output for the external RAMDAC or color panel. P[0:7] 85:90 92:93 O VIDEO DATA OUT: If external, RAMDAC configuration and pixel data output for flat panels. HSYNC 94 O HORIZONTAL SYNC to CRT Monitor. VSYNC 95 O VERTICAL SYNC to CRT Monitor. 8 DATA BOOK July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller 2. Detailed Pin Description (cont.) NAME PIN NO. TYPE DESCRIPTION BLANK* 96 O BLANK OUTPUT: If external, RAMDAC configuration for the CL-GD6340 CL-GD6340. FPVDCLK 97 O FLAT PANEL VIDEO CLOCK. LLCLK/DE/PHSYNC 98 O FLAT PANEL LINE CLOCK: This is used to increment Row-Shift Registers within LCD panels, or DISPLAY ENABLE if the CL-GD6420 CL-GD6420 is used with the CL-GD6340 CL-GD6340. PHSYNC: To be used for flat panels that require a Horizontal Sync Signal. This signal should be used instead of HSYNC since that signal is not active in Panel-Only Mode. LFS/PVSYNC 99 O LCD FRAME START PULSE: This indicates the start of a new frame on flat panels. PVSYNC: To be used for flat panels that require a Vertical Sync Signal. This signal should be used instead of VSYNC since that signal is not active in Panel-Only Mode. MODUL/P8/INTERNAL* 100 O LCD PANEL MODULATION SIGNAL: This is required for LCD panels that do not drive the function themselves. INTERNAL* is a programmable output. P8 is the ninth data bit needed for 512-color LCD panels. FC[0]/FPVCC 101 O FEATURE CONNECTOR PROGRAMMABLE I/O BIT [0] or LCD panel 5V control. FC[1]/FPVEE 102 O FEATURE CONNECTOR PROGRAMMABLE I/O BIT [1] or LCD panel back-light power control. CLK32K CLK32K 103 I 32 kHz CLOCK: The input is used both for slow timers and in Suspend Mode. Power-sequencing of the LCD flat panel is initiated from this input. This input is required. OSC 104 I CLOCK-IN: This is an input from a multifrequency clock source or 14.318 MHz crystal. CLKSEL[3:0] 105:108 I/O CLOCK SELECT: These are inputs from external oscillators or outputs to a multifrequency synthesizer. SQCLK 109 I VIDEO MEMORY SEQUENCER CLOCK. R 67 AO ANALOG RED. G 70 AO ANALOG GREEN. July 1993 DATA BOOK 9 CL-GD6420 CL-GD6420 Notebook VGA Controller 2. Detailed Pin Description (cont.) Name Pin No. Type B 71 BIOS-A[13:15] 79, 78, 76 I/O BIOS ADDRESS 13 - 15. BIOS-ROMEN*/SSCLK 80 I/O BIOS-ROM ENABLE: This output is used to enable C000 BIOS ROM if the CL-GD6420 CL-GD6420 is used in an adapter card application. SCREEN SAVE CLOCK: This input is used to detect keyboard activity for Standby Mode in motherboard applications. STANDBY* 74 I STANDBY: This input is used to initiate Standby Mode from an external source. It can be used in conjunction with the software method. It is asynchronous active low. IREF 72 AI RAMDAC CURRENT REFERENCE. AVSS 73 PW RAMDAC ANALOG VSS. AVDD 66 PW RAMDAC ANALOG VDD. VCC 40, 77 132, 149 PW VCC PINS. GND 29, 56, PW 81, 91, 110 127, 155 GROUND PINS. Reserved 14, 68, 69, 75 Reserved (May be connected to ground). 10 DATA BOOK AO Description ANALOG BLUE. July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller 3. FUNCTIONAL DESCRIPTION 3.1 Functional Operation The CL-GD6420 CL-GD6420 interfaces with the host processor, video memory, display device, and other external I/O. The host memory interface may be either 8 or 16 bit. In the CL-GD6420 CL-GD6420 revision `A', the video memory interface may be organized as two or four DRAMs for a maximum of 512k bytes. In the CL-GD6420 CL-GD6420 revision `B', the video memory interface may be organized as two, four, or eight DRAMs for a maximum of 1 Mbyte. The CLGD6420 CLGD6420 is AT bus-compatible to 12.5 MHz. Because the CL-GD6420 CL-GD6420 has a demultiplexed address and data bus, most systems will be able to interface it directly - without the addition of businterface buffers. Flat-panel display devices supported will typically be 640 x 480-resolution monochrome STN or color TFT LCD panels. These panels are supported by a direct interface, precluding the need for buffers. Direct power sequencing for panels that require sequencing is supported. CRT displays supported are PS/2TM VGAcompatible analog monitors, including the IBM 85xx families, and multifrequency analog monitors. The CL-GD6420 CL-GD6420 also interfaces with the Cirrus Logic CL-GD6340 CL-GD6340 Color LCD Interface Controller for the best possible color support on a wide variety of color panels. A PS/2-compatible RAMDAC, necessary to accomplish a VGA design, is built into the CLGD6420 CLGD6420. This provides savings in both power consumption and space requirements. The RAMDAC is fully compatible, and is fully supported by the CL-GD6420 CL-GD6420 enhanced power management features. The four major operations supported by the CLGD6420 CLGD6420 are: · Host Access to CL-GD6420 CL-GD6420 Registers · Host Access to Video Memory · Memory Refresh · Display Refresh July 1993 Host Access to Registers The host processor is typically a minimum 8088 or 80x86-type microprocessor in a PC/XT/AT buscompatible environment and can access the CLGD6420 CLGD6420 Registers by setting up a 24-bit address and generating IORD*, IOWR, MEMR* and MEMW* signals. Memory reads and writes can be 8 or 16 bit; I/O reads and writes are 8 bit. DRAM and screen refresh activities occur concurrently and independently. The registers that may be accessed by the host are listed in Section 4. They include all of the standard VGA registers as well as the CL-GD6420 CL-GD6420 Extension Registers. Host Access to Video Memory Host access to video memory is channeled via the CL-GD6420 CL-GD6420. The host must establish the proper address/data/timing parameters in the CLGD6420 CLGD6420 Registers to transfer to and from video memory. The CL-GD6420 CL-GD6420 also contains an intelligent sequencer that allocates video memory cycles not only to the host, but also to the DRAM refresh and the display CRT controllers. Memory Refresh Memory bandwidth is allocated to each process according to the actual real-time needs of the process, ensuring efficient use of the available bandwidth. For a CRT display device, the display is blanked during horizontal and vertical retrace intervals, opening memory bandwidth for host access and/or memory refresh. Unlike early VGA implementations that gave the host only 14% of memory cycles, the CL-GD6420 CL-GD6420 can give the host from 25-50% access to video memory, or one out of two memory cycles. This is largely due to the sequencing strategy. Display Refresh In bit-mapped graphics modes, and text modes, pixel data is latched into the CL-GD6420 CL-GD6420, transferred to Shift Registers, and shifted out upon translation through the CL-GD6420 CL-GD6420 self-contained Color Palette Registers and RAMDAC. DATA BOOK 11 CL-GD6420 CL-GD6420 Notebook VGA Controller The CL-GD6420 CL-GD6420 tracks the active and unused areas of the screen and cursor positions and consequently supplies screen control signals - VSYNC, HSYNC, and BLANK*. When the CL-GD6420 CL-GD6420 is connected to a dual-scan LCD display, an additional 64K x 4 DRAM is needed. This Frame-Accelerator is used for splitpanel data formatting. The reconstituted data from the Frame-Accelerator and video memory is then supplied in parallel to the LCD 4-bit upper and lower panel data buses. This technique not only maintains display contrast, but also reduces the power consumption of the video circuitry. The panel frame rate is twice the rate that the data is fetched from video memory. 3.2 CRT Display Modes The CL-GD6420 CL-GD6420 includes all registers and data paths required for VGA compatibility. VGA enhancements include 16 simultaneously loadable text fonts (twice the capability of IBM VGA), and Readable Registers. Extended graphics resolutions beyond the 640 x 480 IBM VGA standard are available. Using multifrequency monitors, 800 x 600 and 1024 x 768 Modes with a 4:3 aspect ratio can be displayed in either 16 or 256 colors. (1024 x 768 with 256 colors is available only in Interlaced Mode). High-resolution text modes offer from 100 columns by 50 rows up to 132 columns by 60 rows. 3.3 Flat Panel Display Modes The CL-GD6420 CL-GD6420 will directly drive all of the popular monochrome dual-panel/dual-scan LCD panels. Proprietary techniques minimize flicker, noise and pattern motion while enhancing contrast within the grayscales being used. Grayscaling is accomplished by modulating the ON-to-OFF time of individual pixels in the panel and allowing the eye to integrate the superposed pixels to 16 perceptible grayscales. Flicker is eliminated by proprietary techniques involving distribution of time between ON and OFF pixels during frame modulation. 12 DATA BOOK The CL-GD6420 CL-GD6420 allows the full spectrum of PC applications written for analog monitors and various video modes to run on standard 640 x 480 flat panels. This is accomplished through color emulation, attribute remapping, and resolution mapping. In addition, summing circuitry allows rapid generation of IBM-compatible grayscale equivalents of color images. Up to 64 grayscale levels are available by using proprietary two-dimensional stippling logic. This technique permits all applications that generate monochrome, 4,- 16-, or 256-color images to be run on a monochrome flat-panel display. Cirrus Logic AutoMap logic can map 256 colors into a monochrome image; the colors then appear either in 16 shades of gray with grayscale enhancement (640 x 480 256 color mode), or 64 shades of gray (320 x 200 256 color mode). The hardware-based algorithm tracks the particular palette map being used by the internal RAMDAC. RAMDAC data may be stored, as desired by the application, in orderly or random sequences. Realistic renditions of color images are not affected. In color text modes, foreground and background attributes can be automatically remapped to black and white for maximum contrast. Positive or negative raster may be selected under program control to match the visual qualities of the display and/or needs of the application. The video resolutions that an application has selected are remapped to a flat panel according to whether Compatibility Mode, Compression Mode, or Expanded Mode was selected. 3.4 Intelligent Power Management and Sequencing Notebook and laptop PCs have stringent power limitations due to battery operation and heat dissipation. To meet these needs, the CL-GD6420 CL-GD6420 is manufactured using low-power CMOS technology. In addition, the CL-GD6420 CL-GD6420 has programmable output pins as well as other intelligent power management features that will permit the controller to enter the modes explained below to conserve power. July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller Several dedicated pins have been assigned to facilitate power management. The PWG Signal (Power Good) can be used to signify the beginning of a power-on or power-off sequence. The signal FPVCC and FPVEE can be used to control panel logic power and panel back light/contrast, when a panel requires that these functions be sequenced or controlled. Normal Mode · · · · · Power to LCD panel and full screen refresh CPU access to Video Memory Refresh to Video Memory CPU access to RAMDAC CPU access to I/O Registers Since power consumption is directly proportional to the frequency at which the controller is run, the CL-GD6420 CL-GD6420 uses a proprietary Frame-Accelerator to maintain the maximum screen refresh rate, while the clock to the CL-GD6420 CL-GD6420 functions at 25 MHz or less. The Frame-Accelerator is used only with dual-scan LCD panels. Standby Mode · · · · · · · No power to LCD panel and no screen refresh Panel power sequencing is observed CPU access to Video Memory Refresh to Video Memory CPU access to RAMDAC CPU access to I/O Registers Frequency Synthesizer is not powered-down The primary power savings in this mode comes from cutting power to the LCD panel only. Since there is no screen refresh, normal clock rates are not required and may be replaced by slower clock rates to further reduce power consumption. The SSCLK (Screen-Save-Clock) input pin can be used to detect a variety of external system activities: detecting keyboard activity is one recommended implementation. Any RAMDAC I/O can be executed. The system will recover from Standby Mode after receiving stimuli in the form of video memory read or write accesses, or the presence of the SSCLK Signal. If power sequencing is in progress, then the CL-GD6420 CL-GD6420 will allow the sequencing to complete before exiting Standby Mode. July 1993 The CL-GD6420 CL-GD6420 contains a power-save timer that allows it to be programmable in increments of one minute up to 63 minutes with an accuracy of ± 15 seconds. If the feature is enabled, this is the timeout time from the last stimuli to automatically switch to Standby Mode. The timer stimuli can be by either the SSCLK Signal or by CPU memory access (read or write). The input signal STANDBY* can be used by external hardware to enter or exit from this mode. Use of the STANDBY* Pin can be combined with the software method in any combination. Suspend Mode · · · · No power to LCD panel and no screen refresh Panel power sequencing is observed No CPU access to Video Memory Refresh to Video Memory continues but using a 32 kHz clock · No CPU access to RAMDAC · No CPU access to I/O Registers · Frequency Synthesizer is powered-down The power savings in this mode occurs because host access to video memory is now denied, and a slower clock is used. This slow clock refreshes video memory by performing CAS*-before-RAS* refresh. With slow-refresh DRAM, a clock running as slow as 32 kHz can be used. If calculations indicate that 32 kHz violates the selected DRAM refresh specifications, then the CL-GD6420 CL-GD6420 can provide 64 kHz from the 32 kHz input. Other than this refresh logic, the rest of the CL-GD6420 CL-GD6420 does not have clocks, reducing power consumption even further. Suspend Mode can be activated or deactivated, under program control, by a sequence of three consecutive I/O writes to the `active' IBM VGAcompatible `Sleep' Port (46E8H 46E8H or 3C3H). Shutdown · No power to LCD panel · No clocks to the VGA controller subsystem Prior to initiating a system-wide shutdown, the video-subsystem state can be saved by the system itself for later restoration. The CL-GD6420 CL-GD6420 allows the system to save or restore the status of all controller registers. DATA BOOK 13 CL-GD6420 CL-GD6420 Notebook VGA Controller 3.5 Internal RAMDAC each - one for R, one for G, and one for B - and then applied to the individual DAC inputs. The CL-GD6420 CL-GD6420 includes an on-chip, high-speed, memory digital-to-analog converter known as a RAMDAC. The RAMDAC circuitry helps the CLGD6420 CLGD6420 process color video signals and timing information to the display. The RAMDAC includes a 256-entry by 18-bit word color lookup table, three 6-bit digital-to-analog converters (DACs), a Pixel Mask Register and a Border Color Register. An 8-bit address value applied on the pixel addres inputs defines the memory location for reading an 18-bit color data word from the color lookup table. This data is partitioned as three fields of six bits A pixel word mask is incorporated to allow the incoming pixel address to be altered, permitting changes to the color lookup table contents to be made immediately. This feature allows special display operations such as flashing objects and overlays to be created. The color lookup table contents are accessed via its 8-bit-wide host interface. An internal synchronizing circuit allows the color value accesses to be completely asynchronous to the pixel video operation. 346420-1 NOTE: This diagram documents the RAMDAC as if it were external. Some signals are not INPUTS or OUTPUTS of the CL-GD6420 CL-GD6420. Figure 3­1. RAMDAC Block Diagram 14 DATA BOOK July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller RAMDAC Video Operation In video operation, pixel addresses P0 through P7, BLANK* and BORDER* are sampled on the rising edge of ther pixel clock (PCLK). Their effect appears at the DAC outputs after three further rising edges of PCLK. Both BLANK* and BORDER* are active-low signals. When the BLANK* input is low, a binary 0 is applied to the DAC inputs, producing a zero-volt DAC output. When the BORDER* input is low, the color data from the Border Color Register is applied to the DAC inputs. The DACOFF* Input is both a display disable control and a DAC power-down control. When DACOFF* is low, the DACs in the RAMDAC are totally inoperative, which results in the power dissipation being reduced to standby minimum. During this time, the three DAC outputs are at a zero-volt level. When DACOFF* goes high, several PCLK cycles are required before the DACs in the RAMDAC will function properly. Analog Outputs The DAC outputs are designed to produce 0.7-volt peak white amplitude with a reference current (IREF) of 6.7 mA when driving a doubly terminated 75 ohm load, which corresponds to an effective DAC output load of 37.5 ohms (Reffective). For all values of IREF and output loading: Vblacklevel = zero volts Writing to the Color Lookup Table To write a color definition to the lookup table, a value specifying an address location in the lookup table is first written to the Write Mode Address Reg- July 1993 ister. The color values for the red, green and blue intensities are then written in succession to the Color Value Register. After the blue data is latched, this new color data is then written into the lookup table at the defined address, and the Address Register is incremented automatically. Since Address Register increments after each transfer of data to the lookup table, it is best to write a set of consecutive locations at once. The start address of the set of locations is first written to the Write Address Mode Register. The color data for each address location is then sequentially written to the Color Value Register. The RAMDAC automatically writes data to the lookup table and increments the Address Register after each host transfer of three bytes of color data. Reading from the Color Lookup Table To read color data from the lookup table, a value specifying the address location of the data is written to the Read Mode Address Register. After the address is latched, the data from this location is automatically read out to the Color Value Register, and the Address Register automatically increments. The color intensity values are then read from the Color Value Register by the sequence of three read (RD*) commands. After the blue value is transferred out, new data is read from the lookup table at the current address to the Color Value Register, and the Address Register to automatically increment again. If the Address Register is loaded with a new starting address while an unfinished sequence is in progress, the system resets and starts a new sequence. This occurs for both read and write operations. DATA BOOK 15 CL-GD6420 CL-GD6420 Notebook VGA Controller 3.6 CL-GD6420 CL-GD6420 Configuration The CL-GD6420 CL-GD6420 provides several configuration options. These options are set by installing `pull-up' or `pull-down' resistors on certain CL-GD6420 CL-GD6420 pins, which are sampled at system reset. The selections made are configurations that need only be made once. All listed connections are required. Pin Name and No. Function Notes FRA4/PUD0 (4) BIOS Support High = BIOS @ C000; Low = E000 Low for motherboard implementations when the desired BIOS is at E000. Pull high for adapter implementations or when the BIOS is at C000. FRA6/PD2 (6) VGA Address Space High = Yxx (I/O)/Yxxx (memory) Low = 3xx (I/O)/Axxx (memory) Low in most cases. Pulling high would allow for other than a DOS environment. FRA7/PD3 (7) Sleep Mode I/O Address High = 46E8h; Low = 3C3h Normally high for adapter controller implementations, low for motherboard implementations. FRA8/PUD4 (8) BIOS Width Select High = 16-bit BIOS; Low = 8-bit Defines BIOS-to-controller interface. FRAD0/SW4 (111) Reserved and FRAD1/SW3 (112) FRAD2/SW2 (113) Panel Class and FRAD3/SW1 (114) 16 DATA BOOK No connection required. SW3 0 0 0 0 1 1 1 1 SW2 0 0 1 1 0 1 1 1 SW1 0 1 0 1 1 0 0 1 Panel Class 0 = 3 MHz 1 = 6/6.3 MHz 2 = 3 MHz with extra line clock 3 = 512 color TFT 4 = 3 MHz 5 = 6/6.3 MHz 6 = 3 MHz with extra line clock 7 = Plasma July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller 3.7 CL-GD6420 CL-GD6420 DRAM Configuration 0 - 1024K 1024K (8-DRAM) 0 - 512K (4-DRAM) 0 - 256K (2-DRAM) AA[8:0] RAS[0] / CAS[0] 256K x 4 256K x 4 256K x 4 256K x 4 WE[0] / OE[0] WE[1] / OE[1] M0D[3:0] M0D[7:4] AB[8:0] RAS[1] / CAS[1] 256K x 4 256K x 4 256K x 4 256K x 4 WE[0] / OE[0] WE[1] / OE[1] M2D[3:0] M2D[7:4] BANK 0 BANK 1 Figure 3­2. CL-GD6420 CL-GD6420 DRAM Configuration July 1993 DATA BOOK 17 CL-GD6420 CL-GD6420 Notebook VGA Controller 4. VGA REGISTERS 4.1 Video Graphics Array-Compatible Register Table Abbr. VGA Register Name MISC FEAT STAT FC GPOS1/MISC GPOS2/FC GRX GR0 GR1 GR2 Miscellaneous Output Input Status 0 (Feature Read) Input Status 1 (DisplayStatus) Feature Control Graphics 1 Pos. (W), Misc. (R) Graphics 2 Pos. (W), FeatCtrl (R) Graphics Controller Index Set/Reset Enable Set/Reset Color Compare GR3 GR4 GR5 GR6 GR7 GR8 ARX AR0-F AR10 AR11 AR12 AR13 AR14 CLPEN SLPEN SERX SR0 SR1 SR2 SR3 SR4 SR6 SR7 Data Rotate Read Map Select Mode Miscellaneous Color Don't Care Bit Mask Attribute Controller Index Color Palette Regs 0-15 Mode Control Overscan Color Color Plane Enable Horizontal Pixel Panning Color Select Clear Light Pen Flip Flop Set Light Pen Flip Flop Sequence/Extension Register Index Reset Clocking Mode Plane Mask Character Map Select Memory Mode Extensions Control (see Ext. Table) Reset H. Character Counter 18 DATA BOOK Bits R/W Reg. Index Mono. Port Color Port 8 4 7 3 2, 8 2, 3 4 4 4 4 W R R W R/W R/W R/W R/W R/W R/W ­ ­ ­ ­ ­ ­ ­ 00 01 02 3C2 3C2 3BA 3BA 3CC 3CA 3CE 3CF 3CF 3CF 3C2 3C2 3DA 3DA 3CC 3CA 3CE 3CF 3CF 3CF 5 3 7 4 4 8 6 8 7 8 6 4 4 0 0 7 2 6 4 6 3 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W W R/W R/W R/W R/W R/W R/W R/W W 03 04 05 06 07 08 ­ 00-0F 00-0F 10 11 12 13 14 ­ ­ ­ 00 01 02 03 04 06 07 3CF 3CF 3CF 3CF 3CF 3CF 3C0 3C0 3C0 3C0 3C0 3C0 3C0 3BB 3BC/3B9 3C4 3C5 3C5 3C5 3C5 3C5 3C5 3C5 3CF 3CF 3CF 3CF 3CF 3CF 3C0 3C0 3C0 3C0 3C0 3C0 3C0 3DB 3DC 3C4 3C5 3C5 3C5 3C5 3C5 3C5 3C5 July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller 4.1 Video Graphics Array-Compatible Register Table (cont.) Abbr. VGA Register Name CRX CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 CRA CRB CRC CRD CRE CRF LPENH LPENL CR10 CR11 CR12 CR13 CR14 CR15 CR16 CR17 CR18 CR22 CR24 CR26MSB CR26MSB CR27MSB CR27MSB CR30-CR3F CR30-CR3F CRTC Index Horizontal Total Horizontal Display End Horizontal Blanking Start Horizontal Blanking End Horizontal Retrace Start Horizontal Retrace End Vertical Total Overflow Screen A Preset Row Scan Character Cell Height Cursor Start Cursor End Screen A Start Address High Screen A Start Address Low Cursor Location High Cursor Location Low Light Pen High Light Pen Low Vertical Retrace Start Vertical Retrace End Vertical Display End Offset Underline Location Vertical Blanking Start Vertical Blanking End CRT Mode Control Line Compare Readback CRT Latches Attribute Index Toggle CRTC ScrA Start Address MSB CRTC Cursor Address MSB Frame Blank NOTE: Bits 6/5 8 8 8 5+2+1 8 5+2+1 8 8 7 5+1+1+1 6 5+2 8 8 8 8 8 8 8 4+2+1+1 8 8 5+2 8 8 7 8 8 7 2 2 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R W W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W W Reg. Index ­ 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 10 11 12 13 14 15 16 17 18 22 24 26 27 3X Mono. Port 3B4 3B5 3B5 3B5 3B5 3B5 3B5 3B5 3B5 3B5 3B5 3B5 3B5 3B5 3B5 3B5 3B5 3B5 3B5 3B5 3B5 3B5 3B5 3B5 3B5 3B5 3B5 3B5 3B5 3B5 3B5 3B5 3B5 Color Port 3D4 3D5 3D5 3D5 3D5 3D5 3D5 3D5 3D5 3D5 3D5 3D5 3D5 3D5 3D5 3D5 3D5 3D5 3D5 3D5 3D5 3D5 3D5 3D5 3D5 3D5 3D5 3D5 3D5 3D5 3D5 3D5 3D5 Split-field registers are denoted by `X+Y' or `X+Y+Z' or `X+Y+Z+M'. July 1993 DATA BOOK 19 CL-GD6420 CL-GD6420 Notebook VGA Controller 4.2 CL-GD6420 CL-GD6420 Extension Register Table The extensions are enabled by GR0A. These extensions are different than CL-GD510/520 CL-GD510/520, CL-GD610/620 CL-GD610/620, CL-GD5320 CL-GD5320 and CL-GD6340 CL-GD6340 extension registers, which were at 3C4/3C5 in the Sequencer Indexed Registers address space. Abbr. Extension Register Bits GRX GR0A ARXER CR11B7X CR11B7X CR09X CR09X CR0AX CR0BX CR14X CR14X ­ VOVF35 VOVF35 VTOT35 VTOT35 VRTCS35 VRTCS35 VRTCE35 VRTCE35 VBLKS35 VBLKS35 VBLKE35 VBLKE35 LRHTH HRHT LRHBS HRHBS LRHBE HRHBE LRHRS HRHRS LRHBE HRHBE VOVF40 VOVF40 VTOT40 VTOT40 VRTCS40 VRTCS40 VRTCE40 VRTCE40 VBLKS40 VBLKS40 VBLKE40 VBLKE40 Graphics Extensions Register Index Extension Control ARX Unique Read/Write with Toggle CR11 Bit 7 at Extension Cell Height Extension Cursor Start Extension Cursor End Extension Underline Location Extension Reserved Vertical Overflow Register for 350-Line Modes Vertical Total for 350-Line Modes Vertical Retrace Start for 350-Line Modes Vertical Retrace End for 350-Line Modes Vertical Blank Start for 350-Line Modes Vertical Blank End for 350-Line Modes Horizontal Total for Low-Resolution Modes Horizontal Total for High-Resolution Modes Horizontal Blanking Start for Low-Resolution Modes Horizontal Blanking Start for High-Resolution Modes Horizontal Blanking End for Low-Resolution Modes Horizontal Blanking End for High-Resolution Modes Horizontal Retrace Start for Low-Resolution Modes Horizontal Retrace Start for High-Resolution Modes Horizontal Retrace End for Low-Resolution Modes Horizontal Retrace End for High-Resolution Modes Vertical Overflow Register for 400-Line Modes Vertical Total for 400-Line Modes Vertical Retrace Start for 400-Line Modes Vertical Retrace End for 400-Line Modes Vertical Blank Start for 400-Line Modes Vertical Blank End for 400-Line Modes [7:0] [0] [7, 5:0] [7] [7:0] [5:0] [6:0] [6:0] ­ [7:0] [7:0] [7:0] [3:0] [7:0] [3:0] [7:0] [7:0] [7:0] [7:0] [4:0] [4:0] [7:0] [7:0] [4:0] [4:0] [7:0] [7:0] [7:0] [3:0] [7:0] [3:0] 20 DATA BOOK Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W ­ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reg/ Index ­ 0A 0B 0C 30 31 32 33 39-49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F Port Addr. 3CE 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller 4.2 CL-GD6420 CL-GD6420 Extension Register Table (cont.) Abbr. Extension Register Bits HTX HBSX HBEX HRSX HREX ­ VOVF48 VOVF48 VTOT48 VTOT48 VRTCS48 VRTCS48 VRTCE48 VRTCE48 VBLKS48 VBLKS48 VBLKE48 VBLKE48 VTX VDEX VBSX VBEX VRSX VREX ­ CR07X CR07X VOVFL ­ HVPOL DM CCLK WRC CLK VSW CRTCTST ­ CRTCBC VMCC CBC FONTC Horizontal Total Extension Horizontal Blank Start Extension Horizontal Blank End Extension Horizontal Retrace Start Extension Horizontal Retrace End Extension Reserved Vertical Overflow Register for 480-Line Modes Vertical Total for 480-Line Modes Vertical Retrace Start for 480-Line Modes Vertical Retrace End for 480-Line Modes Vertical Blank Start for 480-Line Modes Vertical Blank End for 480-Line Modes Vertical Total Extension Vertical Display Enable Extension Vertical Blank Start Extension Vertical Blank End Extension Vertical Retrace Start Extension Vertical Retrace End Extension Reserved CR07 Extension Register Vertical Overflow Beyond CR07 Reserved CRTC Control Display Mode Register Character Clock Register Write Control Register Clock Select Virtual Switch Source CRTC Test Register Reserved CRTC BIOS Configuration Register VMC Control CRT Circular Buffer Policy Selection Font Control [7:0] [7:0] [7, 4:0] [7:0] [7:0] ­ [7:0] [7:0] [7:0] [3:0] [7:0] [3:0] [7:0] [7:0] [7:0] [7:0] [7:0] [3:0] ­ [7:0] [4:0] ­ [7:0] [7:2, 0] [7:0] [6:0] [7, 5:2] [4:0] [6:1] ­ [1:0] [7:5, 3:0] [7:5, 3:0] [7:5, 3] July 1993 Read/ Write R/W R/W R/W R/W R/W ­ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ­ R/W R/W ­ R/W R/W R/W R/W R/W R/W R/W ­ R/W R/W R/W R/W Reg/ Index 60 61 62 63 64 65-69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76-77 78 79 7A-7F 80 81 82 83 84 85 86 87-8E 87-8E 8F 90 91 92 DATA BOOK Port Addr. 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 21 CL-GD6420 CL-GD6420 Notebook VGA Controller 4.2 CL-GD6420 CL-GD6420 Extension Register Table (cont.) Abbr. Extension Register Bits ­ DELTA VMCTST MONSW PANCF PUDCF VMCF MMCF MONID ­ BIUC TTC BIOSPG ­ WAIT GIO FCER CACHE DREV MREV ­ SCR5:0 ATTC CURS GRL0:3 ­ DACPW GATST Reserved CRT Circular Buffer Delta and Burst VMC Test Register Monitor Switch Read-back Panel Type Configuration Bits Pullup/Down Configuration Bits Video Memory Configuration Bits Misc. Pin Configuration Bits PS/2 Monitor ID Read-back Reserved BIU Control Tristate and Test Control BIOS Page Selection Reserved Wait State Control General I/O Register FC[1:0] Pins Extensions BIU Cache Control Design Revision Mask Revision Reserved Scratch Registers 5:0 Attribute Control Cursor Attributes Graphics Controller Memory Latches Reserved DAC Power Control Register Graphics and Attribute Test Register ­ [7:0] [7:0] [7:4] [7:0] [7,4,3,0] [7:6, 4:3] [6:3, 1:0] [7:5] ­ [7,4,3,0] [7:6, 3:0] [2:0] ­ [7, 5:0] [7, 3:1] [3:0] [6:0] [7:0] [7:0] ­ [7:0] [3:0] [5, 3:0] [7:0] ­ [7:0] [4, 2:0] ­ R/W R/W R/W R/W R R/W R/W R/W ­ R/W R/W R/W ­ R/W R/W R/W R/W R/W R/W ­ R/W R/W R/W R/W ­ R/W R/W 93-94 95 96 97 98 99 9A 8B 9C 9D-9F A0 A1 A2 A3-A5 A6 A7 A8 A9 AA AB AC-B9 BA-BF C0 C1 C2-C5 C6-C7 C8 C9 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF Reserved ­ ­ CA-CF 3CF ­ 22 DATA BOOK Read/ Write Reg/ Index Port Addr. July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller 4.3 CL-GD6420 CL-GD6420 Flat Panel Extension Register Table Abbr. Extension Register Bits COLOFF PNHDE ROWOFF PRST PNOVFL ATTLCD GROFF RLLCLK FRCLR ACMOD FRBC PWSTIM COLLCD ­ Flat Panel Column Offset Flat Panel Horizontal Displayed Flat Panel Row Offset Extended in ER7C Panel Row Segment Total Flat Panel Overflow Attribute LCD Control Grayscale Offset LCD Retrace LLCLK Frame Color AC Modulation Frame Buffer Control Power Save Timer Color LCD Control Register Reserved [7:0] [7:0] [7:0] [7:0] [6:0] [7:0] [7:6, 2:1] [7:0] [4:0] [7:0] [7:1] [7:0] [2:0] ­ July 1993 Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ­ Reg/ Index D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD-DF DATA BOOK Port Addr. 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 23 CL-GD6420 CL-GD6420 Notebook VGA Controller 4.4 CL-GD6420 CL-GD6420 Memory Map Summary Table Address VGA Port 3B4 CRTC Index MP (R/W) 3B5 CRTC Data MP (R/W) 3C0 Attribute Controller Index (R/W)/Data (W) 3C1 Attribute Controller Data (R) in VGA Attribute Controller Data (R/W) in EGA 3C2 Miscellaneous Output (W); Feature (R) 3C3 Motherboard Sleep Address (R/W) (in address space only, if switch is enabled) 3C4 Sequencer (R/W) 3C5 Sequencer (R/W) 3C6 RAMDAC Pixel Mask 3C7 RAMDAC Address Register Read Mode (W) RAMDAC Status Register 3C8 RAMDAC Address Register Write Mode 3C9 RAMDAC Data 3CA Feature Control (R) 3CC Miscellaneous Output (R) 3CE Graphics Controller and Extensions Index (R/W) 3CF Graphics Controller and Extensions Data (R/W) 3D4 CRTC Index (R/W) 3D5 CRTC Data (R/W) 3DA Feature Control (W), Display Status (R) 46E8 AT Adapter Sleep Address (R/W) (if switch enabled) 24 DATA BOOK July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller 4.5 Modes Supported During CRT Display Table IBM Standard VGA Modes Mode No. Number of Colors Char. x Row Char. Cell Screen Format Display Mode Dot Clock MHz Horiz. Freq. kHz Vert. Freq. Hz Monitor Supported 0,1 16/256K 16/256K 40 x 25 9 x 16 360 x 400 Text 28 31.5 70 All 2,3 16/256K 16/256K 80 x 25 9 x 16 720 x 400 Text 28 31.5 70 All 4,5 4/256K 4/256K 40 x 25 8x8 320 x 200 Graphics 25 31.5 70 All 6 2/256K 2/256K 80 x 25 8x8 640 x 200 Graphics 25 31.5 70 All 7 Mono. 80 x 25 9 x 16 720 x 400 Text 28 31.5 70 All d 16/256K 16/256K 40 x 25 8x8 320 x 200 Graphics 25 31.5 70 All e 16/256K 16/256K 80 x 25 8 x 14 640 x 200 Graphics 25 31.5 70 All f Mono. 80 x 25 8 x 14 640 x 350 Graphics 25 31.5 70 All 10 16/256K 16/256K 80 x 25 8 x 14 640 x 350 Graphics 25 31.5 70 All 11 2/256K 2/256K 80 x 30 8 x 16 640 x 480 Graphics 25 31.5 60 All 12 16/256K 16/256K 80 x 30 8 x 16 640 x 480 Graphics 25 31.5 60 All 13 256/256K 256/256K 40 x 25 8x8 320 x 200 Graphics 25 31.5 70 All Cirrus Logic Extended Video Modes (Modes supported during CRT only display) 2D 256/256K 256/256K 80 x 25 8 x 16 640 x 400 Graphics 25 31.5 70 All 2E 256/256K 256/256K 80 x 30 8 x 16 640 x 480 Graphics 25 31.5 60 All 30 256/256K 256/256K 100 x 37 8 x 16 800 x 600 Graphics 40 37.8 60 Multifrequency 37* 16/256K 16/256K 128 x 48 8 x 16 1024 x 768 Graphics 44.9 35.5 87* Multifrequency 41 16/256K 16/256K 100 x 50 8x8 800 x 400 Text 32 31.5 60 All 42 16/256K 16/256K 100 x 60 8x8 800 x 480 Text 32 31.5 60 All 44 16/256K 16/256K 100 x 25 8 x 16 800 x 400 Text 32 31.5 70 All 51 16/256K 16/256K 132 x 50 8x8 1056 x 400 Text 40 31.5 70 All 52 16/256K 16/256K 132 x 60 8x8 1056 x 480 Text 40 31.5 60 All 53 16/256K 16/256K 80 x 60 8x8 640 x 480 Text 25 31.5 60 All 54 16/256K 16/256K 132 x 25 8 x 16 1056 x 400 Text 40 31.5 60 All 64,6a 16/256K 16/256K 100 x 37 8 x 16 800 x 600 Graphics 40 37.8 60 Multifrequency NOTES: - `All' refers to PS/2-compatible monitors supporting a horizontal sync frequency of 31.5 kHz. - `Multifrequency' refers to monitors supporting variable horizontal sync frequencies ranging from 15 kHz to 50 kHz. - * This mode is interlaced. - This table represents video modes supported in the Cirrus Logic Video BIOS for the CL-GD6420 CL-GD6420. Supported video modes may be different when using other video BIOS vendors. July 1993 DATA BOOK 25 CL-GD6420 CL-GD6420 Notebook VGA Controller 4.6 Modes Supported During LCD Display Table IBM Standard VGA Modes Mode No. Mono. STN Number of Shades Color TFT Number of Colors CRT Number of Colors Char. x Row Char. Cell Number of Pixels Expanded Char. Cell 0,1 16/16 16/512 16/256K 16/256K 40 x 25 9 x 16 360 x 400 16x19 2,3 16/16 16/512 16/256K 16/256K 80 x 25 9 x 16 720 x 400 4,5 4/64 4/512 4/256K 4/256K 40 x 25 8x8 320 x 200 6 2/16 2/512 2/256K 2/256K 80 x 25 8x8 640 x 200 NA 7 2/16 2/512 Mono. 80 x 25 9 x 16 720 x 400 8x19 d 16/64 16/512 16/256K 16/256K 40 x 25 8x8 320 x 200 NA e 16/16 16/512 16/256K 16/256K 80 x 25 8 x 14 640 x 200 NA Expand Size Display Mode SimulSCAN 640 x 475 Text Yes, PS/2 8x16 640 x 475 Text Yes, PS/2 NA 640 x 475 Graphics Yes, PS/2 640 x 475 Graphics Yes, PS/2 640 x 475 Text Yes, PS/2 640 x 475 Graphics Yes, PS/2 640 x 475 Graphics Yes, PS/2 f 2/16 2/512 Mono. 80 x 25 8 x 14 640 x 350 NA 640 x 475 Graphics Yes, PS/2 10 16/16 16/512 16/256K 16/256K 80 x 25 8 x 14 640 x 350 NA 640 x 475 Graphics Yes, PS/2 11 2/16 2/512 2/256K 2/256K 80 x 25 8 x 16 640 x 480 NA 640 x 480 Graphics Yes, PS/2 12 16/16 16/512 16/256K 16/256K 80 x 25 8 x 16 640 x 480 NA 640 x 480 Graphics Yes, PS/2 13 64/64 256/24K 256/24K 256/256K 256/256K 40 x 25 8x8 320 x 200 NA 640 x 475 Graphics Yes, PS/2 Cirrus Logic Extended Video Modes 2D 16/16 256/512 256/256K 256/256K 80 x 25 8 x 16 640 x 400 NA 640 x 475 Graphics Yes, PS/2 2E 16/16 256/512 256/256K 256/256K 80 x 25 8 x 16 640 x 480 NA 640 x 480 Graphics Yes, PS/2 53 16/16 16/512 16/256K 16/256K 80 x 60 8x8 640 x 480 NA 640 x 480 Text Yes, PS/2 NOTE: - This table represents video modes supported in the Cirrus Logic Video BIOS for the CL-GD6420 CL-GD6420. Supported video modes may be different when using other video BIOS vendors. 26 DATA BOOK July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller 5. ELECTRICAL SPECIFICATIONS 5.1 Absolute Maximum Ratings Ambient temperature under bias. 0o C to 70o C Storage temperature . -65o C to 150o C Voltage on any pin with respect to ground .-0.5 to VCC + 0.5 Volts Operating power dissipation.1.000 Watt Standby power dissipation .0.100 Watt Suspend power dissipation .0.020 Watt Power supply voltage . 7 Volts Injection current (latch-up) . 25 mA NOTE: Stresses above those listed may cause permanent damage to system components. These are stress ratings only. Functional operation at these or any conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect system reliability. July 1993 DATA BOOK 27 CL-GD6420 CL-GD6420 Notebook VGA Controller 5.2 CL-GD6420 CL-GD6420 DC Specifications (Digital) (VCC = 5V ± 10%, TA = 0o to 70o C, unless otherwise specified) Symbol Parameter MIN MAX Units VCC Power Supply Voltage 4.50 5.50 V VIL Input Low Voltage 0 0.8 V VIH Input High Voltage 2.0 VCC + 0.5 V VIHC Input High Voltage CMOS 3.0 VCC + 0.5 V VILC Input Low Voltage CMOS 1.5 V VOHC Output High Voltage CMOS VOLC Output Low Voltage CMOS ICC Operating Supply Current IL Input Leakage CIN COUT Conditions Normal Operation V IOHC = -200 µA V IOLC = 3.2 mA mA 5V nominal 10.0 µA 0 < VIN < VCC Input Capacitance 10.0 pF Output Capacitance 10.0 pF 3.5 0.4 180.0 -10.0 NOTES: IOL MAX for IOCHRDY, MEMCS16 MEMCS16* = 24 mA. IOL MAX for CRTINT = 12 mA. IOL MAX for CPU DATA, DIR, WE*, CAS* = 8 mA. IOL MAX for LCD Control Signals = 4 mA. 28 DATA BOOK July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller 5.3 CL-GD6420 CL-GD6420 DC Specifications (RAMDAC) (VCC = 5V ± 10%, TA = 0o to 70o C, unless otherwise specified) Symbol Parameter MIN MAX VCC/AVDD Power Supply Voltage 4.50 5.50 IREF DAC Reference Current IDD Operating Supply Current Conditions V Normal Operation -10 mA Notes 1 and 2 100.0 -6.7 Units mA Note 3 NOTES: 1) Reference currents below the minimum specified may cause the analog output to become invalid. 2) The pixel clock frequency must be stable for a period of 20 µS after power-up before proper device operation. 3) IDD is dependent upon the digital output loading and pixel clock rate. The value specified is with the outputs unloaded and the pixel clock frequency equal to 33 MHz. 5.4 DAC Characteristics Symbol Parameter MIN R Resolution 6 Vomax Output Voltage Iomax Output Current tr Rise Time ts Full-scale settling time MAX Units Conditions Bits 0.75 V IO < 10 mA mA Vo < 1V 8 ns Note 1 25 ns Notes 1 and 2 -21 NOTES: 1) Load = 37.5 ohms + 30 pF and IREF = -6.7 mA. 2) From a 2% change in output voltage until settling within 2% of the final value. July 1993 DATA BOOK 29 CL-GD6420 CL-GD6420 Notebook VGA Controller 6. AC TIMING CHARACTERISTICS This section includes system timing requirements for the CL-GD6420 CL-GD6420. Timings are provided in nanoseconds (ns), at TTL input levels, with the ambient temperature varying from 0 to 70° C, and VCC varying from 4.50 to 5.50V DC. The AT bus speed is 12.5 MHz unless otherwise noted. Note that (*) denotes an active-low signal. 1. All timings assume a load of 50 pF. 2. TTL signals are measured at TTL threshold; CMOS signals are measured at CMOS threshold. 3. On power-up, all DRAM interface signals are inactive. Memory data bus is in Input Mode to sense values on configuration option pins set by pull-up or pull-down resistors. 4. The CL-GD6420 CL-GD6420 executes eight RAS*-only cycles to initialize DRAMs before executing normal cycles. 30 DATA BOOK July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller 6.5 Index of Timing Information Table/Figure Title Page 6­1 I/O Write Timing (ISA Bus). 32 6­2 I/O Read Timing (ISA Bus. 33 6­3 Memory Write Timing (ISA Bus) . 34 6­4 Memory Read Timing (ISA Bus) . 35 6­5 MEMCS16 MEMCS16* Timing (ISA Bus). 36 6­6 BALE Timing (ISA Bus). 37 6­7 IOCHRDY Timing for Memory Access (ISA Bus) . 38 6­8 IOCHRDY Timing for I/O Access (ISA Bus). 39 6­9 REFRESH* Timing (ISA Bus) . 39 6­10 DSELH* and DIR Timing for 8-Bit Read Access (ISA Bus) . 40 6­11 DSELH* and DIR Timing for 16-Bit Read Access (ISA Bus) . 41 6­12 DSELH* Timing for Write Access (ISA Bus) . 41 6­13 BIOS-ROMEN* Timing (ISA Bus) . 42 6­14 AEN Timing (ISA Bus) . 42 6­15 Random Read/Write Cycle Timing. 43 6­16 Fast Page Mode Read/Write Cycle Timing . 46 6­17 CAS*-Before-RAS* Refresh Cycle Timing . 48 6­18 Clocks . 49 6­19 Sync, BLANK*, and RGB as Outputs (Internal VDCLK) . 50 6­20 Suspend Mode Timing . 51 6­21 Programmable Pins Output Timing . 52 6­22 Frame-Accelerator Interface Timing . 53 6­23 Monochrome LCD Interface Timing . 55 6­24 512-Color LCD Interface Timing . 57 July 1993 DATA BOOK 31 CL-GD6420 CL-GD6420 Notebook VGA Controller Table 6­1. I/O Write Timing (ISA Bus) Symbol Parameter MIN tWAS Address to IOW* active setup tWDH MAX Unit 40 ns Data hold time from IOW* inactive 0 ns tWAH Address hold time from IOW* inactive 0 ns tWDD Data delay from IOW* active 0 tWP IOW* pulse width tWI IOW* inactive to any command 70 ns 320 ns 80 ns NOTES: 1) AEN must be inactive (See Figure 6­14, AEN Timing). 2) See Figure 6­11 for DSELH* timing. 3) See Figure 6­8 for IOCHRDY timing. IOW* Address Data tWAS tWAH tWDH tWI tWDD tWP Figure 6­1. I/O Write Timing (ISA Bus) 32 DATA BOOK July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller Table 6­2. I/O Read Timing (ISA Bus) Symbol Parameter MIN MAX 10 Unit tRRA Address setup to IOR* active ns tRDH Data hold time from IOR* inactive 0 tRAH Address hold from IOR* inactive 0 tRDD Data delay from IOR* active tRP IOR* pulse width tRZ IOR* active to data active delay tRTZ IOR* active to tristate delay 30 ns tDDI Data delay from IOCHRDY active 25 ns 30 ns ns 220 ns 320 ns 0 ns NOTES: 1) AEN must be inactive. 2) See Figure 6­12 for DSELH* and DIR timing. 3) See Figure 6­8 for IOCHRDY timing. tDDI IOCHRDY IOR* Address Data tRRA tRZ tRDH tRDD tRP tRAH tRTZ Figure 6­2. I/O Read Timing (ISA Bus) July 1993 DATA BOOK 33 CL-GD6420 CL-GD6420 Notebook VGA Controller Table 6­3. Memory Write Timing (ISA Bus) Symbol Parameter MIN MAX tMWAS Address to MEMW* active setup 10 ns tMWDH Data hold from MEMW* inactive 0 ns tMWAH Address hold from MEMW* inactive 0 ns tMWDD Data delay from MEMW* active tMWP MEMW* pulse width tMWI MEMW* to any command 40 Unit ns 155 ns 80 ns NOTES: 1) See Figure 6­12 for DSELH* timing. 2) See Figure 6­5 for MEMCS16 MEMCS16* timing. 3) See Figure 6­7 for IOCHRDY timing. MEMW* Address Data tMWAS tMWDH tMWAH tMWDD tMWP tMWI Figure 6­3. Memory Write Timing (ISA Bus) 34 DATA BOOK July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller Table 6­4. Memory Read Timing (ISA Bus) Symbol Parameter MIN tMRAS Address to MEMR* active 0 tMRDH Data hold from MEMR* inactive 0 tMRAH Address hold from MEMR* inactive 0 tMRDI Data delay from IOCHRDY active tMRP MEMR* pulse width tMRZ MEMR* active to data active delay tMRTZ MAX MEMR* inactive to tristate delay Unit ns 30 ns ns 60 2100 375 ns ns 0 ns 30 ns NOTES: 1) See Figure 6­10 for DSELH* and DIR timing. 2) See Figure 6­5 for MEMCS16 MEMCS16* timing. 3) See Figure 6­7 for IOCHRDY timing. IOCHRDY MEMR* Address Data tMRAH tMRAS tMRDI tMRDH tMRTZ tMRZ tMRP Figure 6­4. Memory Read Timing (ISA Bus) July 1993 DATA BOOK 35 CL-GD6420 CL-GD6420 Notebook VGA Controller Table 6­5. MEMCS16 MEMCS16* Timing (ISA Bus) Symbol Parameter MIN MAX Unit tMAD MEMCS16 MEMCS16* active delay from address 26 ns tMID MEMCS16 MEMCS16* inactive delay from address 45 ns Address Non-VGA Address VGA Address MEMCS16 MEMCS16* tMID tMAD Figure 6­5. MEMCS16 MEMCS16* Timing (ISA Bus) 36 DATA BOOK July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller Table 6­6. BALE Timing (ISA Bus) Symbol Parameter MIN MAX Unit tLAS Address setup to BALE 20 ns tLBS SBHE* setup to BALE 20 ns tLAH Address hold from BALE 20 ns tLBH SBHE* hold from BALE 20 ns LA23:17 BALE BHE* tLAS tLBS tLAH tLBH Figure 6­6. BALE Timing (ISA Bus) July 1993 DATA BOOK 37 CL-GD6420 CL-GD6420 Notebook VGA Controller Table 6­7. IOCHRDY Timing for Memory Access (ISA Bus) Symbol tMA Parameter MIN IOCHRDY inactive pulse width tIMA IOCHRDY active from MEMR* or MEMW* active for one additional wait state: 16-bit access 100 ns ns 2100 tILP Unit 230 40 MEMW* or MEMR* active to IOCHRDY inactive: 8-bit access 16-bit access MAX ns 140 ns MEMW* or MEMR* IOCHRDY tMA tIMA tILP Figure 6­7. IOCHRDY Timing for Memory Access (ISA Bus) 38 DATA BOOK July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller Table 6­8. IOCHRDY Timing for I/O Access (ISA Bus) Symbol Parameter tIIA MIN IOCHRDY inactive pulse width tIIH IOCHRDY active from IOR* or IOW* active for one additional wait state: 8-bit access 300 ns 2100 tILP Unit 190 IOR* or IOW* active to IOCHRDY inactive: 8-bit access MAX ns 340 ns MAX Unit IOR* or IOW* IOCHRDY tIIA tIIH tILP Figure 6­8. IOCHRDY Timing for I/O Access (ISA Bus) Table 6­9. REFRESH* Timing (ISA Bus) Symbol Parameter MIN tRMA REFRESH* active setup to MEMR* active 20 ns tRHM REFRESH* active hold from MEMR* inactive -10 ns REFRESH* MEMR* tRHM tRMA Figure 6­9. REFRESH* Timing (ISA Bus) July 1993 DATA BOOK 39 CL-GD6420 CL-GD6420 Notebook VGA Controller Table 6­10. DSELH* and DIR Timing for 8-Bit Read Access (ISA Bus) Symbol Parameter MIN MAX Unit tCD8 Command active to Buffer Control active 40 ns tICD8 Command inactive to Buffer Control inactive 20 ns MEMR* or IOR* DSELH* and DIR tCD8 tICD8 Figure 6­10. DSELH* and DIR Timing for 8-Bit Read Access (ISA Bus) 40 DATA BOOK July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller Table 6­11. DSELH* and DIR Timing for 16-Bit Read Access (ISA Bus) Symbol Parameter MIN MAX Unit tCD16 Command active to Buffer Control active 40 ns tICD16* Command inactive to Buffer Control inactive 20 ns MEMR* tICD16* DSELH*, DIR tCD16 NOTE: *: DSELH* stays low until the beginning of the next read access. Figure 6­11. DSELH* and DIR Timing for 16-Bit Read Access (ISA Bus) Table 6­12. DSELH* Timing for Write Access (ISA Bus) Symbol Parameter MIN MAX Unit tCDS Command active to DSELH* active 40 ns tICDS Command inactive to DSELH* inactive 20 ns MEMR* or IOR* DSELH* tCDS tICDS Figure 6­12. DSELH* Timing for Write Access (ISA Bus) July 1993 DATA BOOK 41 CL-GD6420 CL-GD6420 Notebook VGA Controller Table 6­13. BIOS-ROMEN* Timing (ISA Bus) Symbol Parameter MIN MAX Unit tRAM BIOS-ROMEN* active delay from MEMR* active 30 ns tRIM BIOS-ROMEN* inactive delay from MEMR* inactive 30 ns NOTE: Address to MEMR* setup and hold indicated in Figure 6­4 must be met. MEMR* BIOS-ROMEN* tRAM tRIM Figure 6­13. BIOS-ROMEN* Timing (ISA Bus) Table 6­14. AEN Timing (ISA Bus) Symbol Parameter MIN MAX Unit tASI AEN active setup to IOR* or IOW* active 20 ns tAHI AEN hold from IOR* or IOW* active 0 ns AEN IOW* or IOR* tASI tAHI Figure 6­14. AEN Timing (ISA Bus) 42 DATA BOOK July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller Table 6­15. Random Read/Write Cycle Timing Symbol Parameter MIN MAX Unit tASR Address setup time to RAS* 5 ns tASC Address setup time to CAS* 5 ns tRCD RAS* to CAS* delay time 2.5 TC tRAH Row address hold time 1 TC tCAH Column address hold time 1 TC tRCS Read command setup time 5 ns tDZO Data valid from OE* low * 1.5 TC tDZR Data valid from RAS* low * 4 TC tDZC Data valid from CAS* low * 1.5 TC tDZCA Data valid from column address 2.0 TC tDTO Data tristate from OE* high * * ns tRPN RAS* precharge time 3 TC tCR Read-write cycle time (random cycle) 7 TC tRHC Read command hold from CAS* high 0.5 TC tRHR Read command hold from RAS* high 1 TC tRZO RAS* hold time from OE* low 2 TC tCPN CAS* precharge time 0.5 TC tWSC WE* setup time to CAS* 0.5 TC tWHC WE* hold time from CAS* low 0.5 TC tWP WE* pulse width 1 TC tDSC Write data setup to CAS* 5 ns tDHC Write data hold from CAS* 1 TC tT Transition time July 1993 5 ns DATA BOOK 43 CL-GD6420 CL-GD6420 Notebook VGA Controller Table 6-15. Random Read/Write Cycle Timing (cont.) Symbol Parameter MIN MAX Unit tDHR Write data hold from RAS* low 3.5 TC tRP RAS* pulse width 4 TC tCP CAS* pulse width 1.5 TC NOTES: 1) An asterisk (*) indicates the parameter is a device-dependent value or active-low signal, as appropriate. 2) TC is one SQCLK period. 44 DATA BOOK July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller tCR tRPN tASR tT tRP RAS*[1:0] tRCD tCPN tCP CAS*[1:0] tCAH tASC tRAH tRHC AA[0:8] AB[0:8] tRHR tRCS tWSC tWP WE* tWHC tDZCA tRZO tDZO OE* tDZC tDHC tDTO M0D*[7:0] VALID M2D*[7:0] tDSC tDZR tDHR Read Cycle Write Cycle Figure 6­15. Random Read/Write Cycle Timing July 1993 DATA BOOK 45 CL-GD6420 CL-GD6420 Notebook VGA Controller Table 6­16. Fast Page Mode Read/Write Cycle Timing Symbol Parameter MIN MAX Unit tASR Address setup time to RAS* 5 ns tASC Address setup time to CAS* 5 ns tRCD RAS* to CAS* delay time 2.5 TC tRAH Row address hold time 1 TC tCAH Column address hold time 1 TC tRCS Read command setup time 5 ns tDZO Data valid from OE* low * tDZR Data valid from RAS* low tDZC Data valid from CAS* low tDZCA Data valid from column address tDTO Data tristate from OE* high * tRHC Read command hold from CAS* high 0.5 TC tWSC WE* setup time to CAS* 0.5 TC tWHC WE* hold time from CAS* low 0.5 TC tWP WE* pulse width 1 TC tDSC Write data setup to CAS* 5 ns tDHC Write data hold from CAS* 1 TC tT Transition time tCP Page Mode cycle time tCPN CAS* precharge (Page Mode) TC 4 TC 1.5 TC 2.0 * 1.5 TC * ns 5 ns 2 TC 0.5 TC NOTES: 1) An asterisk (*) indicates the parameter is a device-dependent value or active-low signal, as appropriate. 2) TC is one SQCLK period. 46 DATA BOOK July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller tASR tCP RAS*[0/1] tCPN CAS*[0/1] tRCD tCAH tASC tRAH tT tRHC AA[0:8] AB[0:8] tWSC tRCS tWP WE* tWHC tDZCA tDZO OE* tDZC M0D*[7:0] M2D*[7:0] tDHC tDTO VALID tDZR tDSC Figure 6-16. Fast Page Mode Read/Write Cycle Timing July 1993 DATA BOOK 47 CL-GD6420 CL-GD6420 Notebook VGA Controller Table 6­17. CAS*-Before-RAS* Refresh Cycle Timing Symbol Parameter MIN MAX Unit tCSR CAS* setup before RAS* 1 TC tCHR CAS* hold from RAS* 1.5 TC tRPL RAS* pulse width (low) 6 TC tRPH RAS* pulse width (high) 2 TC tRC Cycle (Refresh) 9 TC tRC RAS* CAS* tRPH tCHR tCSR tRPL Figure 6­17. CAS*-Before-RAS* Refresh Cycle Timing 48 DATA BOOK July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller Table 6­18. Clocks Symbol Parameter Unit 6 6 10 6 10 6 ns ns ns ns ns ns Fall time: SQCLK VDCLK OSC (below 25 MHz) OSC (above 25 MHz) CLKSEL[3:0] (below 25 MHz) CLKSEL[3:0] (above 25 MHz) tF MAX Rise time: SQCLK VDCLK OSC (below 25 MHz) OSC (above 25 MHz) CLKSEL[3:0] (below 25 MHz) CLKSEL[3:0] (above 25 MHz) tR MIN 6 6 10 6 10 6 ns ns ns ns ns ns High Period (Note 1): SQCLK VDCLK OSC CLKSEL[3:0] tL -5% -5% -5% -5% +5% +5% +5% +5% Low Period (Note 1): SQCLK VDCLK OSC CLKSEL[3:0] tH -5% -5% -5% -5% +5% +5% +5% +5% NOTE: The percentages for High and Low Period indicate permissible deviation from tCP/2. tF tR tH tL tCP Figure 6­18. Clocks July 1993 DATA BOOK 49 CL-GD6420 CL-GD6420 Notebook VGA Controller Table 6­19. Sync, BLANK*, and RGB as Outputs (Internal VDCLK) Symbol Parameter MIN MAX Unit tVBD VDCLK to BLANK* delay 3 7 ns tVPD VDCLK to P[7:0] delay 3 7 ns tVHD VDCLK to HSYNC, VSYNC delay 0 5 ns tAND VDCLK to R, G, B delay 0 30 ns VDCLK BLANK* P[7:0] HSYNC, VSYNC R, G, B tVBD tVPD tVHD tAND Figure 6­19. Sync, BLANK*, and R, G, B as Outputs (Internal VDCLK) 50 DATA BOOK July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller Table 6­20. Suspend Mode Timing Symbol Parameter MIN MAX Unit 20 200 ns tCSR CAS* setup to RAS* low tCHR CAS* hold after RAS* low 100 1000 ns tCL CAS* low time 120 1000 ns tRL RAS* low time 120 1000 ns tREF Refresh period (normal) TSUSP/2 ns tREF Refresh period (slow) TSUSP*4 ns Suspend Clock (32 kHz) tSUSP CAS* RAS* tCSR tCHR tRL tCL tREF Figure 6­20. Suspend Mode Timing July 1993 DATA BOOK 51 CL-GD6420 CL-GD6420 Notebook VGA Controller Table 6­21. Programmable Pins Output Timing Symbol tDWO Parameter MIN Unit 0 Delay from IOW* inactive to output valid MAX 100 ns NOTE: The programmable pins include PO1, PO2, FC[0]/FPVCC, FC[1]/FPVEE, and CLKSEL[3:0] in Output Mode. CLKSEL[3:0] is in Output Mode at power-on. IOWR* tDWO PO1, PO2, FC[0]/FPVCC, FC[1]/FPVEE, CLKSEL[3:0] Figure 6­21. Programmable Pins Output Timing 52 DATA BOOK July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller Table 6­22. Frame-Accelerator Interface Timing Symbol Parameter tFRS Row Address valid setup to FRRAS* active tFRH Row Address hold from FRRAS* active tFOD Read Data delay from FROE* active tFCS MIN MAX Unit 2 TC ns 0.5 TC ns 5 ns Column Address valid setup to FRCAS* active 0.5 TC -5 ns tFCH Column Address valid hold after FRCAS* active 0.5 TC -5 ns tFODH Read Data hold after FROE* inactive 2 tFODS Read Data setup to FROE* inactive 5 ns tFCOS FRCAS* active delay to FROE* active 0.5 TC ns tFOE FROE* active pulse width 1 TC ns tFWS Write Data setup to FRWE* active 0.5 TC -10 ns tFWH Write Data hold from FRWE* inactive 0.5 TC -5 0.5 TC + 5 ns tFWA FRWE* active time 0.5 TC -5 0.5 TC + 5 ns tFCC FRCAS* cycle time 4 TC ns tFCI FRCAS* inactive time 1 TC -5 ns tFCA FRCAS* active time 3 TC -5 ns tFRI FRRAS* inactive time 12 TC -5 ns tFRA FRRAS* active time 641 TC -5 ns 0.5 TC ns NOTE: TC = FPVDCLK period. July 1993 DATA BOOK 53 CL-GD6420 CL-GD6420 Notebook VGA Controller FRD[3:0] FRAD[7:0] READ DATA ROW ADDR. COL. ADDR. tFRH FRRAS* WRITE DATA READ DATA WRITE DATA READ DATA READ DATA COL. ADDR. WRITE DATA WRITE DATA tFODS tFRS tFCS tFRA tFRI tFCH FRCAS* tFODH tFOD FROE* tFCI tFCA tFCOS tFWH tFOE tFWS FRWE* tFCC tFWA Figure 6­22. Frame-Accelerator Interface Timing 54 DATA BOOK July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller Table 6­23. Monochrome LCD Interface Timing Symbol Parameter tFODH Read Data hold after FROE* inactive tKP LLCLK pulse width tKLK MIN 2 MAX 0.5TC Unit ns TC ns FPVDCLK low setup to LLCLK TC + 20 ns tKC FPVDCLK cycle time TC - 10 ns tKH FPVDCLK high time 0.5 TC - 10 ns tKF FPVDCLK fall time 10 ns tKR FPVDCLK rise time 10 ns tKHL FPVDCLK low hold time after LLCLK low tVDS TC -20 ns Video data setup time 0.5 TC - 20 ns tVDH Video data hold time 0.5 TC - 20 ns tLHK LFS high hold time after LLCLK low TC ns tLSK LFS high setup to LLCLK low TC ns tMDK MOD delay from LLCLK high 30 ns NOTE: TC = 24 MHz/4. July 1993 DATA BOOK 55 CL-GD6420 CL-GD6420 Notebook VGA Controller tKP LLCLK tKLK tKC FPVDCLK tKHL tKH tFLT tKF tKR tVDS PIXEL DATA tVDH tLHK LFS tLSK MOD tMDK Figure 6­23. Monochrome LCD Interface Timing 56 DATA BOOK July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller Table 6­24. 512-Color LCD Interface Timing Symbol Parameter tKP HSYNC pulse width tKC FPVDCLK cycle time tKH FPVDCLK high time tKL FPVDCLK low time tKF MIN MAX Unit 90 1.05 TC TC 0.5 TC -5 0.5 TC + 5 TC 0.5 TC -5 0.5 TC + 5 TC FPVDCLK fall time 10 ns tKR FPVDCLK rise time 10 ns tVDS Video data setup time 10 ns tVDH Video data hold time 10 ns tKLK FPVDCLK low to HSYNC active 0.5 TC tDDS Panel Data valid to FPHDE active 0 ns tDDH FPHDE inactive to FPVDCLK low 10 ns tBSD FPHDE active to FPVDCLK low 8 ns tBSH FPVDCLK low to FPHDE inactive 10 ns tBDD VSYNC inactive to valid Data 0 ns tBP VSYNC pulse width 1600 TC 0.95 TC TC NOTE: TC = FPVDCLK period. July 1993 DATA BOOK 57 CL-GD6420 CL-GD6420 Notebook VGA Controller tKP SYNC tKC FPVDCLK tKH tKLK tKR tKL tKF tVDS PIXEL DATA tBP VSYNC tVDH tBDD tBSD tDDS tBSH tDDH FPHDE Figure 6­24. 512-Color LCD Interface Timing 58 DATA BOOK July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller 7. CL-GD6420 CL-GD6420 REGISTERS The following tables list the CL-GD6420 CL-GD6420 extension registers. Extension Registers Abbreviation Register Name Index Port Page ER0A ER0B ER0C ER0D ER0E ER0F Reserved ER60 ER61 ER62 ER63 ER64 Reserved ER70 ER71 ER72 ER73 ER74 ER75 Reserved ER78 ER79 ER7A Reserved ER7C Reserved ER80 ER81 ER82 ER83 ER84 Reserved ER86 ER87 Unused ER8F ER90 ER91 ER92 ER95 ER96 Extension Control Attribute Controller Index at Extension CR11 Bit 7 at Extension CPU Base Address Control CPU Base Address Mapping Register A CPU Base Address Mapping Register B ­ Horizontal Total Extension Horizontal Blank Start Extension Horizontal Blank End Extension Horizontal Retrace Start Extension Horizontal Retrace End Extension ­ Vertical Total Extension Vertical Display Enable Extension Vertical Blank Start Extension Vertical Blank End Extension Vertical Retrace Start Extension Vertical Retrace End Extension ­ CR07 Extension Vertical Overflow Coarse Vertical Retrace Skew ­ Screen A Start Address Extension ­ H/V Retrace Polarity Control Register Display Mode Character Clock Selection Write Control Clock Select ­ CRTC Test CRTC Spare Extension (Rev. B Only) ­ CRTC BIOS Configuration Display Memory Control CRT-Circular Buffer Policy Selection Font Control CRT-Circular Buffer Delta and Burst Display Memory Control Test 0A 0B 0C 0D 0E 0F 30-5F 30-5F 60 61 62 63 64 65-6F 65-6F 70 71 72 73 74 75 76-77 78 79 7A 7B 7C 7D-7F 80 81 82 83 84 85 86 87 88-8E 88-8E 8F 90 91 92 95 96 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 62 63 64 65 67 68 ­ 69 71 72 73 74 ­ 75 76 77 78 79 80 ­ 81 82 83 ­ 84 ­ 85 86 87 88 89 ­ 91 92 ­ 93 95 97 98 99 100 July 1993 DATA BOOK 59 CL-GD6420 CL-GD6420 Notebook VGA Controller 7. CL-GD6420 CL-GD6420 REGISTERS (cont.) Abbreviation Register Name Index Port Page ER97 ER98 ER99 ER9A ER9B ER9C Reserved ERA0 ERA1 ERA2 Reserved ERA6 ERA7 Reserved ERA9 ERAA ERAB Reserved ERBA-BF ERC0 ERC1 ERC2-C5 Monitor Switches Read-back Scratch Configuration Register Display Memory Configuration Miscellaneous Configuration PS/2 Monitor ID ­ Bus Interface Unit Control Three-State and Test Control BIOS Page Selection ­ Wait State Control General I/O Controls ­ Bus Interface Cache Control Design Revision Mask Revision ­ Scratch Register 5-0 Attribute and Graphics Control Cursor Attributes Graphics Controller Memory Latches 0-3 ­ RAMDAC Control Graphics and Attribute Test ­ Flat Panel Column Offset Flat Panel Horizontal Size Flat Panel Row Offset Flat Panel Vertical Size Flat Panel Overflow Flat Panel Attribute Control Flat Panel Gray Scale Offset Flat Panel Retrace Line Clock Control Flat Panel Frame Color Flat Panel AC Modulation Flat Panel Display Control Standby Timer Control Flat Panel Color Configuration ­ 97 98 99 9A 9B 9C 9D-9F A0 A1 A2 A3-A5 A6 A7 A8 A9 AA AB AC-B9 BA-BF C0 C1 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 101 102 103 104 105 107 ­ 108 110 111 ­ 112 113 ­ 114 116 117 ­ 118 119 120 C2-C5 C6-C7 C8 C9 CA-CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD-DF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 121 ­ 122 123 ­ 124 125 126 127 128 129 131 133 134 135 136 138 139 ­ Reserved ERC8 ERC9 Reserved ERD0 ERD1 ERD2 ERD3 ERD4 ERD5 ERD6 ERD7 ERD8 ERD9 ERDA ERDB ERDC Reserved 60 DATA BOOK July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller 7.1 VGA Register Port Map Table 7­1. VGA Register Port Map Address Port 3?4 CRT Controller Index (R/W) 3?5 CRT Controller Data (R/W) 3BA Feature Control (W), Input Status Register 1 (R) (Monochrome) 3C0 Attribute Controller Index/Data (Write) 3C1 Attribute Controller Index/Data (Read) 3C2 Miscellaneous Output (W), Input Status Register 0 (R) 3C3 VGA Enable (R/W) 3C4 Sequencer Index (R/W) 3C5 Sequencer Data (R/W) 3C6 Video DAC Pixel Mask (R/W), Hidden DAC Register (R/W) 3C7 Pixel Address Read Mode (W), DAC State (R) 3C8 Pixel Mask Write Mode (R/W) 3C9 Pixel Data (R/W) 3CA Feature Control Readback (R) 3CC Miscellaneous Output Readback (R) 3CE Graphics Controller Index (R/W) 3CF Graphics Controller Data (R/W) 3DA Feature Control (W), Input Status Register 1 (R) (Color) NOTE: The `?' in an address would be `B' for monochrome and `D' for color 7.2 Register Delta List Between the CL-GD6420-A CL-GD6420-A and the CL-GD6420-B CL-GD6420-B Table 7­2. Register Delta List Register CL-GD6420-A CL-GD6420-A CL-GD6420-B CL-GD6420-B ER81[6] Not Used Used ER87[7,4] Not Used Used ER90[6] Not Used Used ER97 and ER99 Pull-Down Resistors May Be Used Pull-Down Resistors Are Not Necessary ERD6[5,4] Not Used Used ERD8[6] Not Used Used ERDA[0] Not Used Used July 1993 DATA BOOK 61 CL-GD6420 CL-GD6420 Notebook VGA Controller 7.3 7.3.1 CL-GD6420 CL-GD6420 Extended Register Details Extension Control Register: ER0A I/O Port Address: 3CF Index: 0A Bit 7(MSB) 6 5 4 3 2 1 0(LSB) Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Extensions Register Access Flag Access R/W Reset State 0 0 0 0 0 0 0 0 This register is used to enable or disable access to the Extension Registers. To enable access to the Extension Registers, write the value EC to this register. A subsequent read from this register will return the value `01', indicating access to the Extension Registers. To disable access to the Extension Registers, write the value CE to this register. A subsequent read from this register will return the value `00', indicating no access to the Extension Registers. Bit Bits 7:1 Reserved Bit 0 62 Description Extensions Register Access Flag: A `1' indicates access is allowed to the Extension Registers. DATA BOOK July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller 7.3.2 Attribute Controller Index At Extension Register: ER0B I/O Port Address: 3CF Index: 0B Bit 7(MSB) 6 5 4 3 2 1 0(LSB) Description Index/Data State of Attribute Controller Reserved Video Enable Attribute Controller Index 4 Attribute Controller Index 3 Attribute Controller Index 2 Attribute Controller Index 1 Attribute Controller Index 0 Access R/W R/W R/W R/W R/W R/W R/W Reset State 0 0 0 x x x x x This register duplicates the Attribute Controller Index Register (3C0) Bits 5-0. In addition, Bit 7 enables the program to unconditionally determine or force the state of the Index/Data Pointer. Bit Description Bit 7 Index/Data State of Attribute Controller: This bit reflects and controls the state of the Index/Data Pointer in the Attribute Controller. When the register is read, the state is returned; when the register is written, the state is forced. 0 = Index 1 = Data Bit 6 Reserved Bit 5 Video Enable: When this bit is reset to a `0', the screen displays the color indicated by Overscan Register AR11 (normally black); when set to a `1', normal video display is enabled. In the standard VGA, this bit also selects the address source for the Palette Registers (0 = CPU and 1 = Video), which requires that CPU writes to the Palette Registers only occur when this bit is a `0' (or else the data will be written to random Palette Register locations as determined by the Video Data Stream at the time of the write). In the CL-GD6420 CL-GD6420, the palette is dual-ported and may be accessed at any time, independent of the state of this bit. Bits 4:0 Attribute Controller Indexes: These five bits form the index to the Data Registers in the Attribute Controller. July 1993 DATA BOOK 63 CL-GD6420 CL-GD6420 Notebook VGA Controller 7.3.3 CR11 Bit 7 at Extension Register: ER0C I/O Port Address: 3CF Index: 0C Bit 7(MSB) 6 5 4 3 2 1 0(LSB) Description Access Write Protect CR00-CR07 CR00-CR07 R/W Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reset State 0 0 0 0 0 0 0 0 This register is used to break a deadlock between CR3 and CR11. Bit Description Bit 7 Write Protect CR00-CR07 CR00-CR07: This bit provides write protection for Registers CR00-CR07 CR00-CR07 (mostly the Horizontal Control Registers). The functionality of this bit is the same as Bit 7 of CR11h. This bit resolves the deadlock issue described in the next paragraph. If CR3[7] is reset to a `0', then CR11 no longer controls write protect for CR0-CR7. If CR11[7] is set to a `1', then CR3[7] is write protected. Since CR3[7] is write protected, CR10 and CR11 cannot be accessed as Vertical Retrace Control Registers, and in particular, CR11[7] cannot be programmed to change the write-protected state of CR3[7]. ER0C[7] is always accessible and breaks the deadlock. Bits 6:0 64 DATA BOOK Reserved July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller 7.3.4 CPU Base Address Control Register: ER0D I/O Port Address: 3CF Index: 0D Bit 7(MSB) 6 5 4 3 2 1 0(LSB) Description Reserved Reserved Reserved Reserved Reserved 2/1 Page Selection 64K/32K 64K/32K Page Size Enable Page Remapping Access Reset State 0 0 0 0 0 0 0 0 R/W R/W R/W R/W This register is write protected by ERA7[4] = 1. This register is used to control the mapping of host memory access into the Display Memory. The host has at most a 128K window (A0000h through BFFFFh) to access up to 1024K 1024K bytes of the Display Memory. This register, in conjunction with the ER0E and ER0F Registers, provides the necessary remapping. The remapping is done using an 8-bit adder. It adds the low-order 15 or 16 bits of host address with the eight bits taken from either ER0E or ER0F. Whether 15 or 16 bits are used depends on the page size. Whether ER0E or ER0F is chosen depends on the page size and number of pages. Bit 0 of the Remapping Register is aligned with Bit 12 of the CPU address. This means that the low-order 12 bits of the Display Memory Address are determined strictly by the CPU address. The high-order eight bits of the Display Memory Address are the arithmetic sum of Bits 15:12 or 14:12 of the CPU address, and Bits 7:0 of the Remapping Register. Bits 23:16 of the CPU address are ignored by the adder. Overflow is possible and is not detected. Bit alignment is shown in the following table: Table 7­2. Adder Alignment CPU Bit Register Bit 15 7 6 5 4 14 13 12 3 2 1 0 This scheme provides a 64K block beginning on any 4K boundary accessible through each of the Remapping Registers. July 1993 DATA BOOK 65 CL-GD6420 CL-GD6420 Notebook VGA Controller 7.3.4 CPU Base Address Control Register: ER0D (cont.) Bit Description Bits 7:4 Reserved Bit 2 2/1 Page Selection: If Bit 2 is reset to a `0', remapping is possible only through ER0E. If Bit 2 is set to a `1', remapping is possible through both ER0E and ER0F. Bit 1 64K/32K 64K/32K Page Size: If Bit 1 is reset to a `0', remapping is done for 32K pages. If Bit 1 is set to a `1', remapping is done for 64K pages. The following table summarizes the remapping according to the CPU address. Table 7­3. Remapping Register Selection Bit 2 Bit 1 A000A7FFF A000A7FFF A8000AFFFF A8000AFFFF B0000B7FFF B0000B7FFF B8000BFFFF B8000BFFFF 0 0 ER0E *a * * 0 1 ER0E ER0E * * 1 0 ER0E ER0F * * 1 1 ER0E ER0E ER0F ER0Fb a. (*) indicates the address is not modified in the Remapping Logic. b. To use two pages of 64K each, program GR6[3:2] to 0:0; 128K of Display Memory is selected. Bit 0 66 DATA BOOK Enable Page Remapping: If this bit is reset to a `0', the address is passed through the Remapping Logic with no modification. July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller 7.3.5 CPU Base Address Mapping Register A: ER0E I/O Port Address: 3CF Index: 0E Bit 7(MSB) 6 5 4 3 2 1 0(LSB) Description Address Offset Bit 19 Address Offset Bit 18 Address Offset Bit 17 Address Offset Bit 16 Address Offset Bit 15 Address Offset Bit 14 Address Offset Bit 13 Address Offset Bit 12 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset State 0 0 0 0 0 0 0 0 The contents of this register are added to the upper bits A[19:12] of the CPU address prior to accessing the Display Memory, if necessary. The circumstances under which this addition takes place are explained in the description of ER0D above. Bit Description Bits 7:0 Address Offset Bits: This is the 8-bit value added to the upper bits of the CPU address. July 1993 DATA BOOK 67 CL-GD6420 CL-GD6420 Notebook VGA Controller 7.3.6 CPU Base Address Mapping Register B: ER0F I/O Port Address: 3CF Index: 0F Bit 7(MSB) 6 5 4 3 2 1 0(LSB) Description Address Offset Bit 19 Address Offset Bit 18 Address Offset Bit 17 Address Offset Bit 16 Address Offset Bit 15 Address Offset Bit 14 Address Offset Bit 13 Address Offset Bit 12 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset State 0 0 0 0 0 0 0 0 The contents of this register are added to the upper bits A[19:12] of the CPU address prior to accessing the Display Memory, if necessary. The circumstances under which this addition takes place are explained in the description of ER0D above. Bit Bits 7:0 68 Description Address Offset Bits: This is the 8-bit value added to the upper bits of the CPU address. DATA BOOK July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller 7.3.7 Horizontal Total Extension Register: ER60 I/O Port Address: 3CF Index: 60 Bit 7(MSB) 6 5 4 3 2 1 0(LSB) Description Horizontal Total Extension Horizontal Total Extension Horizontal Total Extension Horizontal Total Extension Horizontal Total Extension Horizontal Total Extension Horizontal Total Extension Horizontal Total Extension Access R/W R/W R/W R/W R/W R/W R/W R/W Reset State 0 0 0 0 0 0 0 0 The registers ER60h to ER64h are grouped as the working set of CRTC horizontal monitor timing, and they always control the CRTC to drive horizontal monitor timing. These registers are the counterpart of the CRTC Standard Registers mapped into Extension Address Spaces and are totally transparent to standard VGA applications. The data sources are controlled by ER83h[1] when the working set is being updated. ER83h[1] = 0: The data will be written to both corresponding standard registers in CRTC and the registers in this working set through standard address path, 3X4h (X = D or B). ER83h[1] = 1: The working set registers can only be written from the extension address path. The corresponding standard registers in CRTC will not be changed. Bit Description Bits 7:0 Horizontal Total Extension: The value in this register is the least-significant eight bits of a 9-bit field specifying the total number of horizontal character clocks; the most-significant bit is in ER64[5]. This value includes the number of character in the active-display area and the number of characters required for the horizontal blanking period. The actual value programmed is the total number of characters in a horizontal display period minus 5. The total number of characters in a horizontal display period is calculated from dot clock, horizontal frequency, and font width. July 1993 DATA BOOK 69 CL-GD6420 CL-GD6420 Notebook VGA Controller 7.3.7 Horizontal Total Extension Register: ER60 (cont.) For example: Dot Clock = 28.322 MHz, Horizontal Frequency = 31.5 kHz, Font Width = 9 Dots. 28322/31.5 = 900 dots approximately per horizontal cycle. 900/9 = 100 characters per horizontal cycle. 100 - 5 = 95 (5Fh) to be programmed into this register. In standard VGA, horizontal total has an 8-bit value. In the CL-GD64XX CL-GD64XX family, the horizontal total is extended to up to 512-character clocks. 70 DATA BOOK July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller 7.3.8 Horizontal Blank Start Extension Register: ER61 I/O Port Address: 3CF Index: 61 Bit 7(MSB) 6 5 4 3 2 1 0(LSB) Description Horizontal Blank Start Extension Bit 7 Horizontal Blank Start Extension Bit 6 Horizontal Blank Start Extension Bit 5 Horizontal Blank Start Extension Bit 4 Horizontal Blank Start Extension Bit 3 Horizontal Blank Start Extension Bit 2 Horizontal Blank Start Extension Bit 1 Horizontal Blank Start Extension Bit 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset State 0 0 0 0 0 0 0 0 Bit Description Bits 7:0 Horizontal Blank Start Extension: The value in this register is the least-significant eight bits of a 9-bit field specifying horizontal blanking start. The most-significant bit is ER62[7]. This bit is used to indicate in character clock units, based on 0, when the Horizontal Blanking Signal becomes active. When the internal character counter reaches the value programmed into this register, blanking starts. If the Blanking Signal is activated too early, some of the display will be lost. If the Blanking Signal is activated after horizontal display enable ends; the timing gap between horizontal display enable end and horizontal blanking start will be the border. This register is also extended to nine bits instead of the eight bits available to standard VGA. July 1993 DATA BOOK 71 CL-GD6420 CL-GD6420 Notebook VGA Controller 7.3.9 Horizontal Blank End Extension Register: ER62 I/O Port Address: 3CF Index: 62 Bit 7(MSB) 6 5 4 3 2 1 0(LSB) Description Horizontal Blank Start Extension Bit 8 Reserved Reserved Horizontal Blank End Bit 4 Horizontal Blank End Bit 3 Horizontal Blank End Bit 2 Horizontal Blank End Bit 1 Horizontal Blank End Bit 0 Access R/W Bit Description Bit 7 Horizontal Blank Start Extension: This is Bit 8 of the Horizontal Blank Start Field. It serves to extend ER61, making a 9-bit field. Bits 6:5 Reserved Bits 4:0 Horizontal Blank End: These bits are used to indicate in character clocks when the Horizontal Blanking Signal becomes inactive. The value is six bits, with the most-significant bit in ER64[7]. The least-significant bits from the following formula determine the value programmed into this register: R/W R/W R/W R/W R/W Reset State 0 0 0 0 0 0 0 0 Horizontal Blanking Start (ER61 and ER62[7]) + Horizontal Blanking Width. The 6-bit value of horizontal blank end limits the length of the horizontal blanking pulse to 63 character clocks in VGA. The Blanking Signal should go inactive at least one character clock before the next Horizontal Display Signal enable. The timing gap between Blanking Signal inactive and Horizontal Display Signal active is perceived as the left border. For example, Horizontal Total Number of Characters = 100 (64h). The horizontal blanking end should be at Location 98 (62h). 72 DATA BOOK July 1993 CL-GD6420 CL-GD6420 Notebook VGA Controller 7.3.10 Horizontal Retrace Start Extension Register: ER63 I/O Port Address: 3CF Index: 63 Bit 7(MSB) 6 5 4 3 2 1 0(LSB) Description Horizontal Retrace Start Bit 7 Horizontal Retrace Start Bit 6 Horizontal Retrace Start Bit 5 Horizontal Retrace Start Bit 4 Horizontal Retrace Start Bit 3 Horizontal Retrace Start Bit 2 Horizontal Retrace Start Bit 1 Horizontal Retrace Start Bit 0 Bit Description Bits 7:0 Horizontal Retrace Start: This entire byte is the lower eight bits of the 9-bit location value of Horizontal Retrace Start. The most-significant bit is at ER64[6]. These eight bits are used to indicate the point at which the horizontal synchronization pulse becomes active. The value in the register will affect the centering of the screen horizontally. July 1993 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset State 0 0 0 0 0 0 0 0 DATA BOOK 73 CL-GD6420 CL-GD6420 Notebook VGA Controller 7.3.11 Horizontal Retrace End Extension Register: ER64 I/O Port Address: 3CF Index: 64 Bit 7(MSB) 6 5 4 3 2 1 0(LSB) Description Horizontal Blank End Bit 6 Horizontal Retrace Start Extension Bit 8 Horizontal Total Extension Bit 8 Horizontal Retrace End Bit 4 Horizontal Retrace End