CIII52001-1 EP3C10 EP3C16 EP3C40 EP3C55 EP3C80 EP3C25 EP3C120 SSTL-18 HSTL-18 - Datasheet Archive

 

Switching Characteristics CIII52001-1.3 Electrical Characteristics Operating Conditions When Cyclone® III devices are

 

1. Cyclone III Device Datasheet: DC and Switching Characteristics CIII52001-1 CIII52001-1.3 Electrical Characteristics Operating Conditions When Cyclone® III devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of Cyclone III devices, system designers must consider the operating requirements within this document. Cyclone III devices are offered in both commercial and industrial grades. Commercial devices are offered in ­6 (fastest), ­7, and ­8 speed grades. Absolute Maximum Ratings Absolute maximum ratings define the maximum operating conditions for Cyclone III devices. The values are based on experiments conducted with the device and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied at these conditions. Conditions beyond those listed in Table 1­1 may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device. All parameters representing voltages are measured with respect to ground. Table 1­1. Cyclone III Device Absolute Maximum Ratings Note (1) Symbol Parameter Min Max Unit VCCINT Supply voltage for internal logic and input buffers ­0.5 1.8 V VCCIO Supply voltage for output buffers ­0.5 3.9 V VCCA Supply (analog) voltage for PLL regulator ­0.5 3.75 V VCCD_PLL Supply (digital) voltage for PLL ­0.5 1.8 V VI DC input voltage ­0.5 3.95 V IOUT DC output current, per pin ­25 40 mA VE S D H B M Electrostatic discharge voltage using the human body model NA ±2000 V VE S D C D M Electrostatic discharge voltage using the charged device model NA ±500 V TSTG Storage temperature ­65 150 °C TJ Operating junction temperature ­40 125 °C Note to Table 1­1: (1) Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply. Maximum Allowed Overshoot/Undershoot Voltage During transitions, input signals may overshoot to the voltage shown in Table 1­2 and undershoot to ­2.0 V for input currents less than 100 mA and for periods shorter than 20 ns. Table 1­2 lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage over the lifetime of the device. The maximum allowed overshoot duration is specified as percentage of high-time over the lifetime of the device. Altera Corporation July 2007 1­1 Electrical Characteristics A DC signal is equivalent to 100% duty cycle. For example, a signal that overshoots to 4.2 V can only be at 4.2 V for 10.74% over the lifetime of the device; for device lifetime of 10 years, this amounts to 10.74/10ths of a year. Figure 1­1 shows the way to determine the overshoot duration. Table 1­2. Maximum Allowed Overshoot During Transitions over 10-Year Time Frame Symbol Parameter Condition Overshoot Duration as % of High Time Unit Vi AC Input Voltage VI = 3.95 V 100 % VI = 4.0 V 95.67 % VI = 4.05 V 55.24 % VI = 4.10 V 31.97 % VI = 4.15 V 18.52 % VI = 4.20 V 10.74 % VI = 4.25 V 6.23 % VI = 4.30 V 3.62 % VI = 4.35 V 2.1 % VI = 4.40 V 1.22 % VI = 4.45 V 0.71 % VI = 4.50 V 0.41 % VI = 4.60 V 0.14 % VI = 4.70 V 0.047 % Note to Table 1­2: (1) Figure 1­1 shows the methodology to determine the overshoot duration. In the example in Figure 1­1, overshoot voltage is shown in red and is present on the Cyclone III input pin at over 4.1 V but below 4.2 V. From Table 1­1, for an overshoot of 4.1 V the percentage of high time for the overshoot can be as high as 31.97 % over a 10-year period. Percentage of high time is calculated as (delta T)/T) × 100. This 10-year period assumes the device is always turned on with 100% I/O toggle rate and 50% duty cycle signal. For lower I/O toggle rates and situations where the device is in an idle state, lifetimes are increased. Figure 1­1. Overshoot Duration 4.2 V 4.1 V 3.3 V T T Altera Corporation July 2007 1­2 Cyclone III Device Handbook, Volume 2 Electrical Characteristics Recommended Operating Conditions This section lists the functional operation limits for AC and DC parameters for Cyclone III devices. The steady-state voltage and current values expected from Cyclone III devices are provided in the Table 1­3. All supplies must be strictly monotonic without plateaus. Table 1­3. Recommended Operating Conditions Notes (1), (2) Symbol Parameter Conditions Min Typ Max Unit VCCINT (3) Supply voltage for internal logic and input buffers - 1.15 1.2 1.25 V VCCIO (3) Supply voltage for output buffers, 3.3-V operation - 3.15 3.3 3.45 V Supply voltage for output buffers, 3.0-V operation - 2.85 3 3.15 V Supply voltage for output buffers, 2.5-V operation - 2.375 2.5 2.625 V Supply voltage for output buffers, 1.8-V operation - 1.71 1.8 1.89 V Supply voltage for output buffers, 1.5-V operation - 1.425 1.5 1.575 V Supply voltage for output buffers, 1.2-V operation - 1.14 1.2 1.26 V VCCA (3) Supply (analog) voltage for PLL regulator - 2.375 2.5 2.625 V VCCD_PLL (3) Supply (digital) voltage for PLL - 1.15 1.2 1.25 V VI Input voltage - ­0.5 - 3.6 V VO Output voltage - 0 - VCCIO V TJ Operating junction temperature For commercial use 0 - 85 °C For industrial use ­40 - 100 °C tRAMP Power supply ramptime Standard POR (4) 50 µs - 50 ms - Fast POR (5) 50 µs - 3 ms - Notes to Table 1­3: (1) (2) (3) (4) (5) VCCIO for all I/O banks should be powered up during device operation. All VCCA pins must be powered to 2.5 V (even when PLLs are not used), and must be powered-up and powered-down at the same time. VCCD_PLL must always be connected to VCCINT through a decoupling capacitor and ferrite bead. The VCC must rise monotonically. POR time for Standard POR will range between 50 ­ 200 ms. All supplies must be up and stable within 50 ms. POR time for Fast POR will range between 3 ­ 9 ms. All supplies must be up and stable within 3 ms. DC Characteristics This section lists the I/O leakage currents, pin capacitance, on chip termination tolerance and and bus hold specifications for Cyclone III devices. Supply Current Standby current is the current the device draws after the device is configured with no inputs/outputs toggling and no activity in the device. Since these currents vary largely with resources used, use the Excel based Early Power Estimator to get supply current estimates for your design. Table 1­4 lists I/O pin leakage current for Cyclone III. Table 1­4. Cyclone III I/O Pin Leakage Current Notes (1), (2) (Part 1 of 2) Symbol Parameter Conditions Min Typ Max Unit II Altera Corporation July 2007 Input Pin Leakage Current VI = VCCIOMAX to 0 V ­10 - 10 A IOZ Tri-stated I/O Pin Leakage Current VO = VCCIOMAX to 0 V ­10 - 10 A 1­3 Cyclone III Device Handbook, Volume 2 Cyclone III Device Datasheet: DC and Switching Characteristics Table 1­4. Cyclone III I/O Pin Leakage Current Notes (1), (2) (Part 2 of 2) Symbol Min Typ Max Unit VI = ground, no load, no toggling inputs, TJ = 25C EP3C5 1.7 (3) mA EP3C10 EP3C10 1.7 mA EP3C16 EP3C16 3.0 mA 3.5 mA EP3C40 EP3C40 4.3 mA EP3C55 EP3C55 5.2 mA EP3C80 EP3C80 VC C I N T supply current (standby) Conditions EP3C25 EP3C25 IC C I N T 0 Parameter 6.5 mA EP3C120 EP3C120 mA 11.4 mA 18.4 mA 18.6 mA 18.7 mA 18.9 mA 19.2 EP3C5 4.1 EP3C10 EP3C10 4.1 mA EP3C16 EP3C16 8.2 mA EP3C25 EP3C25 8.2 mA EP3C40 EP3C40 8.2 mA EP3C55 EP3C55 8.2 mA EP3C80 EP3C80 VI = ground, no load, no toggling inputs, TJ = 25C 11.3 EP3C16 EP3C16 EP3C120 EP3C120 VC C D _ P L L supply current (standby) EP3C10 EP3C10 EP3C80 EP3C80 IC C D _ P L L 0 8.4 EP3C55 EP3C55 VI = ground, no load, no toggling inputs, TJ = 25C 11.3 EP3C40 EP3C40 VC C A supply current (standby) EP3C5 EP3C25 EP3C25 IC C A 0 mA 8.2 mA (3) mA mA (3) mA EP3C120 EP3C120 8.2 EP3C10 EP3C10 0.6 mA EP3C16 EP3C16 0.9 mA 0.9 mA 1.3 mA EP3C55 EP3C55 1.3 mA EP3C80 EP3C80 1.3 mA EP3C120 EP3C120 VI = ground, no load, no toggling inputs, TJ = 25C 0.6 EP3C40 EP3C40 VC C I O supply current (standby) EP3C5 EP3C25 EP3C25 IC C I O 0 mA 1.2 mA (3) mA Notes to Table 1­4: (1) (2) (3) This value is specified for normal device operation. The value may vary during power-up. This applies for all VCCIO settings (3.3, 3.0, 2.5, 1.8, 1.5 and 1.2 V). 10 A I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be the observed when the diode is on. Maximum values depend on the actual TJ and design utilization. Refer to the Excel-based PowerPlay Early Power Estimator (available at ) or the Quartus II PowerPlay Power Analyzer feature for maximum values. Refer to the "Power Consumption" on page 1­11" for more information. 1­4 Cyclone III Device Handbook, Volume 2 Altera Corporation July 2007 Electrical Characteristics Bus Hold Bus hold retains the last valid logic state after the source driving it either enters the high impedance state or is removed. Each I/O pin has an option to enable bus hold in user mode. Bus hold is always disabled in configuration mode. Table 1­5 lists bus hold specifications for Cyclone III. Also listed are the input pin capacitances and on-chip termination tolerance specifications. Table 1­5. Cyclone III Bus Hold Parameter Note (1) VCCIO (V) Parameter Condition 1.2 1.5 1.8 2.5 3.0 Unit 3.3 Min Max Min Max Min Max Min Max Min Max Min Max Bus-hold low, sustaining current VIN > VIL (maximum) 8 - 12 - 30 - 50 - 70 - 70 - A Bus-hold high, sustaining current VIN < VIL (minimum) ­8 - ­12 - ­30 - ­50 - ­70 - ­70 - A Bus-hold low, overdrive current 0 V < VIN < VCCIO - 125 - 175 - 200 - 300 - 500 - 500 A Bus-hold high, overdrive current 0 V < VIN < VCCIO - ­125 - ­175 - ­200 - ­300 - ­500 - ­500 A - 0.3 0.9 0.375 1.125 0.68 1.07 0.7 1.7 0.8 2 0.8 2 V Bus-hold trip point Note to Table 1­5: (1) The bus-hold trip points are based on calculated input voltages from the JEDEC standard. On-Chip Termination (OCT) Specifications Table 1­6 lists variation of uncalibrated OCT across process, temperature and voltage. Table 1­6. Uncalibrated On-Chip Series Termination Specifications Preliminary Resistance Tolerance Symbol VCCIO (V) Commercial Industrial Min Series Termination without calibration 3.0 Max Min Max ­30 +30 (1) (1) Unit % 2.5 ­30 +30 (1) (1) % 1.8 ­30 +30 (1) (1) % 1.5 ­30 +30 (1) (1) % 1.2 ­40 +40 (1) (1) % Note to Table 1­6: (1) Pending silicon characterization OCT calibration is automatically performed at power up for OCT enabled I/Os. Altera Corporation July 2007 1­5 Cyclone III Device Handbook, Volume 2 Electrical Characteristics Table 1­7 lists the OCT calibration accuracy at power up. Table 1­7. On-Chip Series Termination Power-up Calibration Specifications Preliminary Calibration Accuracy VCCIO (V) Series Termination with power-up calibration Commercial Max 3.0 2.5 Symbol Industrial Max Unit ±10% (1) % ±10% (1) % 1.8 ±10% (1) % 1.5 ±10% (1) % 1.2 ±10% (1) % Note to Table 1­7: (1) Pending silicon characterization Table 1­8 lists the percentage change of the OCT resistance with voltage and temperature. Use Table 1­8 and Equation 1­1 to determine OCT variation after power-up calibration. Table 1­8. On-Chip Termination Variation After Power-up Calibration Nominal Voltage dR/dT (%Ohm/°C) dR/dmV (%Ohm/mV) 3.0 0.262 ­0.026 2.5 0.234 ­0.039 1.8 0.219 ­0.086 1.5 0.199 ­0.136 1.2 0.161 ­0.288 Note to Table 1­8: (1) Altera Corporation July 2007 This table is needed to calculate the final OCT resistance with the variation of temperature and voltage. 1­6 Cyclone III Device Handbook, Volume 2 Electrical Characteristics Equation 1­1. Notes (1), (2), (3), (4), (5), (6), (7), (8), (9), (10), (11), (12) RV = (V2 ­ V1) × 1000 × dR/dmV - (1) RT = (T2 ­ T1) × dR/dT - (2) For Rx < 0; MFx = 1/ (|Rx|/100 + 1) - (3) For Rx > 0; MFx = Rx/100 + 1 - (4) MF = MFV × MFT - (5) Rfinal = Rinitial × MF - (6) Notes to Equation 1­1: (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) RV is variation of resistance with voltage. RT is variation of resistance with temperature. dR/dT is the percentage change of resistance with temperature. dR/dmV is the percentage change of resistance with voltage. V2 is final voltage. V1 is the initial voltage. T2 is the final temperature. T1 is the initial temperature. MF is multiplication factor. Rfinal is final resistance. Rinitial is initial resistance. Subscript x refers to both V and T. For example, to calculate the change of 50 I/O impedance from 25° C at 3.0 V to 85° C at 3.15 V, RV = (3.15 ­ 3) × 1000 × ­0.026 = ­3.83 RT = (85 ­ 25) × 0.262 = 15.72 Since RV is negative, MFV = 1 / ( 3.83/100 + 1) = 0.963 Since RT is positive, MFT = 15.72/100 + 1 = 1.157 MF = 0.963 × 1.157 = 1.114 Rfinal = 50 × 1.114 = 55.71 Pin Capacitance Table 1­9 shows the Cyclone III device family pin capacitance. Table 1­9. Cyclone III Device Pin Capacitance Note (1) (Part 1 of 2) Symbol Preliminary Typical ­ QFP Parameter Typical ­ FBGA Unit CIOTB Input capacitance on top/bottom I/O pins 7 6 pF CIOLR Input capacitance on left/right I/O pins 6 5 pF CLVDSLR Input capacitance on left/right I/O pins with Dedicated LVDS output 8 7 pF CVREFLR Input capacitance on top/bottom I/O pins with VREF CCLKTB Altera Corporation July 2007 Input capacitance on left/right I/O pins with VREF CVREFTB Input capacitance on top/bottom dedicated clock input pins 21 21 pF 21 (2) 21 (2) pF 7 6 pF 1­7 Cyclone III Device Handbook, Volume 2 Cyclone III Device Datasheet: DC and Switching Characteristics Table 1­9. Cyclone III Device Pin Capacitance Note (1) (Part 2 of 2) Symbol CCLKLR Preliminary Typical ­ QFP Typical ­ FBGA Unit 6 Parameter 5 pF Input capacitance on left/right dedicated clock input pins Notes to Table 1­9: (1) (2) Pending silicon characterization. CV R E F T B for EP3C25 EP3C25 is 30 pF. Internal Weak Pull-up and Weak Pull-down Resistor Table 1­10 lists the weak pull-up and pull-down resistor values for Cyclone III devices. Table 1­10. Cyclone III Internal Weak Pull-Up / Weak Pull-Down Resistor Note (1) Symbol Conditions Typ Max Unit 7 25 41 K VI = 0 V, VCCIO = 3.0 V ± 5% (3), (4) 7 28 47 K VI = 0 V, VCCIO = 2.5 V ± 5% (3), (4) 8 35 61 K 10 57 108 K 13 82 163 K VI = 0 V, VCCIO = 1.2 V ± 5% (3), (4) 19 143 351 K VI = 0 V, VCCIO = 3.3 V ± 5% (3), (4) 6 19 30 K VI = 0 V, VCCIO = 3.0 V ± 5% (3), (4) 6 22 36 K VI = 0 V, VCCIO = 2.5 V ± 5% (3), (4) 6 25 43 K VI = 0 V, VCCIO = 1.8 V ± 5% (3), (4) 7 35 71 K VI = 0 V, VCCIO = 1.5 V ± 5% (3), (4) Value of I/O pin pull-down resistor before and during configuration Min VI = 0 V, VCCIO = 1.5 V ± 5% (3), (4) RCONF_PD (2) Parameter Value of I/O pin pull-up resistor before and during configuration VI = 0 V, VCCIO = 3.3 V ± 5%(3), (4) VI = 0 V, VCCIO = 1.8 V ± 5% (3), (4) RCONF_PU (2) 8 50 112 K Notes to Table 1­10: (1) (2) (3) (4) All I/O pins have an option to enable weak pull-up except configuration, test and JTAG pin. Weak pull-down feature is only available for JTAG TCK. RCONF values are based on characterization. RCONF = VCCIO/IRCONF. RCONF values may be different if VI value is not 0 V. VI refers to the input voltage at the I/O pin. Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO. Minimum condition at ­40° C and high VCC, typical condition at 25° C and nominal VCC and maximum condition at 125° C and low VCC for RCONF values. Hot Socketing Table 1­11 lists the hot-socketing specifications for Cyclone III devices. Table 1­11. Cyclone III Hot Socketing Specifications Symbol Parameter Maximum IIOPIN(DC) DC current per I/O pin 300 A IIOPIN(AC) AC current per I/O pin 8 mA (1) Note to Table 1­11: (1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, where C is I/O pin capacitance and dv/dt is the slew rate. 1­8 Cyclone III Device Handbook, Volume 2 Altera Corporation July 2007 Electrical Characteristics I/O Standard Specifications The following tables list input voltage sensitivities (VIH and VIL), and output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O standards supported by Cyclone III devices. Table 1­12 to Table 1­17 show the Cyclone III device family I/O standard specifications. Refer to "Single-ended Voltage referenced I/O Standard" in "Glossary" for voltage referenced receiver input waveform and explanation of terms used in Table 1­12. Table 1­12. Single-Ended I/O Standard Specifications Note (1) VCCIO(V) VIL(V) VIH(V) VOL(V) VOH(V) I/O Standard IOH (3) IOL (3) Min Max Min Max Min Max Max Min 3.15 3.3-V LVTTL (2) Typ 3.3 3.45 - 0.8 1.7 3.6 0.45 2.4 4 ­4 (mA) (mA) 3.3-V LVCMOS (2) 3.15 3.3 3.45 - 0.8 1.7 3.6 0.2 VC C I O ­ 0.2 2 ­2 3.0-V LVTTL (2) 2.85 3.0 3.15 ­0.3 0.8 1.7 VCCIO + 0.3 0.45 2.4 4 ­4 3.0-V LVCMOS (2) 2.85 3.0 3.15 ­0.3 0.8 1.7 VCCIO + 0.3 0.2 VCCIO ­ 0.2 0.1 ­0.1 2.5-V LVTTL and LVCMOS (2) 2.375 2.5 2.625 ­0.3 0.7 1.7 VCCIO + 0.3 0.2 2.1 0.1 ­0.1 0.4 2.0 1 ­1 0.7 1.7 2 ­2 1.8-V LVTTL and LVCMOS 1.71 1.8 1.89 ­0.3 0.35 * VCCIO 0.65 * VCCIO 0.45 VCCIO ­ 0.45 2 ­2 1.5-V LVCMOS 1.425 1.5 1.575 ­0.3 0.35 * VCCIO 0.65 * VCCIO VCCIO + 0.3 0.25 * VCCIO 0.75 * VCCIO 2 ­2 0.35 * VCCIO 0.65 * VCCIO VCCIO + 0.3 0.25 * VCCIO 0.75 * VCCIO 1.2-V LVCMOS 1.14 1.2 1.26 ­0.3 PCI and PCI-X 2.85 3.0 3.15 - 0.3 * VCCIO 0.5 * VCCIO 2.25 VCCIO + 0.3 0.1 * VCCIO 0.9 * VCCIO 2 ­2 1.5 ­0.5 Notes to Table 1­12: (1) (2) (3) AC load CL = 10 pF. For more detail of interfacing Cyclone III devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O standards, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. Specified IOL and IOH are valid with lowest current strength setting available for respective I/O standards. IOL and IOH values correspond to the selected current strength settings value. For example, current drive characteristics for 3.3-V LVTTL with 8 mA current strength setting are 8 mA (IOL) and ­8 mA (IOH) at 0.45 V (VOL) and 2.4 V (VOH), respectively. Refer to "Glossary" for explanation of terms used in Table 1­13. Table 1­13. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications VCCIO(V) I/O Standard Min VREF(V) Typ Max Min Typ VTT(V) (3) Max Min Typ Max SSTL-2 Class I, II 2.375 2.5 2.625 1.19 1.25 1.31 VREF ­ 0.04 VREF VREF + 0.04 SSTL-18 SSTL-18 Class I, II 1.7 1.8 1.9 0.833 0.9 0.969 VREF ­ 0.04 VREF VREF + 0.04 HSTL-18 HSTL-18 Class I, II 1.71 1.8 1.89 0.85 0.9 0.95 0.85 0.9 0.95 HSTL-15 HSTL-15 Class I, II 1.425 1.5 1.575 0.71 0.75 0.79 0.71 0.75 0.79 HSTL-12 HSTL-12 Class I, II 1.14 1.2 1.26 - 0.5 * VCCIO - 0.48 * VCCIO (1) 0.5 * VCCIO (1) 0.52 * VCCIO (1) 0.47 * VCCIO (2) 0.5 * VCCIO (2) 0.53 * VCCIO (2) Notes to Table 1­13: (1) (2) (3) Value shown refers to DC input reference voltage, VREF(DC). Value shown refers to AC input reference voltage, VREF(AC). VTT of transmitting device must track VREF of the receiving device. Altera Corporation July 2007 1­9 Cyclone III Device Handbook, Volume 2 Cyclone III Device Datasheet: DC and Switching Characteristics Table 1­14. Single-Ended SSTL and HSTL I/O Standards Signal Specifications VIL(DC)(V) I/O Standard VIH(DC)(V) VIL(AC)(V) VIH(AC)(V) Max Max Min IOL (mA) IOH (mA) VTT ­ 0.57 VTT + 0.57 8.1 ­8.1 VTT + 0.76 Max Min Max Min - VREF ­ 0.18 VREF + 0.18 - - VREF ­ 0.35 VREF + 0.35 - VREF + 0.18 - - VREF ­ 0.35 VREF + 0.35 - VTT ­ 0.76 16.4 ­16.4 - - VREF ­ 0.25 VREF + 0.25 - VTT ­ 0.475 VTT + 0.475 6.7 ­6.7 SSTL-2 Class II - VREF ­ 0.18 SSTL-18 SSTL-18 Class I - VREF ­ 0.125 VREF + 0.125 SSTL-18 SSTL-18 Class II - VREF ­ 0.125 VREF + 0.125 HSTL-18 HSTL-18 Class I - Min VOH(V) Min SSTL-2 Class I Max VOL(V) - - VREF ­ 0.25 VREF + 0.25 - 0.28 VCCIO ­ 0.28 13.4 ­13.4 VREF ­ 0.1 VREF + 0.1 - - VREF ­ 0.2 VREF + 0.2 - 0.4 VCCIO ­ 0.4 8 ­8 HSTL-18 HSTL-18 Class II - VREF ­ 0.1 VREF + 0.1 - - VREF ­ 0.2 VREF + 0.2 - 0.4 VCCIO ­ 0.4 16 ­16 HSTL-15 HSTL-15 Class I - VREF ­ 0.1 VREF + 0.1 - - VREF ­ 0.2 VREF + 0.2 - 0.4 VCCIO ­ 0.4 8 ­8 HSTL-15 HSTL-15 Class II - VREF ­ 0.1 VREF + 0.1 - - VREF ­ 0.2 VREF + 0.2 - 0.4 VCCIO ­ 0.4 16 ­16 HSTL-12 HSTL-12 Class I ­0.15 VREF ­ 0.08 VREF + 0.08 VCCIO + 0.15 ­0.24 VREF ­ 0.15 VREF + 0.15 VCCIO + 0.24 0.25 × VCCIO 0.75 × VCCIO 8 ­8 HSTL-12 HSTL-12 Class II ­0.15 VREF ­ 0.08 VREF + 0.08 VCCIO + 0.15 ­0.24 VREF ­ 0.15 VREF + 0.15 VCCIO + 0.24 0.25 × VCCIO 0.75 × VCCIO 14 ­14 f For more illustrations of receiver input and transmitter output waveforms, and for other differential I/O standards, refer to the High-Speed Differential Interfaces chapter in volume 1 of the Cyclone III Device Handbook. Table 1­15. Differential SSTL I/O Standard Specifications VCCIO(V) I/O Standard VSwing(DC)(V) VX(DC)(V) Min Typ Max Min Max Min Typ SSTL-2 Class I, II 2.375 2.5 2.625 0.36 VCCIO VCCIO/2 ­ 0.2 SSTL-18 SSTL-18 Class I, II 1.7 1.8 1.90 0.25 VCCIO VCCIO/2 ­ 0.175 VSwing(AC)(V) Max Min Max - VCCIO/2 + 0.2 0.7 - VCCIO/2 + 0.175 0.5 VOX(AC)(V) Min Typ Max VCCIO (1) - (1) VCCIO VCCIO/2 ­ 0.125 - VCCIO/2 + 0.125 Note to Table 1­15: (1) Pending silicon characterization. Table 1­16. Differential HSTL I/O Standard Specifications VCCIO(V) I/O Standard VDIF(DC)(V) VX(AC)(V) VCM(DC)(V) VDIF(AC)(V) Min Typ Max Min Max Min Typ Max Min Typ Max Min Max HSTL-18 HSTL-18 Class I, II 1.71 1.8 1.89 0.2 - 0.85 - 0.95 0.85 - 0.95 0.4 - HSTL-15 HSTL-15 Class I, II 1.425 1.5 1.575 0.2 - 0.71 - 0.79 0.71 - 0.79 0.4 - HSTL-12 HSTL-12 Class I, II 1.14 1.2 1.26 0.16 VC C I O 0.48 * VC C I O - - 0.52 * VC C I O 1­10 Cyclone III Device Handbook, Volume 2 0.52 * VC C I O 0.48 * VC C I O 0.3 0.48 * VC C I O Altera Corporation July 2007 Electrical Characteristics Refer to "Transmitter Output Waveform" in "Glossary" for an explanation of terms used in Table 1­17. Table 1­17. Differential I/O Standard Specifications VCCIO(V) I/O Standard Min LVPECL (Row I/Os) (2) Typ 2.375 2.5 VTH(mV) Max Min 2.625 ­100 VIN(V) Condition Max Min VCM = 1.25V 100 0 Condition DMAX 500 Mbps 0.5 500 Mbps DMAX 700 Mbps VOD(mV) (1) Max Min Typ Max 2.5 2.625 ­100 VCM = 1.25V 100 1.85 247 - 600 1.125 1.25 1.375 247 - 600 1.125 1.25 1.375 247 - 600 1.125 1.25 1.375 247 - 600 1.125 1.25 1.375 DMAX > 700 Mbps 2.375 DMAX 500 Mbps 1.85 0.5 500 Mbps DMAX 700 Mbps LVDS (Column I/Os) 2.375 2.5 2.625 ­100 VCM =1.25V 100 DMAX > 700 Mbps 0 DMAX 500 Mbps 0.5 500 Mbps DMAX 700 Mbps 2.625 ­100 VCM = 1.25V 100 Max 1.85 1.6 1.85 1.85 1 2.5 Typ 1.6 0 1 LVDS (Row I/Os) Min 1.85 1 LVPECL 2.375 (Column I/Os) (2) VOS(V) (1) DMAX > 700 Mbps 1.6 0 DMAX 500 Mbps 1.85 0.5 500 Mbps DMAX 700 Mbps 1 DMAX > 700 Mbps 1.85 1.6 2.375 2.5 2.625 - - - - - - 300 - 600 1.0 1.2 1.4 mini-LVDS 2.375 (Column I/Os) (3) 2.5 2.625 - - - - - - 300 - 600 1.0 1.2 1.4 2.375 2.5 2.625 - - - - - - 100 200 600 0.5 1.2 1.5 RSDS 2.375 (Column I/Os) (3) 2.5 2.625 - - - - - - 100 200 600 0.5 1.2 1.5 2.375 PPDS® (Row I/Os) (3) (4) 2.5 2.625 - - - - - - 100 200 600 0.5 1.2 1.4 PPDS 2.375 (Column I/Os) (3) 2.5 2.625 - - - - - - 100 200 600 0.5 1.2 1.4 mini-LVDS (Row I/Os) (3) RSDS® (Row I/Os)(3) (4) Notes to Table 1­17: (1) (2) (3) (4) RL range : 90 RL 110 . LVPECL input standard is only supported at clock input. Output standard is not supported. Mini-LVDS, RSDS and PPDS standards are only supported at output pins of Cyclone III devices. RSDS and PPDS are registered trademarks of National Semiconductor. Power Consumption Altera® offers two ways to estimate power for a design: the Excel-based Early Power Estimator and the Quartus® II PowerPlay Power Analyzer feature. The interactive Excel-based Early Power Estimator is typically used prior to designing the device in order to get a magnitude estimate of the device power. The Quartus II PowerPlay Power Analyzer provides better quality estimates based on the specifics of the design after place-and-route is complete. The PowerPlay Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities which, combined with detailed circuit models, can yield very accurate power estimates. f Altera Corporation July 2007 For more information on power estimation tools, refer to the Early Power Estimator User Guide and the PowerPlay Power Analysis chapters in the Quartus II Handbook. 1­11 Cyclone III Device Handbook, Volume 2 Cyclone III Device Datasheet: DC and Switching Characteristics Switching Characteristics This section provides performance characteristics of the Cyclone III core and periphery blocks for commercial grade devices. These characteristics can be designated as Preliminary and Final. Each designation is defined below. Preliminary Final Preliminary characteristics are created Final numbers are based on actual silicon characterization and testing. using simulation results, process data, These numbers reflect the actual performance of the device under worst-case silicon process, voltage and junction temperature and other known parameters. conditions. The upper-right hand corner of a table shows the designation as 'Preliminary' or 'Final'. Core Performance Specifications Clock Tree Specifications Table 1­18 lists the clock tree specifications for Cyclone III devices. Table 1­18. Cyclone III Clock Tree Performance Preliminary Performance Device ­6 Speed Grade ­7 Speed Grade ­8 Speed Grade Unit EP3C5 500 (2) (2) MHz EP3C10 EP3C10 500 (2) (2) MHz EP3C16 EP3C16 500 (2) (2) MHz EP3C25 EP3C25 500 (2) (2) MHz EP3C40 EP3C40 500 (2) (2) MHz EP3C55 EP3C55 500 (2) (2) MHz EP3C80 EP3C80 500 (2) (2) MHz EP3C120 EP3C120 (1) 437.5 (2) MHz Notes to Table 1­18: (1) (2) EP3C120 EP3C120 offered in ­7 and ­8 speed grades only. Pending silicon characterization. PLL Specifications Table 1­19 describes the Cyclone III PLL specifications when operating in both the commercial junction temperature range (0° C to 85° C) and the industrial junction temperature range (­40° C to 100° C). For more information on PLL Block, refer to "PLL Block" in "Glossary". Table 1­19. Cyclone III PLL Specifications Note (5) (Part 1 of 2) Symbol Min Typ Max Unit Input clock frequency (­6 speed grade) 5 - 472.5 MHz Input clock frequency (­7 speed grade) fIN (1) Parameter Preliminary 5 - 472.5 MHz Input clock frequency (­8 speed grade) 5 - 472.5 MHz PFD input frequency (­6 speed grade) 5 - 325 MHz PFD input frequency (­7 speed grade) 5 - 325 MHz PFD input frequency (­8 speed grade) fINPFD 5 - 325 MHz 1­12 Cyclone III Device Handbook, Volume 2 Altera Corporation July 2007 Switching Characteristics Table 1­19. Cyclone III PLL Specifications Note (5) (Part 2 of 2) Symbol Preliminary Parameter Min Typ Max Unit fVCO PLL internal VCO operating range 600 - 1300 MHz fINDUTY Input clock duty cycle 40 - 60 % tINJITTER Input clock period jitter - 200 - ps fOUT_EXT (external clock output) (1) PLL output frequency (­6 speed grade) 5 - 472.5 MHz PLL output frequency (­7 speed grade) 5 - 472.5 MHz PLL output frequency (­8 speed grade) 5 - 472.5 MHz PLL output frequency (­6 speed grade) 5 - 472.5 MHz PLL output frequency (­7 speed grade) 5 - 450 MHz fOUT (to global clock) PLL output frequency (­8 speed grade) 5 - 402.5 MHz tOUTDUTY Duty cycle for external clock output (when set to 50%) 45 50 55 % tLOCK Time required to lock from end of device configuration - - 100 (2) µs tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) - - 1 ms tOU TJIT TE R_DEDCLK Dedicated clock output period jitter - - 300 ps tOU TJIT TE R_IO Regular I/O period jitter - - (4) ps tPLL_PSERR Accuracy of PLL phase shift - - ±60 ps tARESET Minimum pulse width on areset signal. 10 - - ns tCONFIGPLL Time required to reconfigure scan chains for PLLs - 3.5 (3) - SCANCLK cycles fSCANCLK scanclk frequency - - 100 MHz Notes to Table 1­19: (1) (2) (3) (4) (5) This parameter is limited in Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard. For extended temperature devices, the maximum lock time is 500 µs. With 100 MHz scanclk frequency. Pending silicon characterization. VCCD_PLL should always be connected to VCCINT through decoupling capacitor and ferrite bead. Embedded Multiplier Specifications Table 1­20 describes the Cyclone III embedded multiplier specifications. Table 1­20. Cyclone III Embedded Multiplier Specifications Resources Used Mode Number of Multipliers Preliminary Performance ­6 Speed Grade ­7 Speed Grade ­8 Speed Grade Unit 9 × 9-bit multiplier Altera Corporation July 2007 1 260 223 180 MHz 18 × 18-bit multiplier 1 260 223 180 MHz 1­13 Cyclone III Device Handbook, Volume 2 Switching Characteristics Memory Block Specifications Table 1­21 describes the Cyclone III M9K Memory block specifications. Table 1­21. Cyclone III Memory Block Performance Specifications Note (1) Preliminary Resources Used Memory LEs M9K Block Performance Mode M9K Memory ­6 Speed Grade Unit FIFO 256×36 47 1 260 MHz Single-port 256×36 0 1 260 MHz Simple dual-port 256×36 CLK 0 1 260 MHz True dual port 512×18 single CLK 0 1 260 MHz Note to Table 1­21: (1) Values for device speed grade ­7 and ­8 will be available after characterization. Configuration and JTAG Specifications Table 1­22 lists the Cyclone III Configuration Mode Specifications. Table 1­22. Cyclone III Configuration Mode Specifications Preliminary DCLK Fmax Unit Passive Serial (PS) 133 MHz Fast Passive Parallel (FPP) (1) 100 MHz Programming Mode Note to Table 1­22: (1) EP3C25 EP3C25 and smaller family members support 133 MHz. Table 1­23 lists the Cyclone III Active Configuration Mode Specifications. Table 1­23. Cyclone III Active Configuration Mode Specifications Programming Mode Preliminary DCLK Range Unit Active Parallel (AP) 20 ­ 40 MHz Active Serial (AS) 20 ­ 40 MHz Table 1­24 shows the JTAG timing parameters and values for Cyclone III. For more information, refer to "JTAG Waveform" in "Glossary". Table 1­24. Cyclone III JTAG Timing Parameters (Part 1 of 2) Symbol Parameter Preliminary Min Max Unit tJCP 40 - ns TCK clock high time 20 - ns tJCL TCK clock low time 20 - ns tJPSU_TDI JTAG port setup time for TDI(1) 1 - ns tJPSU_TMS JTAG port setup time for TMS (1) 3 - ns tJPH JTAG port hold time 10 - ns tJPCO JTAG port clock to output (1) - 15 ns tJPZX Altera Corporation July 2007 TCK clock period tJCH JTAG port high impedance to valid output (1) - 15 ns 1­14 Cyclone III Device Handbook, Volume 2 Switching Characteristics Table 1­24. Cyclone III JTAG Timing Parameters (Part 2 of 2) Symbol Preliminary Parameter Min Max Unit tJPXZ JTAG port valid output to high impedance (1) - 15 ns tJSSU Capture register setup time (1) 5 - ns tJSH Capture register hold time 10 - ns tJSCO Update register clock to output - 25 ns tJSZX Update register high impedance to valid output - 25 ns tJSXZ Update register valid output to high impedance - 25 ns Note to Table 1­24: (1) The specification is shown for 3.3 V, 3.0 V and 2.5 V LVTTL/LVCMOS operation of JTAG pins. For 1.8- V LVTTL/LVCMOS and 1.5- V LVCMOS, the JTAG port clock to output time is 16 ns. Periphery Performance High-Speed I/O Specification Table 1­25 to Table 1­34 show the high-speed I/O timing for Cyclone III devices. Refer to "Glossary" for definitions of high-speed timing specifications. Table 1­25. Dedicated RSDS Transmitter Timing Specification Notes (2), (3) ­6 Speed Grade Symbol Modes Unit Min Max ×10 10 - 180 MHz ×8 10 - 180 MHz ×7 10 - 180 MHz ×4 10 - 180 MHz ×2 fHSCLK (input clock frequency) Typ 10 - 180 MHz ×1 - 360 MHz 100 - 360 Mbps 80 - 360 Mbps ×7 70 - 360 Mbps ×4 40 - 360 Mbps ×2 20 - 360 Mbps ×1 tDUTY 10 ×10 ×8 Device operation in Mbps 10 - 360 Mbps - (1) - (1) % TCCS - - - (1) ns Output jitter (peak to peak) - - - (1) ps tRISE 20 ­ 80% - (1) - ps tFALL 80 ­ 20% - (1) - ps tLOCK - - - (1) ms Notes to Table 1­25: (1) (2) (3) Altera Corporation July 2007 Pending silicon characterization. Values for device speed grade ­7 and ­8 will be available after characterization. Dedicated RSDS is only supported at output pin of Row I/O (Banks 1, 2, 5, and 6). 1­15 Cyclone III Device Handbook, Volume 2 Switching Characteristics Table 1­26. Single-Resistor RSDS Transmitter Timing Specification Notes (2), (3) ­6 Speed Grade Symbol Modes Unit Min 10 - 85 MHz 10 - 85 MHz 10 - 85 MHz ×4 10 - 85 MHz ×2 10 - 85 MHz ×1 10 - 85 MHz ×10 100 - (1) Mbps ×8 80 - (1) Mbps ×7 70 - (1) Mbps ×4 40 - (1) Mbps ×2 20 - (1) Mbps ×1 10 - (1) Mbps - tDUTY ×10 ×7 Device operation in Mbps Max ×8 fHSCLK (input clock frequency) Typ (1) - (1) % TCCS - - - (1) ps Output jitter (peak to peak) - - - (1) ps tRISE 20 ­ 80% - (1) - ps tFALL 80 ­ 20% - (1) - ps tLOCK - - - (1) ms Notes to Table 1­26: (1) (2) (3) Pending silicon characterization. Values for device speed grade ­7 and ­8 will be available after characterization. Single-resistor RSDS is only supported at output pin of Column I/O (Banks 3, 4, 7, and 8). Table 1­27. Three-Resistor RSDS Transmitter Timing Specification Notes (2), (3) (Part 1 of 2) ­6 Speed Grade Symbol Modes Unit Min ×10 10 - 155.5 MHz 10 - 155.5 MHz ×7 10 - 155.5 MHz ×4 10 - 155.5 MHz ×2 10 - 155.5 MHz ×1 10 - 155.5 MHz ×10 100 - (1) Mbps ×8 Device operation in Mbps Max ×8 fHSCLK (input clock frequency) Typ 80 - (1) Mbps ×7 70 - (1) Mbps ×4 40 - (1) Mbps ×2 tDUTY 20 - (1) Mbps ×1 10 - (1) Mbps - (1) - (1) % TCCS - - - (1) ps Output jitter (peak to peak) - - - (1) ps 20 ­ 80% - (1) - ps tRISE Altera Corporation July 2007 1­16 Cyclone III Device Handbook, Volume 2 Switching Characteristics Table 1­27. Three-Resistor RSDS Transmitter Timing Specification Notes (2), (3) (Part 2 of 2) ­6 Speed Grade Symbol Modes Unit Min Typ Max tFALL 80 ­ 20% - (1) - ps tLOCK - - - (1) ms Notes to Table 1­27: (1) (2) (3) Pending silicon characterization. Values for device speed grade ­7 and ­8 will be available after characterization. Three-resistor RSDS is only supported at output pin of Column I/O (Banks 3, 4, 7, and 8). Table 1­28. Dedicated PPDS Transmitter Timing Specification Notes (2), (3) ­6 Speed Grade Symbol Modes Unit Min Max ×10 10 - (1) MHz ×8 10 - (1) MHz ×7 10 - (1) MHz ×4 10 - (1) MHz ×2 fHSCLK (input clock frequency) Typ 10 - (1) MHz ×1 10 - (1) MHz ×10 100 - (1) Mbps ×8 80 - (1) Mbps ×7 70 - (1) Mbps ×4 40 - (1) Mbps ×2 Device operation in Mbps 20 - (1) Mbps ×1 10 - (1) Mbps tDUTY - (1) - (1) % TCCS - - - (1) ps - - - (1) ps tRISE 20 ­ 80% - (1) - ps tFALL 80 ­ 20% - (1) - ps tLOCK - - - (1) ms Output jitter (peak to peak) Notes to Table 1­28: (1) (2) (3) Pending silicon characterization. Values for device speed grade ­7 and ­8 will be available after characterization. Dedicated PPDS is only supported at output pin of Row I/O (Banks 1, 2, 5, and 6). Table 1­29. Three-Resistor PPDS Transmitter Timing Specification Notes (2), (3) (Part 1 of 2) ­6 Speed Grade Symbol Modes Unit Min ×10 10 - (1) MHz ×8 fHSCLK (input clock frequency) Typ Max 10 - (1) MHz ×7 10 - (1) MHz ×4 10 - (1) MHz ×2 Altera Corporation July 2007 10 - (1) MHz ×1 10 - (1) MHz 1­17 Cyclone III Device Handbook, Volume 2 Switching Characteristics Table 1­29. Three-Resistor PPDS Transmitter Timing Specification Notes (2), (3) (Part 2 of 2) ­6 Speed Grade Symbol Modes Unit Min ×10 100 - (1) Mbps 80 - (1) Mbps ×7 70 - (1) Mbps ×4 40 - (1) Mbps ×2 20 - (1) Mbps ×1 10 - (1) Mbps - tDUTY Max ×8 Device operation in Mbps Typ (1) - (1) % TCCS - - - (1) ps Output jitter (peak to peak) - - - (1) ps tRISE 20 ­ 80% - (1) - ps tFALL 80 ­ 20% - (1) - ps tLOCK - - - (1) ms Notes to Table 1­29: (1) (2) (3) Pending silicon characterization. Values for device speed grade ­7 and ­8 will be available after characterization. Three-resistor PPDS is only supported at output pin of Column I/O (Banks 3, 4, 7, and 8). Table 1­30. Dedicated Mini-LVDS Transmitter Timing Specification Notes (2), (3) ­6 Speed Grade Symbol Modes Unit Min 10 - 200 MHz 10 - 200 MHz 10 - 200 MHz ×4 10 - 200 MHz ×2 10 - 200 MHz ×1 10 - 400 MHz ×10 100 - 400 Mbps ×8 80 - 400 Mbps ×7 70 - 400 Mbps ×4 40 - 400 Mbps ×2 20 - 400 Mbps ×1 tDUTY ×10 ×7 Device operation in Mbps Max ×8 fHSCLK (input clock frequency) Typ 10 - 400 Mbps - (1) - (1) % TCCS - - - 1.30 ns Output jitter (peak to peak) - - - (1) ps tRISE 20 ­ 80% - (1) - ps tFALL 80 ­ 20% - (1) - ps tLOCK - - - (1) ms Notes to Table 1­30: (1) (2) (3) Altera Corporation July 2007 Pending silicon characterization. Values for device speed grade ­7 and ­8 will be available after characterization. Dedicated mini-LVDS is only supported at output pin of Row I/O (Banks 1, 2, 5, and 6). 1­18 Cyclone III Device Handbook, Volume 2 Switching Characteristics Table 1­31. Three-Resistor mini-LVDS Transmitter Timing Specification Notes (2), (3) ­6 Speed Grade Symbol Modes Unit Min 10 - 155.5 MHz 10 - 155.5 MHz 10 - 155.5 MHz ×4 10 - 155.5 MHz ×2 10 - 155.5 MHz ×1 10 - 155.5 MHz ×10 100 - (1) Mbps ×8 80 - (1) Mbps ×7 70 - (1) Mbps ×4 40 - (1) Mbps ×2 20 - (1) Mbps ×1 10 - (1) Mbps - tDUTY ×10 ×7 Device operation in Mbps Max ×8 fHSCLK (input clock frequency) Typ (1) - (1) % TCCS - - - (1) ps Output jitter (peak to peak) - - - (1) ps tRISE 20 ­ 80% - (1) - ps tFALL 80 ­ 20% - (1) - ps tLOCK - - - (1) ms Notes to Table 1­31: (1) (2) (3) Pending silicon characterization. Values for device speed grade ­7 and ­8 will be available after characterization. Three-resistor mini-LVDS is only supported at output pin of Column I/O (Banks 3, 4, 7, and 8). Table 1­32. Dedicated LVDS Transmitter Timing Specification Notes (2), (5) (Part 1 of 2) ­6 Speed Grade Symbol Typ Max (3) Max (4) Unit Min ×10 10 - 420 (1) MHz ×8 10 - 420 (1) MHz ×7 10 - 420 (1) MHz ×4 10 - 420 (1) MHz ×2 10 - 420 (1) MHz ×1 10 - 420 (1) MHz ×10 100 - 840 (1) Mbps ×8 80 - 840 (1) Mbps ×7 70 - 840 (1) Mbps ×4 40 - 840 (1) Mbps ×2 20 - 840 (1) Mbps ×1 10 - 420 (1) Mbps tDUTY - (1) - (1) TCCS - - - Output jitter (peak to peak) - - - fHSCLK (input clock frequency) HSIODR Altera Corporation July 2007 Modes (1) 248 (1) % ps - ps 1­19 Cyclone III Device Handbook, Volume 2 Switching Characteristics Table 1­32. Dedicated LVDS Transmitter Timing Specification Notes (2), (5) (Part 2 of 2) ­6 Speed Grade Symbol Modes Typ Max (3) Max (4) Unit Min tRISE 20 ­ 80% (1) (1) (1) (1) ps tFALL 80 ­ 20% (1) (1) (1) (1) ps tLOCK - - - (1) - ms Notes to Table 1­32: (1) (2) (3) (4) (5) Pending silicon characterization. Values for device speed grade ­7 and ­8 will be available after characterization. The maximum data rate that complies with duty cycle distortion of 45­55%. The maximum data rate when taking duty cycle in absolute ps into consideration that may not comply with 45­55% duty cycle distortion. If the downstream receiver can handle duty cycle distortion beyond the 45­55% range, you may use the higher data rate values from this column. You can calculate the duty cycle distortion as a percentage using the absolute ps value. For example, for a data rate of 640 Mbps (UI = 1625 ps) and a tDUTY of 250 ps, the duty cycle distortion is: tDUTY/(UI*2) *100% = 250 ps/(1625 *2) * 100% = 7.7%, which gives you a duty cycle distortion of 42.3­57.7%. Dedicated LVDS transmitter is only supported at output pin of Row I/O (Banks 1, 2, 5, and 6). Table 1­33. Three-Resistor LVDS Transmitter Timing Specification Notes (2), (5) (Part 1 of 2) ­6 Speed Grade Symbol Modes Unit Min ×10 10 - 320 320 MHz ×8 fHSCLK (input clock frequency) Typ Max (3) Max (4) 10 - 320 320 MHz ×7 10 - 320 320 MHz ×4 10 - 320 320 MHz ×2 10 - 320 320 MHz ×1 10 - 402.5 402.5 MHz ×10 (1) - (1) (1) Mbps ×8 (1) - (1) (1) Mbps ×7 (1) - (1) (1) Mbps ×4 (1) - (1) (1) Mbps ×2 (1) - (1) (1) Mbps ×1 (1) - (1) (1) Mbps tDUTY - (1) - (1) (1) % TCCS - - - (1) (1) ps Output jitter (peak to peak) - - - (1) (1) ps tRISE 20 ­ 80% (1) (1) (1) (1) ps tFALL 80 ­ 20% (1) (1) (1) (1) ps HSIODR Altera Corporation July 2007 1­20 Cyclone III Device Handbook, Volume 2 Switching Characteristics Table 1­33. Three-Resistor LVDS Transmitter Timing Specification Notes (2), (5) (Part 2 of 2) ­6 Speed Grade Symbol Modes Unit Min tLOCK - - Typ - Max (3) Max (4) (1) - ms Notes to Table 1­33: (1) (2) (3) (4) (5) Pending silicon characterization. Values for device speed grade ­7 and ­8 will be available after characterization. The maximum data rate that complies with duty cycle distortion of 45­55%. The maximum data rate when taking duty cycle in absolute ps into consideration that may not comply with 45­55% duty cycle distortion. If the downstream receiver can handle duty cycle distortion beyond the 45­55% range, you may use the higher data rate values from this column. You can calculate the duty cycle distortion as a percentage using the absolute ps value. For example, for a data rate of 640 Mbps (UI = 1625 ps) and a tDUTY of 250 ps, the duty cycle distortion is tDUTY/(UI*2) *100% = 250 ps/(1625 *2) * 100% = 7.7%, which gives you a duty cycle distortion of 42.3­57.7%. Three-resistor LVDS is only supported at output pin of Column I/O (Banks 3, 4, 7, and 8). Table 1­34. Dedicated LVDS Receiver Timing Specification Notes (2), (3) ­6 Speed Grade Symbol Modes Unit Min Max ×10 10 - 437.5 MHz ×8 10 - 437.5 MHz ×7 10 - 437.5 MHz ×4 10 - 437.5 MHz ×2 fHSCLK (input clock frequency) Typ 10 - 437.5 MHz ×1 10 - 437.5 MHz ×10 100 - 875 Mbps ×8 80 - 875 Mbps ×7 70 - 875 Mbps ×4 40 - 875 Mbps ×2 HSIODR 20 - 875 Mbps ×1 10 - 437.5 Mbps SW - - - 400 ps Input jitter tolerance - - - (1) ps tLOCK - - - (1) ps Notes to Table 1­34: (1) (2) (3) Altera Corporation July 2007 Pending silicon characterization. Values for device speed grade ­7 and ­8 will be available after characterization. Dedicated LVDS Receiver is supported at all banks. 1­21 Cyclone III Device Handbook, Volume 2 Switching Characteristics External Memory Interface Specifications Cyclone III devices support external memory interfaces up to 200 MHz. Cyclone III external memory interfaces are auto-calibrating and easy to implement. Table 1­35 to Table 1­38 list the External Memory Interface Specifications for the Cyclone III device family. Use the following tables for memory interface timing analysis. Table 1­35. Cyclone III Maximum Clock Rate Support for External Memory Interfaces Notes (1) (5) Commercial Memory Standard I/O Standard ­6 Speed Grade (MHz) ­7 Speed Grade (MHz) ­8 Speed Grade (MHz) Column I/Os Row I/Os Column I/Os Row I/Os Column I/Os Row I/Os DDR2 SDRAM (2) SSTL-18 SSTL-18 class I 200 167 167 150 167 133 SSTL-18 SSTL-18 class II 133 125 125 (3) (3) (3) DDR SDRAM (2) SSTL-2 class I 167 150 150 133 133 125 SSTL-2 class II 133 125 125 100 100 (3) QDRII 1.8-V HSTL class I SRAM (4) 167 150 150 133 133 125 1.8V HSTL class II 100 (3) (3) (3) (3) (3) Notes to Table 1­35: (1) (2) (3) (4) (5) These numbers are preliminary until characterization is final. The values apply for interfaces with both modules and components. Support will be evaluated after characterization. QDRII SRAM also supports the 1.5-V HSTL I/O standard. However, Altera recommends using the 1.8-V HSTL I/O standard for maximum performance because of the higher I/O Current Strength. Column I/Os refer to Top and Bottom I/Os. Row I/Os refer to Right and Left I/Os. Table 1­36. FPGA Sampling Window (SW) Requirement ­ Read Side Note (1) ­6 Speed Grade Memory Standards Column I/Os Setup Hold ­7 Speed Grade Row I/Os Setup Preliminary Hold Column I/Os Setup ­8 Speed Grade Row I/Os Column I/Os Row I/Os Hold Setup Hold Setup Hold Setup Units Hold DDR2 SDRAM 620 620 745 745 755 755 840 840 790 790 945 945 ps DDR SDRAM 595 595 730 730 728 728 843 843 850 850 975 975 ps QDRII SRAM 695 695 780 780 790 790 885 885 895 895 970 970 ps Note to Table 1­36: (1) Column I/Os refer to Top and Bottom I/Os. Row I/Os refer to Right and Left I/Os. Altera Corporation July 2007 1­22 Cyclone III Device Handbook, Volume 2 I/O Timing Table 1­37. Transmitter Channel-to-Channel Skew (TCCS) ­ Write Side Note (1) ­6 Speed Grade Memory Standards Column I/Os Lead Lag ­7 Speed Grade Row I/Os Lead Preliminary Column I/Os Lag Lead Lag ­8 Speed Grade Row I/Os Lead Column I/Os Row I/Os Lag Lead Lag Lead Units Lag DDR2 SDRAM 585 585 645 645 595 595 650 650 595 595 660 660 ps DDR SDRAM 610 610 670 670 620 620 680 680 630 630 685 685 ps QDRII SRAM 670 670 725 725 675 675 735 735 685 685 740 740 ps Note to Table 1­37: (1) Column I/Os refer to Top and Bottom I/Os. Row I/Os refer to Right and Left I/Os. Table 1­38. DDIO Outputs Half-Period Jitter Name Description tOUTFULLJITTER Max Unit (1) Half-period jitter (PLL driving DDIO outputs) ps Note to Table 1­38: (1) Pending silicon characterization. DCD Specifications Table 1­39 lists the worst case duty cycle distortion for Cyclone III devices. Detailed information on duty cycle distortion will be published after characterization. Table 1­39. Duty Cycle Distortion on Cyclone III I/O Pins Notes (1) (2) ­6 Speed Grade ­7 Speed Grade ­8 Speed Grade Symbol Unit Min Output Duty Cycle Max Min Max Min Max 45 55 45 55 40 60 % Notes to Table 1­39: (1) (2) I/O Timing Preliminary DCD specification applies to clock outputs from PLLs, global clock tree and IOE driving dedicated and general purpose I/O pins. Detailed DCD specification pending silicon characterization. Timing Model The DirectDriveTM technology and MultiTrackTM interconnect ensure predictable performance, accurate simulation, and accurate timing analysis across all Cyclone III device densities and speed grades. This section describes and specifies the performance of I/Os and internal timing. All specifications are representative of worst-case supply voltage and junction temperature conditions. 1 Altera Corporation July 2007 The timing numbers listed in the tables of this section are extracted from the Quartus II software version 7.0 Build 31. 1­23 Cyclone III Device Handbook, Volume 2 Cyclone III Device Datasheet: DC and Switching Characteristics Preliminary, Correlated and Final Timing Timing models can have either preliminary, correlated, or final status. The Quartus II software issues an informational message during the design compilation if the timing models are preliminary. Table 1­40 shows the status of the Cyclone III device timing models. Preliminary status means the timing model is subject to change. Initially, timing numbers are created using simulation results, process data, and other known parameters. These tests are used to make the preliminary numbers as close to the actual timing parameters as possible. Correlated numbers are based on actual device operation and testing. These numbers reflect the actual performance of the device under worst-case voltage and junction temperature conditions. Final timing numbers are based on complete correlation to actual devices and addressing any minor deviations from the correlated timing model. When the timing models are final, all or most of the Cyclone III family devices have been completely characterized and no further changes to the timing model are expected. Table 1­40. Cyclone III Device Timing Model Status Device Preliminary Correlated Final EP3C5 (1) - - EP3C10 EP3C10 v - - EP3C16 EP3C16 v - - EP3C25 EP3C25 v - - EP3C40 EP3C40 v - - EP3C55 EP3C55 v - - EP3C80 EP3C80 v - - EP3C120 EP3C120 v - - Note to Table 1­40: (1) Timing model for EP3C5 will be available in Quartus II software 7.1. I/O Timing Measurement Methodology Altera characterizes timing delays at the worst-case process, minimum voltage, and maximum temperature for input register setup time (tSU) and hold time (tH). The Quartus II software uses the following equations to calculate tSU and tH timing for Cyclone III devices input signals: tSU = + data delay from input pin to input register + micro setup time of the input register ­ clock delay from input pin to input register tH = ­ data delay from input pin to input register + micro hold time of the input register + clock delay from input pin to input register Figure 1­2 shows the setup and hold timing diagram for input registers. 1­24 Cyclone III Device Handbook, Volume 2 Altera Corporation July 2007 I/O Timing Figure 1­2. Input Register Setup and Hold Timing Diagram Input Data Delay micro tSU micro tH Input Clock Delay For output timing, different I/O standards require different baseline loading techniques for reporting timing delays. Altera characterizes timing delays with the required termination for each I/O standard and with 0 pF (except for PCI and PCI-X which use 10 pF) loading and the timing is specified up to the output pin of the FPGA device. The Quartus II software calculates the I/O timing for each I/O standard with a default baseline loading as specified by the I/O standards. The following measurements are made during device characterization. Altera measures clock-to-output delays (tCO) at worst-case process, minimum voltage, and maximum temperature (PVT) for default loading conditions shown in Table 1­41. Use the following equations to calculate clock pin to output pin timing for Cyclone III devices. tCO from clock pin to I/O pin = + delay from clock pad to I/O output register + IOE output register clock-to-output delay + delay from output register to output pin Figure 1­3. Output Register Clock to Output Timing Diagram output Datain Output Register micro tCO Clock Clock pad to output Register delay Output Register to output pin delay Simulation using IBIS models is required to determine the delays on the PCB traces in addition to the output pin delay timing reported by the Quartus II software and the timing model in the device handbook. 1. 2. Record the time to VMEAS. 3. Altera Corporation July 2007 Simulate the output driver of choice into the generalized test setup, using values from Table 1­41. Simulate the output driver of choice into the actual PCB trace and load, using the appropriate IBIS model or capacitance value to represent the load. 1­25 Cyclone III Device Handbook, Volume 2 Cyclone III Device Datasheet: DC and Switching Characteristics 4. Record the time to VMEAS. 5. Compare the results of steps 2 and 4. The increase or decrease in delay should be added to or subtracted from the I/O Standard Output Adder delays to yield the actual worst-case propagation delay (clock-to-output) of the PCB trace. The Quartus II software reports the timing with the conditions shown in Table 1­41 using the above equation. Figure 1­4 shows the model of the circuit that is represented by the output timing of the Quartus II software. Figure 1­4. Output Delay Timing Reporting Setup Modeled by Quartus II Notes (1), (2) VTT VCCIO RT Output Buffer Outputp RS Output VMEAS CL GND Outputn RD GND Notes to Figure 1­4: (1) (2) Output pin timing is reported at the output pin of the FPGA device. Additional delays for loading and board trace delay need to be accounted for with IBIS model simulations. VCCINT is 1.10 V unless otherwise specified. Figure 1­5 and Figure 1­6 show the I/O interface with single and multiple external output resistors. Figure 1­5. I/O Interface with Single External Output Resistor Differential Inputs Differential Outputs Z = 50 RD RP Z = 50 Figure 1­6. I/O Interface with Three External Output Resistor Network Differential Inputs Differential Outputs Z = 50 RS RS RD RP Z = 50 1­26 Cyclone III Device Handbook, Volume 2 Altera Corporation July 2007 I/O Timing Table 1­41. Output Timing Measurement Methodology for Output Pins Notes (1), (2), (4), (5) Preliminary Measurement Point Loading and Termination I/O Standard RS () RT () RD () RP () VCCIO (V) VTT (V) CL (pF) VMEAS (V) 3.3-V LVTTL - - - - 3.135 - 0 1.5675 3.3-V LVCMOS - - - - 3.135 - 0 1.5675 3.0-V LVTTL - - - - 2.85 - 0 1.425 3.0-V LVCMOS - - - - 2.85 - 0 1.425 2.5-V LVTTL/LVCMOS - - - - 2.375 - 0 1.1875 1.8-V LVTTL/LVCMOS - - - - 1.71 - 0 0.855 1.5-V LVCMOS - - - - 1.425 - 0 0.7125 1.2-V LVCMOS - - - - 1.15 - 0 0.575 3.0-V PCI - - - - 2.85 - 10 1.425 3.0-V PCI-X - - - - 2.85 - 10 1.425 SSTL-2 Class I 25 50 - - 2.375 1.1875 0 1.1875 SSTL-2 Class II 25 25 - - 2.375 1.1875 0 1.1875 SSTL-18 SSTL-18 Class I 25 50 - - 1.71 0.855 0 0.855 SSTL-18 SSTL-18 Class II 25 25 - - 1.71 0.855 0 0.855 1.8-V HSTL Class I 50 50 - - 1.71 0.855 0 0.855 1.8-V HSTL Class II 25 25 - - 1.71 0.855 0 0.855 1.5-V HSTL Class I 50 50 - - 1.425 0.7125 0 0.7125 1.5-V HSTL Class II - 25 - - 1.425 0.7125 0 0.7125 1.2-V HSTL CLASS I - 50 - - 1.15 0.575 0 0.575 1.2-V HSTL CLASS II - 25 (50 || 50) - - 1.15 0.575 0 0.575 LVDS LVDS_E_3R mini-LVDS mini-LVDS_E_3R PPDS - - 100 - 2.375 - 0 1.1875 120 (6) - 100 170 (6) 2.375 - 0 1.1875 - - 100 - 2.375 - 0 1.1875 120 (6) - 100 170 (6) 2.375 - 0 1.1875 - - 100 - 2.375 - 0 1.1875 120 (6) - 100 170 (6) 2.375 - 0 1.1875 RSDS - - 100 - 2.375 - 0 1.1875 RSDS_E_1R - - 100 100 (6) 2.375 - 0 1.1875 RSDS_E_3R 120 (6) - 100 170 (6) 2.375 - 0 1.1875 PPDS_E_3R Notes to Table 1­41: (1) (2) (3) (4) (5) (6) Input measurement point at internal node is 0.5 × VCCINT. Output measuring point for VMEAS at buffer output is 0.5 × VCCIO. Input stimulus edge rate is 0 to VCC in 0.2 ns (internal signal) from the driver preceding the I/O buffer. Less than 50-mV ripple on VCCIO. VCCINT = 1.10 V with less than 30-mV ripple. The interface has to use external termination RT. The termination voltage VTT may either be supplied by an independent power supply or created through a Thevenin equivalent circuit. Pending silicon characterization. Altera Corporation July 2007 1­27 Cyclone III Device Handbook, Volume 2 Cyclone III Device Datasheet: DC and Switching Characteristics I/O Default Capacitive Loading Refer to Table 1­42 for default capacitive loading of different I/O standards. Table 1­42. Default Loading of Different I/O Standards for Cyclone III I/O Standard 3.3-V LVTTL Preliminary Capacitive Load Unit 0 pF 3.3-V LVCMOS 0 pF 3.0-V LVTTL 0 pF 3.0-V LVCMOS 0 pF 2.5-V LVTTL/LVCMOS 0 pF 1.8-V LVTTL/LVCMOS 0 pF 1.5-V LVCMOS 0 pF 1.2-V LVCMOS 0 pF 3.0-V PCI 10 pF 3.0-V PCI-X 10 pF SSTL-2 Class I 0 pF SSTL-2 Class II 0 pF SSTL-18 SSTL-18 Class I 0 pF SSTL-18 SSTL-18 Class II 0 pF 1.8-V HSTL Class I 0 pF 1.8-V HSTL Class II 0 pF 1.5-V HSTL Class I 0 pF 1.5-V HSTL Class II 0 pF 1.2-V HSTL CLASS I 0 pF 1.2-V HSTL CLASS II 0 pF Differential SSTL-2 Class I 0 pF Differential SSTL-2 Class II 0 pF Differential SSTL-18 SSTL-18 Class I 0 pF Differential SSTL-18 SSTL-18 Class II 0 pF 1.2-V Differential HSTL Class I 0 pF 1.2-V Differential HSTL Class II 0 pF 1.5-V Differential HSTL Class I 0 pF 1.5-V Differential HSTL Class II 0 pF 1.8-V Differential HSTL Class I 0 pF 1.8-V Differential HSTL Class II 0 pF LVDS 0 pF LVDS_E_3R 0 pF mini-LVDS 0 pF mini-LVDS_E_3R 0 pF PPDS 0 pF PPDS_E_3R 0 pF RSDS 0 pF RSDS_E_1R 0 pF RSDS_E_3R 0 pF 1­28 Cyclone III Device Handbook, Volume 2 Altera Corporation July 2007 I/O Timing Maximum Input and Output Clock Toggle Rate The maximum clock toggle rate is defined as the maximum frequency achievable for a clock type signal at an I/O pin. The I/O pin can be a regular I/O pin or a dedicated clock I/O pin. The maximum clock toggle rate is different from the maximum data bit rate. If the maximum clock toggle rate on a regular I/O pin is 300 MHz, the maximum data bit rate for dual data rate (DDR) could be potentially as high as 600 Mbps on the same I/O pin. Table 1­43 specifies the maximum input clock toggle rates. Table 1­44 specifies the maximum output clock toggle rates at 0 pF load. Table 1­45 specifies the derating factors for the output clock toggle rate for a non 0 pF load. To calculate the output toggle rate for a non 0 pF load, use this formula: The toggle rate for a non 0 pF load = 1000 / (1000/ toggle rate at 0 pF load + derating factor * load value in pF /1000) For example, the output toggle rate at 0 pF load for SSTL-18 SSTL-18 Class II 16 A I/O standard is 260 MHz on a ­6 device clock output pin. The derating factor is 26 ps/pF. For a 10 pF load the toggle rate is calculated as: 1000 / (1000/260 + 26 × 10 /1000) = 243 (MHz) Table 1­43 through Table 1­45 show the I/O toggle rates for Cyclone III devices. Table 1­43. Maximum Input Toggle Rate on Cyclone III Devices (Part 1 of 2) Preliminary Maximum Input Toggle Rate on CIII Devices (MHz) Column I/O Pins I/O Standard Row I/O Pins Dedicated Clock Inputs ­6 Speed Grade ­7 Speed Grade ­8 Speed Grade ­6 Speed Grade ­7 Speed Grade ­8 Speed Grade ­6 Speed Grade ­7 Speed Grade ­8 Speed Grade 3.3-V LVTTL 450 405 360 450 405 360 450 405 360 3.3-V LVCMOS 450 405 360 450 405 360 450 405 360 3.0-V LVTTL 450 405 360 450 405 360 450 405 360 3.0-V LVCMOS 450 405 360 450 405 360 450 405 360 2.5-V LVTTL/LVCMOS 450 405 360 450 405 360 450 405 360 1.8-V LVTTL/LVCMOS 450 405 360 450 405 360 450 405 360 1.5-V LVCMOS 300 270 240 300 270 240 300 270 240 1.2-V LVCMOS 300 270 240 300 270 240 300 270 240 SSTL_2_CLASS_I 500 500 500 500 500 500 500 500 500 SSTL_2_CLASS_II 500 500 500 500 500 500 500 500 500 SSTL_18_CLASS_I 500 500 500 500 500 500 500 500 500 SSTL_18_CLASS_II 500 500 500 500 500 500 500 500 500 1.8 V_HSTL_CLASS_I 500 500 500 500 500 500 500 500 500 1.8 V_HSTL_CLASS_II 500 500 500 500 500 500 500 500 500 1.5 V_HSTL_CLASS_I 500 500 500 500 500 500 500 500 500 1.5 V_HSTL_CLASS_II 500 500 500 500 500 500 500 500 500 1.2 V_HSTL_CLASS_I 500 500 500 500 500 500 500 500 500 1.2 V_HSTL_CLASS_II 500 500 500 (1) (1) (1) 500 500 500 3.0-V PCI 350 315 280 350 315 280 350 315 280 Altera Corporation July 2007 1­29 Cyclone III Device Handbook, Volume 2 Cyclone III Device Datasheet: DC and Switching Characteristics Table 1­43. Maximum Input Toggle Rate on Cyclone III Devices (Part 2 of 2) Preliminary Maximum Input Toggle Rate on CIII Devices (MHz) Column I/O Pins I/O Standard Row I/O Pins Dedicated Clock Inputs ­6 Speed Grade ­7 Speed Grade ­8 Speed Grade ­6 Speed Grade ­7 Speed Grade ­8 Speed Grade ­6 Speed Grade ­7 Speed Grade ­8 Speed Grade 3.0-V PCI-X 350 315 280 350 315 280 350 315 280 DIFFERENTIAL_SSTL_2_CLASS_I (2) (2) (2) (2) (2) (2) 500 500 500 DIFFERENTIAL_SSTL_2_CLASS_II (2) (2) (2) (2) (2) (2) 500 500 500 DIFFERENTIAL_SSTL_18_CLASS_I (2) (2) (2) (2) (2) (2) 500 500 500 DIFFERENTIAL_SSTL_18_CLASS_II (2) (2) (2) (2) (2) (2) 500 500 500 1.8 V_DIFFERENTIAL_HSTL_CLASS_I (2) (2) (2) (2) (2) (2) 500 500 500 1.8 V_DIFFERENTIAL_HSTL_CLASS_II (2) (2) (2) (2) (2) (2) 500 500 500 1.5 V_DIFFERENTIAL_HSTL_CLASS_I (2) (2) (2) (2) (2) (2) 500 500 500 1.5 V_DIFFERENTIAL_HSTL_CLASS_II (2) (2) (2) (2) (2) (2) 500 500 500 1.2 V_DIFFERENTIAL_HSTL_CLASS_I (2) (2) (2) (2) (2) (2) 500 500 500 1.2 V_DIFFERENTIAL_HSTL_CLASS_II (2) (2) (2) (2) (2) (2) 500 500 500 LVPECL (3) (3) (3) (3) (3) (3) 403 403 403 LVDS 403 403 403 438 438 438 403 403 403 Notes to Table 1­43: (1) (2) (3) The 1.2 V_HSTL_CLASS_II is only supported on column I/O pins. Input differential standard is only supported on GCLK pin. Input LVPECL is only supported on GCLK pin. Table 1­44. Maximum Output Toggle Rate on Cyclone III Devices (Part 1 of 4) Preliminary Maximum Output Toggle Rate on CIII Devices (MHz) Column I/O Pins Row I/O Pins Dedicated Clock Inputs ­6 Speed Grade I/O Standard ­7 Speed Grade ­8 Speed Grade ­6 Speed Grade ­7 Speed Grade ­8 Speed Grade ­6 Speed Grade ­7 Speed Grade ­8 Speed Grade 120 100 80 120 100 80 120 100 80 3.3-V LVTTL 4 mA 8 mA 200 170 140 200 170 140 200 170 140 3.3-V LVCMOS 2 mA 120 100 80 120 100 80 120 100 80 3.0-V LVTTL 155 125 100 86 70 185 155 125 190 150 170 145 120 220 190 150 300 245 200 240 200 160 300 245 200 16 mA 311 260 215 250 205 170 311 260 215 4 mA 280 233 190 195 165 130 280 233 190 8 mA 280 233 190 220 180 150 280 233 190 12 mA 300 250 205 240 200 165 300 250 205 16 mA 1­30 Cyclone III Device Handbook, Volume 2 185 220 12 mA 3.0-V LVCMOS 4 mA 8 mA 311 260 210 250 210 170 311 260 210 Altera Corporation July 2007 I/O Timing Table 1­44. Maximum Output Toggle Rate on Cyclone III Devices (Part 2 of 4) Preliminary Maximum Output Toggle Rate on CIII Devices (MHz) Column I/O Pins ­6 Speed Grade I/O Standard 2.5-V LVTTL/LVCMOS ­7 Speed Grade ­8 Speed Grade Row I/O Pins ­6 Speed Grade ­7 Speed Grade Dedicated Clock Inputs ­8 Speed Grade ­6 Speed Grade ­7 Speed Grade ­8 Speed Grade 200 166 133 100 83 66 200 166 133 200 166 133 155 130 100 200 166 133 12 mA 305 255 210 245 205 165 305 255 210 16 mA 1.8-V LVTTL/LVCMOS 4 mA 8 mA 311 280 240 250 225 195 311 280 240 2 mA 210 170 140 85 70 60 210 170 140 4 mA 255 210 170 130 110 85 255 210 170 6 mA 285 233 195 160 130 110 285 233 195 8 mA 250 210 166 170 140 115 250 210 166 10 mA 266 220 185 215 180 150 266 220 185 12 mA 311 260 210 250 210 170 311 260 210 16 mA 311 260 210 250 210 170 311 260 210 2 mA 290 145 120 60 45 36 290 145 120 4 mA 225 190 155 93 80 66 225 190 155 6 mA 1.5-V LVCMOS 245 200 166 129 110 86 245 200 166 8 mA 166 166 136 115 240 195 166 220 185 215 180 150 266 220 185 311 260 210 250 210 170 311 260 210 16 mA 311 260 210 250 210 170 311 260 210 2 mA 190 145 120 66 50 40 190 145 120 4 mA 225 190 155 110 90 75 225 190 155 6 mA 245 200 166 150 125 100 245 200 166 8 mA 240 197 166 192 160 133 240 197 166 10 mA 266 220 185 250 210 175 266 220 185 12 mA 311 260 210 (2) (2) (2) 311 260 210 8 mA 300 255 210 250 210 175 300 255 210 12 mA SSTL_2_CLASS_I 195 266 12 mA 1.2-V LVCMOS 240 10 mA 300 255 210 250 210 175 300 255 210 SSTL_2_CLASS_II 16 mA 300 250 205 250 205 170 300 250 205 SSTL_18_CLASS_I 8 mA 320 270 220 280 233 190 320 270 220 10 mA 320 260 215 290 233 290 320 260 215 12 mA 333 270 225 300 250 200 333 270 225 12 mA 333 280 233 266 233 190 333 280 233 16 mA 333 280 233 300 250 210 333 280 233 8 mA 290 245 200 270 230 190 290 245 200 10 mA 310 260 220 310 260 220 310 260 220 SSTL_18_CLASS_II 1.8 V_HSTL_CLASS_I 12 mA 1.5 V_HSTL_CLASS_I 333 280 230 333 280 230 333 280 230 16 mA 333 275 233 300 250 210 333 275 233 8 mA 320 260 210 275 220 180 320 260 210 10 mA 1.8 V_HSTL_CLASS_II 320 260 220 285 235 195 320 260 220 12 mA 1.5 V_HSTL_CLASS_II Altera Corporation July 2007 333 275 233 300 250 210 333 275 233 16 mA 333 270 222 300 240 200 333 270 222 1­31 Cyclone III Device Handbook, Volume 2 Cyclone III Device Datasheet: DC and Switching Characteristics Table 1­44. Maximum Output Toggle Rate on Cyclone III Devices (Part 3 of 4) Preliminary Maximum Output Toggle Rate on CIII Devices (MHz) Column I/O Pins Row I/O Pins Dedicated Clock Inputs ­6 Speed Grade ­7 Speed Grade ­8 Speed Grade ­6 Speed Grade ­7 Speed Grade ­8 Speed Grade ­6 Speed Grade ­7 Speed Grade ­8 Speed Grade 8 mA 240 190 160 250 205 160 240 190 160 10 mA 240 195 160 250 205 160 240 195 160 I/O Standard 1.2 V_HSTL_CLASS_I 12 mA 1.2 V_HSTL_CLASS_II 250 210 175 (2) (2) (2) 250 210 175 14 mA 250 200 166 (2) (2) (2) 250 200 166 3.0-V PCI - 133 120 106 133 120 105 133 120 106 3.0-V PCI-X - 133 120 106 133 120 105 133 120 106 8 mA (3) (3) (3) (3) (3) (3) 400 340 280 12 mA (3) (3) (3) (3) (3) (3) 400 340 280 DIFFERENTIAL_SSTL_2_CLASS_I DIFFERENTIAL_SSTL_2_CLASS_II 16 mA (3) (3) (3) (3) (3) (3) 350 290 240 DIFFERENTIAL_SSTL_18_CLASS_I 8 mA (3) (3) (3) (3) (3) (3) 260 220 180 10 mA (3) (3) (3) (3) (3) (3) 270 220 180 12 mA (3) (3) (3) (3) (3) (3) 280 230 190 DIFFERENTIAL_SSTL_18_CLASS_II 16 mA (3) (3) (3) (3) (3) (3) 260 220 180 1.8 V_DIFFERENTIAL_HSTL_CLASS_I 8 mA (3) (3) (3) (3) (3) (3) 260 220 180 10 mA (3) (3) (3) (3) (3) (3) 300 250 210 12 mA (3) (3) (3) (3) (3) (3) 320 270 220 1.8 V_DIFFERENTIAL_HSTL_CLASS_II 16 mA (3) (3) (3) (3) (3) (3) 230 190 160 1.5 V_DIFFERENTIAL_HSTL_CLASS_I 8 mA (3) (3) (3) (3) (3) (3) 210 170 140 10 mA (3) (3) (3) (3) (3) (3) 220 180 150 12 mA (3) (3) (3) (3) (3) (3) 230 190 160 1.5 V_DIFFERENTIAL_HSTL_CLASS_II 16 mA (3) (3) (3) (3) (3) (3) 210 170 140 1.2 V_DIFFERENTIAL_HSTL_CLASS_I 8 mA (3) (3) (3) (3) (3) (3) 210 170 140 10 mA (3) (3) (3) (3) (3) (3) 220 180 150 12 mA (3) (3) (3) (3) (3) (3) 230 190 160 14 mA (3) (3) (3) (3) (3) (3) 210 170 140 LVDS - (6) (6) (6) 438 370 305 438 370 305 1.2 V_DIFFERENTIAL_HSTL_CLASS_II LVDS_E_3R - 350 300 245 (5) (5) (5) 438 370 305 mini-LVDS - (4) (4) (4) 200 170 140 200 170 140 mini-LVDS_E_3R - 200 170 140 (5) (5) (5) 200 170 140 PPDS - (4) (4) (4) 220 187 154 220 187 154 PPDS_E_3R - 220 187 154 (5) (5) (5) 220 187 154 RSDS - (4) (4) (4) 180 153 126 180 153 126 RSDS_E_1R - 180 153 126 (5) (5) (5) 180 153 126 RSDS_E_3R - 180 153 126 (5) (5) (5) 180 153 126 OCT_25_ OHMS (1) (1) (1) (1) (1) (1) (1) (1) (1) OCT_50_ OHMS (1) (1) (1) (1) (1) (1) (1) (1) (1) 3.0-V LVTTL/LVCMOS 1­32 Cyclone III Device Handbook, Volume 2 Altera Corporation July 2007 I/O Timing Table 1­44. Maximum Output Toggle Rate on Cyclone III Devices (Part 4 of 4) Preliminary Maximum Output Toggle Rate on CIII Devices (MHz) Column I/O Pins Row I/O Pins Dedicated Clock Inputs ­6 Speed Grade ­7 Speed Grade ­8 Speed Grade ­6 Speed Grade ­7 Speed Grade ­8 Speed Grade ­6 Speed Grade ­7 Speed Grade ­8 Speed Grade OCT_25_ OHMS (1) (1) (1) (1) (1) (1) (1) (1) (1) OCT_50_ OHMS (1) (1) (1) (1) (1) (1) (1) (1) (1) OCT_25_ OHMS (1) (1) (1) (1) (1) (1) (1) (1) (1) OCT_50_ OHMS (1) (1) (1) (1) (1) (1) (1) (1) (1) OCT_25_ OHMS (1) (1) (1) (1) (1) (1) (1) (1) (1) OCT_50_ OHMS (1) (1) (1) (1) (1) (1) (1) (1) (1) I/O Standard 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.2-V LVTTL/LVCMOS Notes to Table 1­44: (1) (2) (3) (4) (5) (6) The current version of the Quartus II software does not have the information for the standard. The 1.2 V (12 mA) and 1.2 V_HSTL_CLASS_I / II (12 mA and 14 mA respectively) are only supported on column I/O pins. Output differential standard is only supported on PLLCLKOUT pin. Dedicated differential standards are supported at row I/O pins. Differential standards with external resistor network are supported at column I/O pins. Output dedicated LVDS is only supported on row I/O pins. Input dedicated LVDS is supported at all I/O pins. Table 1­45. Maximum Output Clock Toggle Rate Derating Factors on Cyclone III Devices (Part 1 of 3) Preliminary Maximum Output Clock Toggle Rate Derating Factors (ps/pf) I/O Standard 3.3-V LVTTL Current Strength or OCT Setting 4 mA Column I/O Pins Row I/O Pins ­6 Speed Grade ­7 Speed Grade ­8 Speed Grade ­6 Speed Grade ­7 Speed Grade ­8 Speed Grade 117 123 123 116 122 122 8 mA 3.3V LVCMOS 50 52 52 50 52 52 2 mA (1) (1) (1) (1) (1) (1) 4 mA (1) (1) (1) (1) (1) (1) 8 mA (1) (1) (1) (1) (1) (1) 12 mA (1) (1) (1) (1) (1) (1) 16 mA 3.0-V LVTTL (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) 12 mA (1) (1) (1) (1) (1) (1) 16 mA Altera Corporation July 2007 4 mA 8 mA 3.0-V LVCMOS (1) (1) (1) (1) (1) (1) 1­33 Cyclone III Device Handbook, Volume 2 Cyclone III Device Datasheet: DC and Switching Characteristics Table 1­45. Maximum Output Clock Toggle Rate Derating Factors on Cyclone III Devices (Part 2 of 3) Preliminary Maximum Output Clock Toggle Rate Derating Factors (ps/pf) I/O Standard Current Strength or OCT Setting Column I/O Pins Row I/O Pins ­7 Speed Grade ­8 Speed Grade ­6 Speed Grade ­7 Speed Grade ­8 Speed Grade 4 mA 36 37 37 35 37 37 8 mA 30 32 32 30 32 32 12 mA 2.5-V LVTTL/LVCMOS ­6 Speed Grade 27 28 28 (1) (1) (1) 16 mA 26 27 27 (1) (1) (1) 2 mA 115 121 121 116 121 121 4 mA 93 97 97 91 96 96 6 mA 1.8-V LVTTL/LVCMOS 48 50 50 47 50 50 8 mA 39 41 41 39 41 41 10 mA 36 37 37 35 37 37 12 mA 35 33 34 34 (1) (1) (1) (1) (1) 2 mA 164 172 172 164 172 172 92 96 96 91 96 96 6 mA 44 46 46 43 45 45 8 mA 37 39 39 (1) (1) (1) 10 mA (1) (1) (1) (1) (1) (1) 12 mA (1) (1) (1) (1) (1) (1) 16 mA (1) (1) (1) (1) (1) (1) 2 mA (1) (1) (1) (1) (1) (1) 4 mA (1) (1) (1) (1) (1) (1) 6 mA 1.2-V LVCMOS 35 (1) 4 mA 1.5-V LVCMOS 33 16 mA (1) (1) (1) (1) (1) (1) 8 mA (1) (1) (1) (1) (1) (1) 10 mA (1) (1) (1) (1) (1) (1) 12 mA (1) (1) (1) (2) (2) (2) SSTL_2_CLASS_I 8 mA 26 27 27 25 27 27 12 mA 25 26 26 25 26 26 SSTL_2_CLASS_II 16 mA 28 29 29 27 28 28 8 mA 24 25 25 23 24 24 10 mA 23 24 24 24 25 25 SSTL_18_CLASS_I 12 mA SSTL_18_ CLASS_II 24 25 25 (1) (1) (1) 16 mA 26 27 27 (1) (1) (1) 18 mA 27 (1) (1) (1) 25 25 25 26 26 26 27 27 23 24 24 26 28 28 25 26 26 12 mA (1) (1) (1) (1) (1) (1) 16 mA 1­34 Cyclone III Device Handbook, Volume 2 27 24 12 mA 1.8 V_HSTL_ CLASS_II 26 8 mA 10 mA 1.8 V_HSTL_ CLASS_I 30 31 31 (1) (1) (1) Altera Corporation July 2007 I/O Timing Table 1­45. Maximum Output Clock Toggle Rate Derating Factors on Cyclone III Devices (Part 3 of 3) Preliminary Maximum Output Clock Toggle Rate Derating Factors (ps/pf) I/O Standard Current Strength or OCT Setting Column I/O Pins Row I/O Pins ­7 Speed Grade ­8 Speed Grade ­6 Speed Grade ­7 Speed Grade ­8 Speed Grade 8 mA 26 28 28 25 26 26 10 mA 25 27 27 (1) (1) (1) 12 mA 1.5 V_HSTL_ CLASS_I ­6 Speed Grade 25 26 26 (1) (1) (1) 1.5 V_HSTL_ CLASS_II 16 mA 31 33 33 (1) (1) (1) 1.2 V_HSTL_ CLASS_I 8 mA (1) (1) (1) (1) (1) (1) 10 mA (1) (1) (1) (1) (1) (1) 12 mA (1) (1) (1) (2) (2) (2) 14 mA (1) (1) (1) (2) (2) (2) - (1) (1) (1) (1) (1) (1) 3.0-V PCI-X - (1) (1) (1) (1) (1) (1) LVDS - (6) (6) (6) 39 41 41 LVDS_E_3R - (1) (1) (1) (5) (5) (5) mini-LVDS - (4) (4) (4) (1) (1) (1) mini-LVDS_E_3R - (1) (1) (1) (5) (5) (5) PPDS - (4) (4) (4) (1) (1) (1) PPDS_E_3R - (1) (1) (1) (5) (5) (5) RSDS - (4) (4) (4) (1) (1) (1) RSDS_E_1R - (1) (1) (1) (5) (5) (5) RSDS_E_3R - (1) (1) (1) (5) (5) (5) OCT_25_OHMS (1) (1) (1) (1) (1) (1) OCT_50_OHMS (1) (1) (1) (1) (1) (1) 1.2 V_HSTL_ CLASS_II 3.0-V PCI 3.0-V OCT_25_OHMS (1) (1) (1) (1) (1) (1) OCT_50_OHMS 2.5-V LVTTL/LVCMOS 240 200 160 240 200 160 (1) (1) (1) (1) (1) (1) 290 240 200 290 240 200 OCT_25_OHMS (1) (1) (1) (1) (1) (1) OCT_50_OHMS 1.2-V LVCMOS OCT_25_OHMS OCT_50_OHMS 1.8-V LVTTL/LVCMOS (1) (1) (1) (1) (1) (1) Notes to Table 1­45: (1) (2) (3) (4) (5) (6) (7) Altera Corporation July 2007 Current version of Quartus II software does not have the information for the standard. The 1.2 V (12 mA) and 1.2 V_HSTL_CLASS_I/II (12 mA and 14 mA, respectively) are only supported on column I/O pins. Output differential standard is only supported on PLLCLKOUT pin. Dedicated differential standards are supported at row I/O pins. Differential standards with external resistor network are supported at column I/O pins. Output dedicated LVDS is only supported on row I/O pins. Input dedicated LVDS is supported at all I/O pins. Indicate the lowest value of derating factor. 1­35 Cyclone III Device Handbook, Volume 2 Cyclone III Device Datasheet: DC and Switching Characteristics IOE Programmable Delay Table 1­46 and Table 1­47 show IOE programmable delay for Cyclone III devices. Table 1­46. Cyclone III IOE Programmable Delay on Column Pins Notes (1), (2) Fast Corner (3) ­6 Speed Grade ­7 Speed Grade ­8 Speed Grade Parameter Paths Affected Number of Settings Min Offset Max Offset Min Offset Max Offset Min Offset Max Offset Min Offset Max Offset Unit Input Delay from Pin to Internal Cells Pad to I/O dataout to core 7 0 1.369 0 2.267 0 2.413 0 2.526 ns Input Delay from Pin to Input Register Pad to I/O input register 8 0 1.528 0 2.446 0 2.571 0 2.696 ns Delay from Output Register to Output Pin I/O output register to Pad 2 0 0.582 0 1 0 1.098 0 1.199 ns Notes to Table 1­46: (1) (2) (3) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of Quartus II software. The minimum and maximum offset timing numbers are in reference to setting "0" as available in the Quartus II software. The fast model timing parameter is for commercial devices. Table 1­47. Cyclone III IOE Programmable Delay on Row Pins Notes (1), (2) Parameter Paths Affected Number of Settings Fast Corner (3) ­6 Speed Grade ­7 Speed Grade ­8 Speed Grade Min Offset Max Offset Min Offset Max Offset Min Offset Max Offset Min Offset Max Offset Unit Input Delay from Pin to Internal Cells Pad to I/O dataout to core 7 0 1.369 0 2.244 0 2.39 0 2.495 ns Input Delay from Pin to Input Register Pad to I/O input register 8 0 1.538 0 2.459 0 2.586 0 2.716 ns Delay from Output Register to Output Pin I/O output register to Pad 2 0 0.62 0 1.065 0 1.171 0 1.277 ns Notes to Table 1­47: (1) (2) (3) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of Quartus II software. The minimum and maximum offset timing numbers are in reference to setting "0" as available in the Quartus II software. The fast model timing parameter is for commercial devices. Typical Design Performance User I/O Pin Timing Parameters Table 1­48 to Table 1­95 show user I/O pin timing for Cyclone III devices. I/O buffer tSU, tH and tCO are reported for the cases when clock is driven by global clock and a PLL. The 12 A programmable current strength for 1.2 V and 1.2-V HSTL Class I I/O standard is not supported at row I/Os. The 1.2-V HSTL Class II standard is only supported at column I/Os. PCI and PCI-X do not support programmable current strength. f For more information about programmable current strength, refer to the Cyclone III Device I/O Features chapter of the Cyclone III Handbook. Dedicated LVDS, mini-LVDS, PPDS, and RSDS I/O standards are supported at row I/Os. External resistor networks are required if the differential standards are used as output pins at column banks. LVDS I/O standard is supported at both input and output pins. PPDS, RSDS, and mini-LVDS standards are only supported at output pins. 1­36 Cyclone III Device Handbook, Volume 2 Altera Corporation July 2007 Typical Design Performance f For more information about the differential I/O interface, refer to High-Speed Differential Interfaces in Cyclone III Devices of the Cyclone III Handbook. EP3C5 I/O Timing Parameters Table 1­48 through Table 1­53 show the maximum I/O timing parameters for EP3C5 devices. Table 1­48. EP3C5 Column I/O Pin Input Timing Parameters for Single-Ended I/O Standards (Part 1 of 6) IO Standard 3.3-V LVTTL Current Strength 4 mA Clock ­6 ­7 ­8 Units tS U 1.123 1.156 1.167 ns tH ­0.843 ­0.838 ­0.813 ns GCLK PLL tS U 2.969 3.178 3.368 ns tH ­2.689 ­2.860 ­3.014 ns GCLK tS U 1.123 1.156 1.167 ns tH 8 mA GCLK Parameter ­0.843 ­0.838 ­0.813 ns GCLK PLL GCLK GCLK PLL 3.178 3.368 ns ­2.689 ­2.860 ­3.014 ns tS U 1.123 1.156 1.167 ns tH 2 mA 2.969 tH 3.3-V LVCMOS tS U ­0.843 ­0.838 ­0.813 ns 3.368 ns ­2.860 ­3.014 ns GCLK tS U 1.123 1.156 1.167 ns tH ­0.843 ­0.838 ­0.813 ns tS U 2.969 3.178 3.368 ns tH 8 mA 3.178 ­2.689 GCLK PLL 4 mA 2.969 tH 3.0-V LVTTL tS U ­2.689 ­2.860 ­3.014 ns GCLK 1.167 ns ­0.838 ­0.813 ns tS U 2.969 3.178 3.368 ns ­2.689 ­2.860 ­3.014 ns tS U 1.123 1.156 1.167 ns tH ­0.843 ­0.838 ­0.813 ns GCLK PLL tS U 2.969 3.178 3.368 ns tH ­2.689 ­2.860 ­3.014 ns GCLK tS U 1.123 1.156 1.167 ns tH 16 mA GCLK 1.156 ­0.843 tH 12 mA 1.123 tH GCLK PLL tS U ­0.843 ­0.838 ­0.813 ns GCLK PLL GCLK GCLK PLL 3.178 3.368 ns ­2.689 ­2.860 ­3.014 ns tS U 1.123 1.156 1.167 ns tH 4 mA 2.969 tH 3.0-V LVCMOS tS U ­0.843 ­0.838 ­0.813 ns 3.178 3.368 ns ­2.689 ­2.860 ­3.014 ns GCLK tS U 1.123 1.156 1.167 ns tH ­0.843 ­0.838 ­0.813 ns GCLK PLL tS U 2.969 3.178 3.368 ns tH Altera Corporation July 2007 2.969 tH 8 mA tS U ­2.689 ­2.860 ­3.014 ns 1­37 Cyclone III Device Handbook, Volume 2 Cyclone III Device Datasheet: DC and Switching Characteristics Table 1­48. EP3C5 Column I/O Pin Input Timing Parameters for Single-Ended I/O Standards (Part 2 of 6) IO Standard Current Strength Units GCLK tS U 1.123 1.156 1.167 ns ­0.843 ­0.838 ­0.813 ns tS U 2.969 3.178 3.368 ns ­2.689 ­2.860 ­3.014 ns GCLK tS U 1.123 1.156 1.167 ns tH ­0.843 ­0.838 ­0.813 ns tS U 2.969 3.178 3.368 ns tH 4 mA ­8 GCLK PLL 2.5V ­7 tH 16 mA ­6 tH 12 mA Parameter GCLK PLL 3.0-V LVCMOS Clock ­2.689 ­2.860 ­3.014 ns 1.066 1.111 1.135 ns ­0.786 ­0.794 ­0.782 ns GCLK PLL tS U 2.912 3.133 3.336 ns tH ­2.632 ­2.816 ­2.983 ns GCLK tS U 1.066 1.111 1.135 ns tH ­0.786 ­0.794 ­0.782 ns GCLK PLL tS U 2.912 3.133 3.336 ns tH ­2.632 ­2.816 ­2.983 ns GCLK tS U 1.066 1.111 1.135 ns tH 12 mA tS U tH 8 mA GCLK ­0.786 ­0.794 ­0.782 ns GCLK PLL ns ­2.983 ns GCLK tS U 1.066 1.111 1.135 ns ­0.786 ­0.794 ­0.782 ns tS U 2.912 3.133 3.336 ns tH ­2.632 ­2.816 ­2.983 ns GCLK tS U 1.001 1.072 1.122 ns tH ­0.723 ­0.756 ­0.768 ns GCLK PLL tS U 2.847 3.094 3.323 ns tH 4 mA 3.336 ­2.816 tH 2 mA 3.133 ­2.632 GCLK PLL 1.8V 2.912 tH 16 mA tS U ­2.569 ­2.778 ­2.969 ns 1.001 1.072 1.122 ns ­0.723 ­0.756 ­0.768 ns GCLK PLL tS U 2.847 3.094 3.323 ns tH ­2.569 ­2.778 ­2.969 ns GCLK tS U 1.001 1.072 1.122 ns tH ­0.723 ­0.756 ­0.768 ns GCLK PLL tS U 2.847 3.094 3.323 ns tH ­2.569 ­2.778 ­2.969 ns GCLK tS U 1.001 1.072 1.122 ns tH 8 mA tS U tH 6 mA GCLK ­0.723 ­0.756 ­0.768 ns GCLK PLL 2.847 3.094 3.323 ns tH 1­38 Cyclone III Device Handbook, Volume 2 tS U ­2.569 ­2.778 ­2.969 ns Altera Corporation July 2007 Typical Design Performance Table 1­48. EP3C5 Column I/O Pin Input Timing Parameters for Single-Ended I/O Standards (Part 3 of 6) IO Standard Current Strength ­8 Units GCLK tS U 1.001 1.072 1.122 ns ­0.723 ­0.756 ­0.768 ns tS U 2.847 3.094 3.323 ns ­2.569 ­2.778 ­2.969 ns GCLK tS U 1.001 1.072 1.122 ns tH ­0.723 ­0.756 ­0.768 ns GCLK PLL tS U 2.847 3.094 3.323 ns tH 16 mA ­7 tH 12 mA ­6 tH 10 mA Parameter GCLK PLL 1.8V Clock ­2.569 ­2.778 ­2.969 ns 1.072 1.122 ns ­0.756 ­0.768 ns tS U 2.847 3.094 3.323 ns tH ­2.569 ­2.778 ­2.969 ns GCLK tS U 1.070 1.164 1.239 ns tH ­0.790 ­0.846 ­0.883 ns GCLK PLL tS U 2.916 3.186 3.440 ns tH ­2.636 ­2.868 ­3.084 ns GCLK tS U 1.070 1.164 1.239 ns tH 4 mA 1.001 ­0.723 GCLK PLL 2 mA tS U tH 1.5V GCLK ­0.790 ­0.846 ­0.883 ns GCLK PLL 3.440 ns ­2.868 ­3.084 ns GCLK tS U 1.070 1.164 1.239 ns tH ­0.790 ­0.846 ­0.883 ns tS U 2.916 3.186 3.440 ns tH ­2.636 ­2.868 ­3.084 ns GCLK tS U 1.070 1.164 1.239 ns tH ­0.790 ­0.846 ­0.883 ns GCLK PLL tS U 2.916 3.186 3.440 ns tH 10 mA 3.186 ­2.636 GCLK PLL 8 mA 2.916 tH 6 mA tS U ­2.636 ­2.868 ­3.084 ns 1.070 1.164 1.239 ns ­0.790 ­0.846 ­0.883 ns GCLK PLL tS U 2.916 3.186 3.440 ns tH ­2.636 ­2.868 ­3.084 ns GCLK tS U 1.070 1.164 1.239 ns tH ­0.790 ­0.846 ­0.883 ns GCLK PLL tS U 2.916 3.186 3.440 ns tH ­2.636 ­2.868 ­3.084 ns GCLK tS U 1.070 1.164 1.239 ns tH 16 mA tS U tH 12 mA GCLK ­0.790 ­0.846 ­0.883 ns GCLK PLL 2.916 3.186 3.440 ns tH Altera Corporation July 2007 tS U ­2.636 ­2.868 ­3.084 ns 1­39 Cyclone III Device Handbook, Volume 2 Cyclone III Device Datasheet: DC and Switching Characteristics Table 1­48. EP3C5 Column I/O Pin Input Timing Parameters for Single-Ended I/O Standards (Part 4 of 6) IO Standard Current Strength ­8 Units GCLK tS U 1.222 1.344 1.445 ns ­0.940 ­1.022 ­1.085 ns tS U 3.068 3.366 3.646 ns ­2.786 ­3.044 ­3.286 ns GCLK tS U 1.222 1.344 1.445 ns tH ­0.940 ­1.022 ­1.085 ns GCLK PLL tS U 3.068 3.366 3.646 ns tH 6 mA ­7 tH 4 mA ­6 tH 2 mA Parameter GCLK PLL 1.2V Clock ­2.786 ­3.044 ­3.286 ns 1.222 1.344 1.445 ns ­0.940 ­1.022 ­1.085 ns GCLK PLL tS U 3.068 3.366 3.646 ns tH ­2.786 ­3.044 ­3.286 ns GCLK tS U 1.222 1.344 1.445 ns tH ­0.940 ­1.022 ­1.085 ns GCLK PLL tS U 3.068 3.366 3.646 ns tH ­2.786 ­3.044 ­3.286 ns GCLK tS U 1.222 1.344 1.445 ns tH 10 mA tS U tH 8 mA GCLK ­0.940 ­1.022 ­1.085 ns GCLK PLL ns ­3.286 ns GCLK tS U 1.222 1.344 1.445 ns ­0.940 ­1.022 ­1.085 ns tS U 3.068 3.366 3.646 ns tH ­2.786 ­3.044 ­3.286 ns GCLK tS U 1.057 1.133 1.188 ns tH ­0.777 ­0.816 ­0.833 ns GCLK PLL tS U 2.901 3.151 3.385 ns tH 12 mA 3.646 ­3.044 tH 8 mA 3.366 ­2.786 GCLK PLL SSTL-2 Class I 3.068 tH 12 mA tS U ­2.621 ­2.834 ­3.030 ns 1.057 1.133 1.188 ns ­0.777 ­0.816 ­0.833 ns GCLK PLL tS U 2.901 3.151 3.385 ns tH ­2.621 ­2.834 ­3.030 ns GCLK tS U 1.057 1.133 1.188 ns tH ­0.777 ­0.816 ­0.833 ns tS U 2.901 3.151 3.385 ns tH 16 mA tS U tH SSTL-2 Class II GCLK ­2.621 ­2.834 ­3.030 ns GCLK PLL 1­40 Cyclone III Device Handbook, Volume 2 Altera Corporation July 2007 Typical Design Performance Table 1­48. EP3C5 Column I/O Pin Input Timing Parameters for Single-Ended I/O Standards (Part 5 of 6) IO Standard Current Strength ­8 Units GCLK tS U 1.118 1.222 1.303 ns ­0.838 ­0.903 ­0.946 ns tS U 2.962 3.240 3.500 ns ­2.682