CH7009B CH7009 AN-38 CCIR-656 AN-41 FSCI31 FSCI23 FSCI15 FSCI30 FSCI22 FSCI14 - Datasheet Archive

 

Chrontel CHRONTEL CHRONTEL CHRONTEL CH7009 DVI / TV Output Device 1. FEATURES 2. GENERAL DESCRIPTION · · ·

 

CH7009B CH7009B Chrontel CHRONTEL CHRONTEL CHRONTEL CH7009 CH7009 DVI / TV Output Device 1. FEATURES 2. GENERAL DESCRIPTION · · · · The CH7009 CH7009 is a display controller device which accepts a digital graphics input signal, and encodes and transmits data through a DVI (DFP can also be supported) or TV output (analog composite, s-video or RGB). The device accepts data over one 12-bit wide variable voltage data port which supports five different data formats including RGB and YCrCb. · · · · · · · · · · · · · DVI Transmitter up to 165M pixels/second DVI low jitter PLL DVI hot plug detection TV output supporting graphics resolutions up to 1024 x768 pixels MacrovisionTM 7.1.L1 copy protection support Programmable digital interface supports RGB and YCrCb True scale rendering engine supports underscan in all TV output resolutions Enhanced text sharpness and adaptive flicker removal with up to 7 lines of filtering Support for all NTSC and PAL formats Provides CVBS, S-Video and SCART (RGB) outputs TV connection detection Programmable power management 10-bit video DAC outputs Fully programmable through serial port Complete Windows and DOS driver support Low voltage interface support to graphics device Offered in a 64-pin LQFP package XCLK, XCLK* The TV-Out processor performs non-interlace to interlace conversion with scaling and flicker filters, and encodes the data into any of the NTSC or PAL video standards. The scaling and flicker filter is adaptive and programmable to enable superior text display. Eight graphics resolutions are supported up to 1024 by 768 with full vertical and horizontal underscan capability in all modes. A high accuracy low jitter phase locked loop is integrated to create outstanding video quality. Support is provided for MacrovisionTM and RGB bypass mode which enables driving a VGA CRT with the input data. DVI PLL Clock Driver 2 2 12 Data Latch, Demux 3 24 3 DVI Encode DVI Serialize H, V, DE Latch D[11:0] H,V,DE VREF The DVI processor includes a low jitter PLL for generation of the high frequency serialized clock, and all circuitry required to encode, serialize and transmit data. The CH7009 CH7009 comes in versions able to drive a DVI display at a pixel rate of up to 165MHz, supporting UXGA resolution displays. No scaling of input data is performed on the data output to the DVI device. XI/FIN,XO P-OUT/TLDET* DVI Driver 2 2 2 24 2 Serial port Control 3 2 PLL3 Scaling Scan Conv Flicker Filt TV Encode TDC0,TDC0* TDC1,TDC1* TDC2,TDC2* VSWING HPDET GPIO[1:0] AS SPC SPD RESET* BCO C/H SYNC ISET Timing 3 24 TLC,TLC* Four 10-bit DAC's CVBS(DAC3) Y/G(DAC1) C/R(DAC2) CVBS/B(DAC0) 24 Figure 1. Functional Block Diagram 201-0000-035 Rev 3.4, 3/17/2010 1 CHRONTEL CH7009B CH7009B 3. PIN DESCRIPTIONS DGND D[0] D[1] D[2] D[3] D[4] D[5] XCL XCLK* D[6] D[7] D[8] D[9] D[10] D[11] DDVD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 3.1 Package Diagram DVDD 1 48 C / H SYNC DE 2 47 BCO / VSYNC VREF 3 46 P-OUT/TLDET* H 4 45 DVDDV V 5 44 VAVDD DGND 6 43 XO GPIO[1] / TLDET* 7 42 XI / FIN GPIO[0] 8 41 AGND HPDET 9 40 GND Chrontel CH7009 CH7009 AS 10 39 CVBS / B DGND 11 38 C/R 26 27 28 29 30 31 32 TGND TDC2* TDC2 TVDD TLC TLC* TGND VDD 25 33 TDC1 16 24 AGND TDC1* GND 23 34 TVDD 15 22 SPC TDC0 ISET 21 35 TDC0* 14 TGND SPD 20 CVBS 19 36 VSWING 13 18 Y/C AVDD 37 17 12 AGND DVDD RESET* Figure 2. 64-Pin LQFP 2 201-0000-035 Rev 3.4, 3/17/2010 CHRONTEL CH7009B CH7009B 3.2 Pin Description Table 1. Pin Description 64-Pin # Pins Type LQFP Symbol Description 2 DE Data Enable 1 In This pin accepts a data enable signal which is high when active video data is input to the device, and low all other times. The levels are 0 to DVDDV, and the VREF signal is used as the threshold level. This input is used by the DVI. The TV-Out function uses H and V sync signals as reference to active video. 3 1 In VREF Reference Voltage Input The VREF pin inputs a reference voltage of DVDDV / 2. The signal is derived externally through a resistor divider and decoupling capacitor, and will be used as a reference level for data, sync, data enable and clock inputs. 4 1 In/Out H Horizontal Sync Input / Output When the SYO bit is low, this pin accepts a horizontal sync input for use with the input data. The amplitude will be 0 to DVDDV, and the VREF signal is used as the threshold level. When the SYO bit is high, the device will output a horizontal sync pulse, 64 pixels wide. The output is driven from the DVDD. This output is only for use with the TV-Out function. 5 1 In/Out V Vertical Sync Input / Output When the SYO bit is low, this pin accepts a vertical sync input for use with the input data. The amplitude will be 0 to DVDDV, and the VREF signal is used as the threshold level. When the SYO bit is high, the device will output a vertical sync pulse one line wide. The output is driven from the DVDD supply. This output is only for use with the TV-Out function. 7 2 In/Out GPIO[1] / TLDET* General Purpose Input - Output[1] / DVI Detect Output (Open drain or internal weak pull-up) This pin provides a general purpose I/O controlled via the serial port. When the GPIO[1] pin is configured as an output, this pin can be used to output the DVI detect signal (pulls low when a termination change has been detected on the HPDET input). This is an open drain output. The output is released through serial port control. 8 2 In/Out GPIO[0] General Purpose Input - Output[0] (Open drain or internal weak pull-up) This pin provides a general purpose I/O controlled via the serial port. This allows an external switch to be used to select NTSC or PAL at power-up. 9 1 In HPDET Hot Plug Detect (internal pull-down) This input pin determines whether the DVI is connected to a DVI monitor. When terminated, the monitor is required to apply a voltage greater than 2.4 volts. Changes on the status of this pin will be relayed to the graphics controller via the P-OUT/TLDET* or GPIO[1]/TLDET* pin pulling low. When the HPDET is pulled low, the DVI output driver will be shut down. 10 1 In AS Address Select (Internal pull-up) This pin determines the serial port address of the device (1,1,1,0,1,AS*,AS). 201-0000-035 Rev 3.4, 3/17/2010 3 CHRONTEL CH7009B CH7009B Table 1. Pin Description (continued) 64-Pin # Pins Type Symbol LQFP Description 13 Reset * Input (Internal pull-up) 1 In RESET* When this pin is low, the device is held in the power-on reset condition. When this pin is high, reset is controlled through the serial port register. 14 1 In/Out SPD Serial Port Data Input / Output This pin functions as the serial port data pin of the serial port interface, and uses the DVDD supply. 15 1 In SPC 19 1 In VSWING Serial Port Clock Input This pin functions as the clock pin of the serial port interface, and uses the DVDD supply. DVI Swing Control This pin sets the swing level of the DVI outputs. A 2.4K ohm resistor should be connected between this pin and TGND using short and wide traces. 22, 21 35 2 1 Out Out In TDC1, DVI Data Channel 1 Outputs These pins provide the DVI differential outputs for data channel 1 (green). TDC2, DVI Data Channel 2 Outputs These pins provide the DVI differential outputs for data channel 2 (red). TLC, DVI Clock Outputs TLC* 30, 31 2 These pins provide the DVI differential outputs for data channel 0 (blue). TDC2* 28, 27 Out DVI Data Channel 0 Outputs TDC1* 2 Out TDC0, TDC0* 25, 24 2 These pins provide the differential clock output for the DVI interface corresponding to data on the TDC[0:2] outputs. ISET Current Set Resistor Input This pin sets the DAC current. A 140 ohm resistor should be connected between this pin and GND (DAC ground) using short and wide traces. 36 1 Out CVBS Composite Video This pin outputs a composite video signal capable of driving a 75 ohm doubly terminated load. 37 1 Out Y/G Luma / Green Output This pin outputs a selectable video signal. The output is designed to drive a 75 ohm doubly terminated load. The output can be selected to be s-video luminance or green. 38 1 Out C/R Chroma / Red Output This pin outputs a selectable video signal. The output is designed to drive a 75 ohm doubly terminated load. The output can be selected to be s-video chrominance or red. 39 1 Out CVBS/B Composite Video / Blue Output This pin outputs a selectable video signal. The output is designed to drive a 75 ohm doubly terminated load. The output can be selected to be composite video or blue. 42 1 In XI / FIN Crystal Input / External Reference Input A parallel resonance 14.31818MHz crystal (+ 20 ppm) should be attached between this pin and XO. However, an external clock can drive the XI/FIN input. 4 201-0000-035 Rev 3.4, 3/17/2010 CHRONTEL CH7009B CH7009B Table 1. Pin Description (continued) 64-Pin # Pins Type Symbol LQFP Description 43 Crystal Output 1 In XO A parallel resonance 14.31818MHz crystal (+ 20 ppm) should be attached between this pin and XI / FIN. However, if an external CMOS clock is attached to XI/FIN, XO should be left open. 46 1 Out P-OUT / Pixel Clock Output / DVI Detect Output TLDET* When the CH7009 CH7009 is operating as a VGA to TV encoder in master clock mode, this pin provides a pixel clock signal to the VGA controller which is used as a reference frequency. The output is selectable between 1X or 2X of the pixel clock frequency. The output driver is driven from the DVDDV supply. This output has a programmable tri-state. The capacitive loading on this pin should be kept to a minimum. When the CH7009 CH7009 is operating as a DVI transmitter, this pin provides an open drain output which pulls low when a termination change has been detected on the HPDET input. The output is released through serial port control. 47 1 Out BCO/ Buffered Clock Output / Vertical Sync Output V SYNC This output pin provides a buffered clock output, driven by the DVDD supply. The output clock can be selected using the BCO register. This pin can also be used as VSYNC output. 48 1 Out C/H SYNC Composite / Horizontal Sync Output This pin can be selected to output a TV composite sync, TV horizontal sync, or a buffered version of the VGA horizontal sync. The output is driven from the DVDD supply. 50 ­ 55, 12 In / Out D[11] - D[0] Data[11] through Data[0] Inputs 58 ­ 63 57, 56 2 In XCLK, XCLK* 1, 12, 49 6, 11, 64 45 23, 29 20, 26, 32 18, 44 16, 17, 41 33 34, 40 3 3 1 2 3 2 3 1 2 201-0000-035 Power Power Power Power Power Power Power Power Power DVDD DGND DVDDV TVDD TGND AVDD AGND VDD GND Rev 3.4, 3/17/2010 These pins accept the 12 data inputs from a digital video port of a graphics controller. The levels are 0 to DVDDV, and the VREF signal is used as the threshold level. External Clock Inputs These inputs form a differential clock signal input to the CH7009 CH7009 for use with the H, V, DE and D[11:0] data. If differential clocks are not available, the XCLK* input should be connected to VREF. The output clocks from this pad cell are able to have their polarities reversed under the control of the MCP bit (in register 1Ch). Digital Supply Voltage (3.3V-3.6V) Digital Ground I/O Supply Voltage (3.3V to 1.1V) DVI Transmitter Supply Voltage (3.3V-3.6V) DVI Transmitter Ground PLL Supply Voltage (3.3V-3.6V) PLL Ground DAC Supply Voltage (3.3V-3.6V) DAC Ground 5 CHRONTEL CH7009B CH7009B 4. MODES OF OPERATION The CH7009 CH7009 is capable of being operated as a single DVI output, or as a VGA to TV encoder. The two modes of operation cannot be used simultaneously. Descriptions of each of the operating modes, with a block diagram of the data flow within the device is shown below. 4.1 DVI Output In DVI Output mode, multiplexed input data, sync and clock signals are input to the CH7009 CH7009 from the graphics controller's digital output port. Data will be 2X multiplexed, and the clock inputs can be 1X or 2X times the pixel rate. Some examples of modes supported are shown in the table below, and a block diagram of the CH7009 CH7009 is shown on the following page. For the table below, clock frequencies for given modes were taken from VESA DISPLAY MONITOR TIMING SPECIFICATIONS if they were detailed there, not VESA TIMING DEFINITION FOR FLAT PANEL MONITORS. The device is not dependent upon this set of timing specifications. Any value of pixels/line, lines/frame and clock rate are acceptable, as long as the pixel rate remains below 165MHz. In the block diagram, all blocks are shown. Those blocks which are non-active are shown as shaded. The clock and data paths which are in use are highlighted. Although the block diagram does not show this path as being active, the data input can be selected to be output by the DACs as a VGA type output. For correct DVI operation, the input data format must be selected to be one of the RGB input formats. Table 2. DVI Output Graphics Resolution 720x400 640x400 640x480 720x4801 720x5762 800x600 1024x768 1280x720 1280x768 1280x1024 1366x768 1600x1200 1920x1080 1 These 2 6 Active Pixel Aspect Refresh Rate Aspect Ratio Ratio (Hz) 4:3 8:5 4:3 4:3 4:3 4:3 4:3 16:9 15:9 4:3 16:9 4:3 16:9 1.35:1.00 1:1 1:1 9:8 15:12 1:1 1:1 1:1 1:1 1:1 1:1 1:1 1:1