CH7002D CH7002 103/C 800X600 640X480 1N4001 CH7002B CH7002D-V - Datasheet Archive

 

Preliminary CHRONTEL Scalable VGA to NTSC/PAL Encoder Features General Description · Fully integrated solution for PC to

 

CH7002D CH7002D Preliminary CHRONTEL Scalable VGA to NTSC/PAL Encoder Features General Description · Fully integrated solution for PC to TV display Chrontel's CH7002 CH7002 VGA to NTSC/PAL encoder is a standalone integrated circuit which provides a PC 99 compliant solution for TV output. It accepts RGB analog inputs directly from VGA controllers and converts them directly into NTSC or PAL TV format, with simultaneous composite and S-Video outputs. · TrueScale TM rendering engine supports underscan operation for both 640x480 or 800x600 inputs · Advanced 3-line digital flicker filtering with programmable algorithm selections · Fully programmable through I2C port or hardware (pin-based) controls · Wide range of VGA software drivers for full synchronization and image positioning This circuit integrates a digital NTSC/PAL encoder with 8bit ADC and DAC interfaces, a 3-line vertical filter, and lowjitter phase-locked loop to create outstanding quality video. Through Chrontel's TrueScale TM rendering technology, the CH7002 CH7002 supports full vertical and horizontal underscan operation from either 640x480 or 800x600 input to either NTSC or PAL outputs. A high level of performance along with full programmability makes the CH7002 CH7002 ideal for system-level PC or Web browser solutions. All features are software programmable, through a standard I2C port, to enable fully integrated system solutions by using a TV as the primary display device. · Auto-detection of TV presence · Programmable power management features three power-down modes · Supports both NTSC and PAL (B, D, G, H, or I) TV formats onto both composite and S-Video · Triple 8-bit ADC inputs and triple 8-bit DAC outputs · On-chip reference generation and loop filter · Offered in 44-pin PLCC package PMODE LEF SC ADDR UP DOWN SD RIGHT Patent number 5,781,241 RSET I2C REGISTER & CONTROL BLOCK RSET LINE MEMORY R R Y Y LINE RENDERING ENGINE G G ADC COLOR U SPACE CONVERTER B B DAC V Y DAC CVBS DAC ADC C OSC CLKOUT DIGITAL U NTSC/PAL -SCALING -DEFLICKERING -SCAN CONVERSION ENCODER V & FILTER ADC SYSTEM CLOCK VREF VREF1 PLL TIMING & SYNC GENERATOR VREF2 XCLK H V XI XO Figure 1: Functional Block Diagram 201-0000-029 Rev 6.1, 8/2/99 1 AGND RED AGND GREEN AGND BLUE AVDD VREF1 AGND VREF2 AVDD 5 4 3 2 1 44 43 42 41 40 CH7002D CH7002D 6 CHRONTEL AVDD 7 39 AGND DVDD 8 38 PMODE UP 9 37 AVDD DGND 10 36 ADDR/FF0 DOWN 11 35 V LEFT 12 34 H RIGHT 13 33 DVDD DVDD 14 32 XCLK/SD3 CLKOUT 15 31 DGND DGND 16 30 SC/DM2 XI 17 29 SD/DM1 22 23 24 25 26 27 28 C CVBS Y VDD RSET AGND RESET/DM0 20 NC 21 19 NC GND 18 XO/FIN CHRONTEL CH7002 CH7002 Figure 2: 44-pin PLCC 2 201-0000-029 Rev6.1, 8/2/99 CHRONTEL CH7002D CH7002D Table 1. Pin Description 44-Pin PLCC Type Symbol Description 2, 4, 6, 27, 39,42 Power AGND Analog ground These pins provide the ground reference for the analog section of CH7002 CH7002, and MUST be connected to the system ground to prevent latchup. Refer to the Application Information section for information on proper supply decoupling. 1, 3, 5 In B, G, R VGA Inputs These pins should be terminated with 75 ohm resistors and isolated from switching digital signals and video output pins. Refer to the Application Information section for detailed technical guidance and alternative connection techniques. 7, 37, 40, 44 Power AVDD Analog Supply Voltage These pins supply the 5V power to the analog section of the CH7002 CH7002. For information on proper supply decoupling, refer to the Application Information section. 15 Out CLKOUT Clock Output This pin defaults to 14.31818 MHz upon power-up and remains active at all times (including power-down). 8, 14, 33 Power DVDD Digital Supply Voltage These pins supply the 5V power to the digital section of CH7002 CH7002. For information on proper supply decoupling, refer to the Application Information section. 10, 16, 31 Power DGND Digital Ground These pins provide the ground reference for the digital section of CH7002 CH7002, and MUST be connected to the system ground to prevent latchup. For information on proper supply decoupling, refer to the Application Information section. 17 In XI Crystal Input A parallel resonance 14.31818 MHz (± 50 ppm) crystal should be attached between XI and XO/FIN. However, if an external CMOS clock is attached to XO/FIN, XI should be connected to ground. 18 In XO/FIN Crystal Output or External Fref A 14.31818 MHz (± 50 ppm) crystal may be attached between XO/FIN and XI. An external CMOS compatible clock can be connected to XO/FIN as an alternative. 25 Power VDD 26 In RSET Reference Resistor A 324 resistor with short and wide traces should be attached between RSET and ground. No other connections should be made to this pin. 21 Power GND DAC Ground These pins provide the ground reference for CH7002 CH7002's internal DACs. For information on proper supply decoupling, refer to the Application Information section. 24 Out Y Luminance Output A 75 termination resistor with short traces should be attached between Y and ground for optimum performance. Use of additional filters is discussed in the Application Information section. 23 Out CVBS 201-0000-029 Rev 6.1, 8/2/99 DAC Power Supply These pins supply power to CH7002 CH7002's internal DACs. Refer to the Application Information section for information on proper supply decoupling. Composite Output A 75 termination resistor, with short traces, should be attached between CVBS and ground for optimum performance. Use of additional filters is discussed in the Application Information section. 3 CHRONTEL CH7002D CH7002D Table 1. Pin Description (continued) 44-Pin PLCC Symbol Description 22 Out C Chrominance Output A 75 termination resistor, with short traces, should be attached between C and ground for optimum performance. Use of additional filters is discussed in the Application Information section. 9, 11, 12, 13 In UP, DOWN, LEFT, RIGHT Position Controls (low-to-high transition, internal pull-up) UP, DOWN, LEFT, and RIGHT, allows the screen display position to be moved incrementally, in each respective direction, for every toggle of this pin to ground. An internal schmitt trigger minimizes switch bounce problems. These pins may be connected directly to the power supply or ground. 28 In RESET*/D M0 Reset (active low) /Display Mode Select [0] (internal pull-up) The function of this dual use pin is determined by the state of the PMODE pin. When the PMODE pin is kept high (default), the RESET*/DM0 pin becomes RESET*. In this mode, when RESET* is held high (default), the chip is in operating state, and when RESET* is pulled low, the entire chip is reset and initialized to its power-up state. When the PMODE pin is pulled low, this pin becomes DM0, which combined with DM1 and DM2, provides for pin-programming of the 7002 display mode. The pin-programming is "mux-ed" with the Display Mode register selections. All applicable modes are described in Application Information and Registers and Programming sections. 29 In/Out SD/DM1 Serial Data/Display Mode Select [1] (internal pull-up) The function of this dual use pin is determined by the state of the PMODE pin. When the PMODE pin is kept high (default), this pin becomes SD, the serial data pin of the I2C interface port. When the PMODE pin is pulled low, this pin becomes DM1, which combined with DM0 and DM2, provides for pin-programming of the 7002 display mode. The pin-programming is "mux-ed" with the Display Mode register selections. All applicable modes are described under the programming section. 30 In SC/DM2 Serial Clock/Display Mode Select [2] (internal pull-up) The function of this dual use pin is determined by the state of the PMODE pin. When the PMODE pin is kept high (default), this pin becomes SC, the serial clock pin of the I2C interface port. When the PMODE pin is pulled low, this pin becomes DM2, which combined with DM0 and DM1, provides for pin-programming of the 7002 display mode. The pin-programming is "mux-ed" with the Display Mode register selections. All applicable modes are described in the Registers and Programming and Application Information sections. 32 In XCLK/SD3 External Clock/Sample Delay (bit 3) (internal pull-up) The function of this dual use pin is determined by the state of the PMODE pin. When the PMODE pin is kept high (default), this pin becomes XCLK or external clock, which accepts an external pixel clock input. When the PMODE pin is pulled low, this pin becomes SD3 or Sample Delay, the function corresponding to bit 3 of the Sample Delay register, which provides the following selection: SD3 Sample Delay Selected 1 20 ns nominal delay 0 0 delay (default) This pin-programming is "mux-ed" with the Sample Delay register (bit 3). All related modes are described in the Registers and Programming section. 35 In V Vertical Sync Input This pin accepts the vertical sync output from the VGA card. The capacitive loading on this pin should be kept to a minimum. 34 4 Type In H Horizontal Sync Input This pin accepts the horizontal sync output from the VGA card. The capacitive loading on this pin should be kept to a minimum. Refer to the Application Information section for PC Board layout considerations. 201-0000-029 Rev6.1, 8/2/99 CHRONTEL CH7002D CH7002D Table 1. Pin Description (continued) 44-Pin PLCC Type Symbol 36 In ADDR/FF0 Description I2C Address Select/Flicker Filter (bit 0)(internal pull-up) The function of this dual use pin is determined by the state of the PMODE pin. When the PMODE pin is kept high (default), this pin becomes ADDR or I2C Address Select, which corresponds to bits 1 and 0 of the I2C device address (see the I2C Control Port Operation section for details), creating an address selection as follows: ADDR I2C Address Selected 1 1110101 = 75H = 117 0 1110110 = 76H = 118 When the PMODE pin is pulled low, this pin becomes FF0 or Flicker Filter select, the function of which corresponds to bit 0 of the Flicker Filter register, which selects between the following: FF0 Flicker Filter Mode 0 0:1:0 No filtering 1 1:2:1 Moderate filtering (default) This pin-programming is "mux-ed" with the Flicker Filter register (bit 0). All related modes are described under the Registers and Programming section. 38 In PMODE Programming Mode (internal pull-up) The PMODE pin selects between the two alternative programming modes for the CH7002 CH7002, which in turn alters the function of five additional pins (RESET/DM0, SD/DM1, SC/DM2, XCLK/SD3, and ADDR/FF0). When PMODE is kept high (default), the chip is placed in I2C programming mode. When PMODE is pulled low, the chip is placed in direct pin programming mode. 41 In VREF2 Internal Voltage Reference VREF2 provides a typical 2.5V reference that is used as an internal bias to the ADCs. A 0.1 µF decoupling capacitor should be connected between VREF2 and ground. 43 In VREF1 ADC Voltage Reference Input / Output VREF1 provides a typical 1.235V reference that sets the RGB input full scale at 0.75V. A 0.1 µF decoupling capacitor should be connected between VREF1 and ground. VREF1 may also be forced by external reference, where (VFS is the full scale input voltage): VFS ~ VREF1 * 0.75/1.235 19, 20 NC NC No Connect Note: For complete information concerning external signal connections, terminations, and system design considerations, refer to the Application Information section. 201-0000-029 Rev 6.1, 8/2/99 5 CHRONTEL CH7002D CH7002D Functional Description The CH7002 CH7002 is a fully integrated system solution for converting analog RGB and synchronization signals from a standard VGA source into high-quality NTSC or PAL video signals. This solution involves both hardware and software elements, which work together, to produce an optimum TV screen image based on the original computer generated pixel data. All essential circuitry for this conversion are integrated on chip. On-chip circuitry includes: memory, memory control, scaling, PLL, ADC, DAC, filters, and a NTSC/PAL encoder. All internal signal processing, including NTSC/PAL encoding, is performed using digital techniques, to ensure that the high-quality video signals are not affected by drift issues associated with analog components. No additional adjustment is required during manufacturing. CH7002 CH7002 is ideal for stand-alone VGA to NTSC/PAL applications, where a minimum of discrete support components (passive components, parallel resonance 14.31818 MHz crystal) are required for full operation. The CH7002 CH7002 is designed to provide an ideal solution for computer motherboards, add-on graphics cards, TV-sets, and scan converter boards. Architectural Overview The CH7002 CH7002 is a complete TV output subsystem, using both hardware and software elements, to produce an image on TV, that is virtually identical to the image that would be displayed on a monitor. Creating a compatible TV output from a VGA input is a relatively straightforward process. This process includes a standard conversion from RGB to YUV color space, converting from a non-interlaced to an interlaced frame sequence, then encoding the pixel stream into NTSC or PAL compliant format. However, creating an optimum computer-generated image on a TV screen involves a highly sophisticated process of scaling, deflickering, and filtering. This results in a compatible TV output that displays a sharp and stable image of the right size, with minimal artifacts from the conversion process. As a key part of the overall system solution, the CH7002 CH7002 software establishes the correct framework for the VGA input signal to enable this process. Once the display is set to a supported resolution (either 640x480 or 800x600), the CH7002 CH7002 software may be invoked to establish the appropriate TV output display. The software then programs the various timing parameters of the VGA controller to create an output signal that will be compatible with the chosen resolution, operating mode, and TV format. Adjustments performed in software include pixel clock rates, total pixels per line, and total lines per frame. By performing these adjustments in software, the CH7002 CH7002 can render a superior TV image, without the added cost of a full frame buffer memory, normally used to implement features such as scaling and full synchronization. Without this added system software, TV output solutions can only guarantee compatible operation in VGA standard mode 12 (640x480x16 color, 60 Hz). The CH7002 CH7002 hardware accepts direct VGA outputs (analog RGB inputs), which are digitized on a pixel-by-pixel basis by three 8-bit video A/D converters. The digitized RGB inputs are then color space converted into YUV in 42-2 format (encoded into luminance (Y) and color-difference (U,V) signals) and stored in a line buffer memory. The stored pixels are fed into a block where scan-rate conversion, underscan scaling, and 3-line vertical flicker filtering are performed. The scan-rate converter transforms the VGA horizontal scan-rate to either NTSC or PAL scan-rates; the vertical flicker filter eliminates flicker at the output, while the underscan scaling reduces the size of the displayed image to fit onto a TV screen. The resulting YUV signals are filtered through digital filters to minimize aliasing problems. The digital encoder receives the filtered signals and transforms the signals into composite and S-Video outputs, which are converted by the three 8-bit DACs into analog outputs. 6 201-0000-029 Rev6.1, 8/2/99 CHRONTEL CH7002D CH7002D Clock Generation and Video Timing All clock signals of the CH7002 CH7002 are generated from the VGA synchronization inputs by a low-jitter, PLL circuit. The VGA input and sync timing are illustrated in Figures 3, 5 and 6. The VGA pixel clock is generated internally, using the VGA horizontal sync signal, and is used for sampling the RGB inputs pixel-by-pixel, which aids in preventing aliasing artifacts. All synchronization and color burst envelope pulses are internally generated, using only the timing signals provided by the VGA synchronization inputs. In situations where the CH7002 CH7002 is placed next to a graphics controller (e.g. motherboard or add-in cards), the graphics pixel clock can be provided to CH7002 CH7002, directly from the graphics controller via pin XCLK. This arrangement minimizes phase jitter of the system clock used in the encoder. See the sections on Application Information and Registers and Programming for detailed information on how to connect and enable this function. 31.78 µs H 25.42 µs 3.81 µs R,G,B DATA ACTIVE VIDEO 1.91 µs 0.64 µs Note: The timing diagram shown is for 640 x 480, 60 Hz VGA mode Figure 3: Typical VGA Input Timing 31.78 µs H 63.56 µs V* (ACTIVE LOW) Figure 4: VGA Horizontal and Vertical Sync Input Timing Note: The values shown in Figures 4 and 5 represent typical timing parameters for VGA controllers operating in 640x480 resolution at 60 Hz, with the CH7002 CH7002 in overscan mode. Other resolutions and display modes have different timing requirements. EXT PCLK HSYNC and VSYNC t1 EXT PCLK HSYNC and V VSYNC SYNC t2 Figure 5: External Clock Input Timing 201-0000-029 Rev 6.1, 8/2/99 7 CHRONTEL CH7002D CH7002D Color Burst Generation* The CH7002 CH7002 employs a proprietary technique for generating the color sub-carrier frequency. This method allows the sub-carrier frequency to be accurately generated from a 14.31818 MHz crystal oscillator, leaving the accuracy of the sub-carrier frequency independent of the sampling rate. As a result, the CH7002 CH7002 is compatible with any VGA chip, since the CH7002 CH7002 sub-carrier frequency is not dependent on the pixel rates of VGA manufacturers. This feature is a significant benefit, since even a ± 0.01% sub-carrier frequency variation may be enough to cause some television monitors to lose color lock. Internal Voltage Reference The on-chip generated ADC voltage references are brought out to pins VREF1 and VREF2 for decoupling purposes. VREF1 and VREF2 should each have a 0.1 µF decoupling capacitor between each pin and ground. VREF2 provides a typical 2.5V reference used for setting the internal bias to the ADCs. VREF1 provides a typical 1.235V reference used for setting the RGB input full scale at 0.75V. VREF1 can be forced by an external voltage reference to accommodate different RGB input ranges. An additional on-chip bandgap circuit is used, in the DAC, to generate a reference voltage, which in conjunction with a reference resistor at pin RSET, sets the output ranges of the DACs. For each DAC, the current output per LSB step is determined by the following equation: ILSB = V(RSET)/RSET * 1/24 = 1.235/324 * 1/24 = 159 uA (nominal) The value of RSET can be adjusted to achieve a desired output signal level. A valid range for RSET is any value at or over 300 ohms. Operating Modes The CH7002 CH7002 is designed to accept certain limited input resolutions, primarily 640x480 and 800x600, from a VGA type graphics controller. The CH7002 CH7002 is also designed to support both NTSC and PAL output formats, with scaling to provide either an overscanned or underscanned image, when displayed on a TV. This combination of input resolution and output formatting results in a matrix of operating modes which are listed below, and are described in detail in Table 2. Note that all of these modes may be set either by I2C programming or by direct pin programming: · · · · 8 Modes 2 and 3 support 640x480 into a NTSC format in overscan and underscan forms respectively. Modes 1 and 4 support 640x480 into a PAL format in underscan and overscan forms respectively. Note that Mode 1 is the recommended operating mode for this resolution because it provides a higher overall quality image. Modes 0 and 5 support 800x600 into a PAL format in underscan and overscan forms respectively. Mode 6 supports 800x600 into a NTSC format in an underscan form. 201-0000-029 Rev6.1, 8/2/99 CHRONTEL CH7002D CH7002D Operating Modes (Continued) Table 2. CH7002 CH7002 Operating Modes PAL OUT 800x600 IN PAL OUT 640x480 IN Underscan NTSC 640x480 IN Overscan NTSC OUT 640x480 IN Underscan PAL OUT 640x480 IN Overscan PAL OUT 800x600 IN Overscan NTSC OUT 800x600 IN Underscan Mode 0 1 2 3 4 5 6 Pixel Clock 35.400 25.000 25.175 28.196 25.000 29.500 43.636 Scale Factor 5/6 1/1 1/1 7/8 1/1 1/1 3/4 Total VGA Lines 750 625 525 600 625 625 700 Active VGA Lines 600 480 480 480 480 600 600 Fvert VGA (Hz) 50.0 50.00 59.94 59.94 50.00 50.00 59.94 Fhor VGA (KHz) 37.5 31.250 31.469 35.964 31.250 31.250 41.958 Total TV Lines 625 625 525 525 625 625 525 Active TV Lines 500 480 480 420 480 600 450 Fvert TV (Hz) 50.00 50.00 59.94 59.94 50.00 50.00 59.94 Fhor TV (Hz) 15625.0 15625.0 15734.3 15734.3 15625.0 15625.0 15734.3 Name Overscan/Underscan The inclusion of both overscan and underscan forms of output display have been created to enable optimal use of the CH7002 CH7002 for different application needs. In general, underscan provides an image that is entirely viewable on screen. It should be used as the default for most applications (e.g. viewing text screens, operating games, running productivity applications, working within Windows). Overscan provides an image that bleeds past the edges of the TV screen, exactly like normal television programs and movies appear on TV. It is only recommended for viewing movies or video clips coming from the computer. Anti-Flicker Filter The CH7002 CH7002 integrates a 3-line vertical filter circuit to help eliminate the flicker associated with interlaced displays. When operating in underscan mode, this flicker circuit provides a adaptive filter algorithm for implementing flicker reduction based on an approximate 1:2:1 weighting sequence. When operating in overscan mode, it provides four anti-flicker filter modes as shown in Table 3. These modes are fully selectable, via I2C, and a subset is selectable (either 0:1:0 filtering or 1:2:1 filtering) when using direct pin programming mode. Table 3. Anti-Flicker Filter Modes FF0 Filter Modes 0 0 0:1:0 averaging (no filtering) 0 1 1:3:1 averaging 1 0 1:2:1 averaging 1 9 FF1 1 1:1:1 averaging *Patent number 5,874,846 201-0000-029 Rev6.1, 8/2/99 CHRONTEL CH7002D CH7002D Power Management The CH7002 CH7002 supports four operating states (including Normal [On], Power Down, S-Video Off, and Composite Off) to provide optimal power consumption for the application involved. Using the programmable power down modes accessed over the I2C port, the CH7002 CH7002 may be placed in either Normal state, or any of the four power managed states listed below (see the Miscellaneous Control Register under the Registers and Programming section). To support power management, a TV sensing function (see Connection Detect Register) is provided, which identifies whether a TV is connected to S-Video or Composite, or neither. This sensing function can then be used to enter into the appropriate operating state (e.g., if TV is sensed only on Composite, the S-Video Off mode could be set by software). Power State Functional Description Normal (On):I In the normal operating state, all functions and pins are active Power Down:I In the complete power-down state, most pins and circuitry are disabled.The CLKOUT pin, however, will continue to provide 14.318 Mhz out. This places the CH7002 CH7002 in its lowest power consumption mode Composite Off In Composite-off state, power is shut off to the unused DAC associated with CVBS output, thereby reducing power by approximately 10% S-Video Off Power is shut off to the unused DAC associated with CVBS output When using direct pin-programming mode for the CH7002 CH7002, only Normal and Power Down states are supported as selected by the Display Mode inputs. When inputs DM[2:0] are set to a 111 state, the CH7002 CH7002 is placed in Power Down state. The CH7002 CH7002 operates in Normal mode when the Display Mode settings are set to any valid state (where DM[2:0] is between 000 and 110). Luminance Filter Options The CH7002 CH7002 contains a set of luminance filters to provide a controllable bandwidth output on both composite and SVideo outputs. The response of the luminance filters are shown in the graphs in Figures 7 and 8. The horizontal axis is frequency in Mhz, and the vertical axis is gain in dBs. The possible S-Video MHz responses are: Y_SV0: A high frequency response, selected by setting YC-HI to 1 in the Y-filter register. Y_SV1: A lower frequency response, selected by setting YC-HI to 0 in the Y-filter register. Y_SV2: A lower frequency response, with peaking enabled, which gives improved transient response, with matching pre-shoot and overshoot of 6%. This is selected by setting YC-HI to 0 and YPEAKD to 0 in the Y-filter register. Note that peaking can only be enabled in the lower frequency response mode. The possible CVBS (composite) responses are: Y_CV0: A high frequency response, selected by setting YCV-HI to 1 in the Y-filter register. Y_CV1: A lower frequency response, selected by setting YCV-HI to 0 in the Y-filter register. This setting will result in a reduced amount of cross-luminance artifacts. 10 201-0000-029 Rev6.1, 8/2/99 CHRONTEL CH7002D CH7002D 0 -1 -2 -3 -4 dB Y_SV0 Y_SV1 -5 -6 -7 -8 -9 -10 0 Y_SV2 Y_CVO Y_CV1 1 2 3 4 5 6 Freq (MHz) Figure 6: Luminance Frequency Response - Detailed View 0 Y_SV0 -10 Y_SV1 -20 Y_SV2 -30 Y_CVO dB Y_CV1 -40 0 1 2 3 4 5 6 7 8 9 10 11 12 Freq (MHz) Figure 7: Luminance Frequency Response - Full View Notes: 1 The curves shown are valid for operating modes 2 and 6. Mode 0 frequency values are 20% higher, mode 1 and 3 frequency values are 12% higher, and mode 4 frequency values are 1% lower, due to changes in clock frequencies. 2 The Y_SV1 and Y_CV0 responses are identical; therefore the curves lie on top of each other. 201-0000-029 Rev 6.1, 8/2/99 11 CHRONTEL CH7002D CH7002D NTSC and PAL Operation Composite and S-Video outputs are supported in either NTSC or PAL format. The general parameters used to characterize these outputs are listed in Table 4 and shown in Figure 8. (See Figures 9 through 16 for illustrations of composite and S-Video output waveforms.) Table 4. NTSC/PAL Composite Output Timing Parameters (in µS) Symbol Level (mV) Description Duration (uS) NTSC PAL NTSC PAL A Front Porch 310 310 1.49 - 1.52 1.50 - 1.78 B Horizontal Sync 24 24 4.69 - 4.72 4.43 - 4.73 C Breezeway 310 310 0.60 0.57 - 0.60 D Color Burst 310 310 2.48 - 2.50 2.33 - 2.52 E Back Porch 310 310 1.60 1.50 - 1.60 F Black 363 310 0.92 - 3.64 0.00 - 4.24 G Active Video 363-1030 310-977 45.40 - 50.84 45.20 - 53.00 H Black 363 310 0.92 - 3.64 0.00 - 4.24 Notes: For this table and all subsequent figures: RSET = 324 ohms; V(RSET) = 1.235 V; 75 ohms doubly terminated load (BLR=61 for NTSC, and BLR=52 for PAL), 100% amplitude, 100% saturation bars are shown (100%=0.66071V). 1 Durations vary slightly in different modes due to the different clock frequencies used. 2 Active video times vary greatly due to different scaling ratios used in different modes. 3 Black times (F and H) vary with position controls. A B C D E F G H Figure 8: NTSC / PAL Composite Output 12 201-0000-029 Rev6.1, 8/2/99 CHRONTEL CH7002D CH7002D START OF VSYNC ANALOG FIELD 1 520 521 522 523 524 525 1 2 3 4 5 6 7 8 9 ANALOG FIELD 2 258 259 260 261 262 263 264 265 266 267 268 270 269 271 272 9 10 LINE RATE = HALF THE VGA LINE RATE IN MODES 1, 2, 4 AND 5 LINE RATE = HALF THE VGA LINE RATE IN MODES 11 & 12 (640 x 480) FIELD RATE = VGA VERTICAL REFRESH RATE IN ALL MODES FIELD RATE = VGA VERTICAL REFRESH RATE IN MODES 11 & 12 (640 x 480) Figure 9: Interlaced NTSC Video Timing START OF VSYNC ANALOG FIELD 1 620 621 622 623 624 625 1 2 3 4 5 6 7 8 ANALOG FIELD 2 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 ANALOG FIELD 3 620 621 622 623 624 625 1 2 3 4 5 6 7 8 9 10 ANALOG FIELD 4 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 Figure 10: Interlaced PAL Video Timing 201-0000-029 Rev 6.1, 8/2/99 13 CHRONTEL CH7002D CH7002D White Yellow 27.48 25.41 1.030 0.953 Cyan Green 22.08 20.01 0.828 0.750 Magenta Red 16.99 14.93 0.637 0.560 Blue Black Blank 11.59 9.69 8.26 0.435 0.363 0.310 Sync 0.64 Color bars: Black Blue Red Magenta V Green Cyan Yellow mA White Color/Level 0024 Figure 11: NTSC Y (Luminance) Output Waveform 26.05 23.98 0.977 0.899 Cyan Green 20.65 18.58 0.774 0.697 Magenta Red 15.56 13.50 0.584 0.506 Blue 10.16 0.381 Blank 8.26 0.310 Sync 0.64 Black White Yellow Color bars: Blue Red Magenta V Green Cyan Yellow mA White Color/Level 0.024 Figure 12: PAL Y (Luminance) Video Output Waveform 14 201-0000-029 Rev6.1, 8/2/99 CHRONTEL CH7002D CH7002D Black Blue 23.82 Red 1.012 0.989 Yellow/Blue Magenta 27.00 26.36 Green Cyan/Red Green/Magenta Cyan V Yellow mA White Color bars: Color/Level 0.893 Peak Burst 19.69 0.739 Blank 15.88 0.596 Peak Burst 12.07 0.337 3.579545 MHz Color Burst (9 cycles) Yellow/Blue 7.94 0.298 Green/Magenta Cyan/Red 5.40 4.76 0.202 0.179 Figure 13: NTSC C (Chrominance) Video Output Waveform Black Blue 23.82 Red 1.012 0.989 Yellow/Blue Magenta 27.00 26.36 Green Cyan/Red Green/Magenta Cyan V Yellow mA White Color bars: Color/Level 0.893 Peak Burst 19.69 0.739 Blank 15.88 0.596 Peak Burst 12.07 0.337 4.433619 MHz Color Burst (10 cycles) Yellow/Blue 7.94 0.298 Green/Magenta Cyan/Red 5.40 4.76 0.202 0.179 Figure 14: PAL C (Chrominance) Video Output Waveform 201-0000-029 Rev 6.1, 8/2/99 15 CHRONTEL CH7002D CH7002D 12.07 0.453 Black 9.69 0.363 Blank 8.26 Black 1.030 Peak Burst Blue 27.48 Red 1.251 White Magenta 33.35 Green Peak Chrome Cyan V Yellow mA White Color/Level 0.310 Peak Burst 4.45 Color bars: 0.167 3.579545 MHz Color Burst (9 cycles) Sync 0.64 0.024 Figure 15: Composite NTSC Video Output Waveform 8.26 0.310 Peak Burst 4.45 Black 0.453 Blank/Black Blue 12.07 Red 0.977 Peak Burst Magenta 26.05 Green 1.197 White Color bars: Cyan V Peak Chrome 31.92 White mA Yellow Color/Level 0.167 Sync 0.64 0.024 4.433619 MHz Color Burst (10 cycles) Figure 16: Composite PAL Video Output Waveform 16 201-0000-029 Rev6.1, 8/2/99 CHRONTEL CH7002D CH7002D I2C Port Operation The CH7002 CH7002 contains a standard I2C control port, through which the control registers can be written and read. This port is comprised of a two-wire serial interface, pins SD (bi-directional) and SC, which can be connected directly to the SDB and SCB buses as shown in Figure 17. The Serial Clock line (SC) is input only and is driven by the output buffer of the master device (also shown in Figure 17). The CH7002 CH7002 acts as a slave, and generation of clock signals on the bus is always the responsibility of the master device. When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. Data on the bus can be transferred up to 400 kbit/s. +VDD RP SDB (Serial Data Bus) SCB (Serial Clock Bus) SD SC DATAN2 OUT MASTER SCLK OUT FROM MASTER DATA IN MASTER BUS MASTER DATAN2 OUT SCLK IN1 DATA IN1 DATAN2 OUT SCLK IN2 SLAVE DATA IN2 SLAVE Figure 17: Connection of Devices to the Bus Electrical Characteristics for Bus Devices The electrical specifications of the bus devices' inputs and outputs and the characteristics of the bus lines connected to them are shown in Figure 17. A pull-up resistor (RP) must be connected to a 5V +/- 10% supply. The CH7002 CH7002 is a device with input levels related to VDD. Maximum and minimum values of pull-up resistor (R P) The value of RP depends on the following parameters: · Supply voltage · Bus capacitance · Number of devices connected (input current + leakage current = Iinput) The supply voltage limits the minimum value of resistor R P due to the specified minimum sink current of 3mA at VOLmax = 0.4 V for the output stages. · RP >= (VDD ­ 0.4) / 3 (RP in k) The bus capacitance is the total capacitance of wire, connections and pins. This capacitance limits the maximum value of RP due to the specified rise time. The equation for RP is shown below: · RP