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Part Manufacturer Description Datasheet BUY
CLP0212FPEX5Z03C GE Critical Power CLP0212 Open Frame Power Supply, 90 - 264Vac input; 12Vdc output; 200W Output Power visit GE Critical Power
CLP0212FPEX5Z02A GE Critical Power CLP0212 Open Frame Power Supply, 90 - 264Vac input; 12Vdc output; 200W Output Power visit GE Critical Power
CLP0412FPXXXZ01A GE Critical Power CLP0412 Open Frame Power Supply, 90 - 265Vac Input; 12Vdc Output; 450W Output Power visit GE Critical Power
CLP0212FPEX5Z03A GE Critical Power CLP0212 Open Frame Power Supply, 90 - 264Vac input; 12Vdc output; 200W Output Power visit GE Critical Power
CLP0412FPXXXZ03A GE Critical Power CLP0412 Open Frame Power Supply, 90 - 265Vac Input; 12Vdc Output; 450W Output Power visit GE Critical Power
CLP0212FPXX5Z03A GE Critical Power CLP0212 Open Frame Power Supply, 90 - 264Vac input; 12Vdc output; 200W Output Power visit GE Critical Power

CERAMIC PIN GRID ARRAY CPGA lead frame

Catalog Datasheet MFG & Type PDF Document Tags

GI 312 diode

Abstract: CERAMIC PIN GRID ARRAY CPGA lead frame , Type, or Name: 144-Pin Ceramic Pin Grid Array Die to Package edge clearance: 80 mils per side , Flatpack Ceramic/Plastic Pin Grid Array ESD Voltage Rating (per MIL STD-008, Method 3018): >1,000V , : DEVICE RELIABILITY SUMMARY VIC064/VIC068A 144-pins Ceramic Pin Grid Array 144-pins Plastic Pin Grid , Wafer Fab: 144-pins Ceramic Pin Grid Array Assembly: 144-pins Plastic Pin Grid Array Fab3 , Plastic Pin Grid Array Die to Package edge clearance: 42 mils per side Mold Compound Name
Cypress Semiconductor
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VIC64 VIC068A VAC068A CY7C964 GI 312 diode CERAMIC PIN GRID ARRAY CPGA lead frame ceramic pin grid array package wire bond CPGA 168 lead frame VIC064 CERAMIC PIN GRID ARRAY 144 pins 7C064-UMB V05032

GOERTZEL ALGORITHM SOURCE CODE

Abstract: 3x3 matrix HFH 305-pin C-PGA (Ceramic Pin Grid Array). This cavity down, heat slug up PGA RJA = 12.6°C/W weighs 41.5 grams. RJC = 0.3°C/W, 320-lead ceramic quad flat pack with 0.5 mm lead pitch. This cavity , Quad Flat Pack GF = Ceramic Pin Grid Array TOOLS SUPPORT Part Number TMDX3240680 TMDS00510 , ) 305-pin C-PGA 305-pin C-PGA 50 MHz 50 MHz 50 MHz 50 MHz n/a 5962-9679101QYC n/a , between external and internal SRAM Video controller with dual frame timers On-chip cache or data RAM is
Texas Instruments
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SM320C80 SMJ320C80 SPRA069 GOERTZEL ALGORITHM SOURCE CODE 3x3 matrix fixed point goertzel goertzel XDS510 TMDS3080002 SGYV006C IEEE-754 C80CD-ROM SPRC001B

QFN108

Abstract: QFN-132 v 11. 2 Package Mechanical Drawings Ceramic Pin Grid Array 84-Pin CPGA Top View 0.050" ± , Drawings Ceramic Pin Grid Array 100-Pin CPGA Top View 0.072" 0.88" Pin #1 ID 0.045" 0.055 , product is obsolete. 2 v11.1 Package Mechanical Drawings Ceramic Pin Grid Array 132-Pin CPGA , Package Mechanical Drawings Ceramic Pin Grid Array 175-Pin CPGA Top View Index Mark 0.100" BSC , Ceramic Pin Grid Array 176-Pin CPGA Top View Index Mark 0.105" ± 0.010" 0.100" BSC 0.018" ±
Actel
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QFN108 QFN-132 kl1-v1 208 pin rqfp drawing RT3PE3000L CQ256 qfn132 A1010B A1020B 100-P A1225XL A1415A 132-P

GOERTZEL ALGORITHM SOURCE CODE for dtmf in c

Abstract: fixed point goertzel the property of their respective owners. PACKAGING GF HFH 305-pin C-PGA (Ceramic Pin Grid Array). This cavity down, heat slug up PGA RJA = 12.6°C/W weighs 41.5 grams. RJC = 0.3°C/W, 320-lead ceramic quad flat pack with 0.5 mm lead pitch. This cavity up, heat slug down package has a nonconductive , Quad Flat Pack GF = Ceramic Pin Grid Array TOOLS SUPPORT Part Number TMDX3240680 TMDS00510 , SM320C80GFM50 SMJ320C80GFM50 320-lead C-QFP (NCTB) 320-lead C-QFP (NCTB) 305-pin C-PGA 305-pin C-PGA
Texas Instruments
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GOERTZEL ALGORITHM SOURCE CODE for dtmf in c c80 Master Processor architecture ti c80 architecture SPRA066 320C80 TMDX3248855-07

CERAMIC CHIP CARRIER LCC 68 socket

Abstract: INTEL 24 PIN CERAMIC DUAL-IN-LINE PACKAGE Socket Mount CQFP (Ceramic Quad Flatpack) CPGA (Ceramic Pin Grid Array) (bottom view , Table 1-3. Ceramic Pin Grid Array Lead Count 68 68 68 88 88 88 132 168 208 , Ceramic Pin Grid Array (CPGA), 0.100" Pitch for 68L - 208L, 0.100/0.50" for 264L- 387L Socket or , package design, such as the Tape Carrier Package (TCP), the Plastic Pin Grid Array (PPGA), the Plastic , footprint integrated circuits. Chapter 13 Plastic Pin Grid Array (PPGA) Packaging: An overview of Plastic
Intel
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CERAMIC CHIP CARRIER LCC 68 socket INTEL 24 PIN CERAMIC DUAL-IN-LINE PACKAGE LCCs 68 socket ic 7912 64 ceramic quad flatpack PLASTIC PIN GRID ARRAY PACKAGING

smd transistor HX

Abstract: TRANSISTOR SMD MARKING CODE TK Frit-Seal (CERDIP) or Ceramic Dual-In-Line Metal Seal (SBDIP) G: Ceramic Pin Grid Array (CPGA) R: Ceramic , : Plastic Leaded Chip Carrier (PLCC) G: Ceramic Pin Grid Array (CPGA) 35 /883 HIGH RELIABILITY , Side-Brazed (SBDIP) 8: Ceramic Pin Grid Array (CPGA) 9: Ceramic Flatpack 0: Die YE: SMD 0.5 9S: TO , DESIGNATOR D: Die G: Ceramic Pin Grid Array (CPGA) J: Plastic Leaded Chip Carrier (PLCC) P: Dual-In-Line , Grid Array (CPGA) H: Small Outline Transistor Plastic (SOT) J: Ceramic Dual-in-line Frit Seal (CERDIP
Intersil
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CD4000 smd transistor HX TRANSISTOR SMD MARKING CODE TK TRANSISTOR SMD MARKING CODE MP smd transistor HX 45 hc221 TRANSISTOR SMD MARKING CODE WM 82CXXX CD22XXX 1-888-INTERSIL JM38510/

transistor BC 458

Abstract: transistor a42 1285 1490 J28BQ CPGA (Continued) 295 600 J28B Ceramic Pin Grid Array (CPGA) MO , -066-AC 48400 32 22 18 16 5 U84B Ceramic Pin Grid Array (CPGA) MO-067-AB 14762 43 , Spec Wide Nom. (mils) Long Nom. (mils) Lead Frame Mt'l Pitch (mils) Board Area , ) Mkt Dwg JEDEC Spec Wide Nom. (mils) Long Nom. (mils) Lead Frame Mt'l Pitch (mils , (CQFP) Mkt Dwg JEDEC Spec Wide Nom. (mils) Long Nom. (mils) Lead Frame Mt'l
National Semiconductor
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transistor BC 458 transistor a42 MO-003 transistor Bc 540 ua109a UA65A AA84A AA84B ALE128A AUA128A AFB13

LM7603

Abstract: . LSI LOGIC L64760 Inter-Frame Processor Preliminary 100-Pin Plastic Pin Grid Array (PPGA) NG 100-Pin Ceramic Pin Grid Array (CPGA) FG N M L K J H G F E D C B A â'¢Â®Â®Â®Â®Â®Â®Â®Â , © â'¢ 1 2 3 4 5 6 7 8 910111213 Plastic and Ceramic Pin Grid Arrays (PPGA/CPGA) DifflMsioM , Grid Array Dimensions 12 LSI LOGIC L64760 Inter-Frame Processor Preliminary 100-Pin , Up to 30/40 MHz clock rates Simple external control 100-pin CPGA,PQFP or PPGA package PFO.Q:7
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OCR Scan
LM7603 L64750 L64740 MIL-STD-883C

transistor BC 458

Abstract: transistor BC 945 J28B Ceramic Pin Grid Array (CPGA) MO-058-AA MO-103-AB J28AQ Ceramic Small Outline Package , Grid Array (CPGA) None 160000 19 14 11 10 1 Data Not Available at This Time , ) Lead Frame Mt'l Pitch (mils) Board Area Max. (mils) (X) Max. (mils) (Y) None 645 , (LCC) Mkt Dwg JEDEC Spec Wide Nom. (mils) Long Nom. (mils) Lead Frame Mt'l , JEDEC Spec Wide Nom. (mils) Long Nom. (mils) Lead Frame Mt'l Pitch (mils) Board
National Semiconductor
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transistor BC 945 ac 1084 transistor bc 577 MS-015-AB Transistor BC 585 DA36A MS011795 AA44A AA68A MS-015-AA
Abstract: available in a 68-pin CPGA or PPGA (ceramic or plastic pin grid array) or 80-pin PQFP (plastic quad flat pack) package L64751 is available in a 68-pin CPGA or PPGA (ceramic or plastic pin grid array) or 100-pin , Coder/Decoder 68-Pin Plastic Pin Grid Array (PPGA) NB 68-Pin Ceramic Pin Grid Array (CPGA) FB L , and Ceramic Pin Grid Arrays (PPGA/CPGA) 68-Pin Dimensions PPGA (NB) CPGA (FB) A , E1- L Plastic and Ceramic Pin Grid Array Dimensions Notes: 1. Ceramic Packages are -
OCR Scan
L64750/51 L64730

845 bios chip

Abstract: bdv 83 d Full or quarter CIF L64750 is available in a 68-pin CPGA or PPGA (ceramic or plastic pin grid array , Variable Length Coder/Decoder 68-Pin Plastic Pin Grid Array (PPGA) NB 68-Pin Ceramic Pin Grid Array (CPGA , © 00O00OG0O 1 2 3 4 5 6 7 8 9 10 11 Plastic and Ceramic Pin Grid Arrays (PPGA/CPGA) TTTTTTÏ E1-B Plastic and Ceramic Pin Grid Array Dimensions Dimensions 68-Pin PPGA (NB) CPGA(FB) A Max 0.139 0.117 , Package Code G = 68-Pin Ceramic Grid Array N = 68-Pin Plastic Grid Array Q = 80-Pin, 100-Pin Plastic
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OCR Scan
845 bios chip bdv 83 d L-803

a5657

Abstract: ZIF socket design guidelines section describes insertion mounting of ceramic pin grid array (CPGA) packages into Low Insertion Force , Discharge Symposium Proceedings. [6] J.B. Cullinane, "Pin Grid Array Socket Total Forces", Proceedings , Failure Bond Wire Lead Frame Metal Interconnect Silicon Chip Header 241422-2 A5656 , Bond Wire Lead Frame Metal Interconnect Silicon Chip Header 241422-3 A5657-01 6.2.2 , packages have increased surface area and lead counts while the ceramic thickness has remained relatively
Intel
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a5657 ZIF socket design guidelines EOS ESD S 61.1 A5659-01 DOD-HNBK-263

a5657

Abstract: DOD Handbook 263 Damage 6.3.1 PGA Insertion This section describes insertion mounting of ceramic pin grid array , . [6] J.B. Cullinane, "Pin Grid Array Socket Total Forces", Proceedings of the 22nd Annual , Failure Bond Wire Lead Frame Metal Interconnect Silicon Chip Header 241422-2 A5656 , Bond Wire Lead Frame Metal Interconnect Silicon Chip Header 241422-3 A5657-01 6.2.2 , structure of the associated CPGA packages. The packages have increased surface area and lead counts while
Intel
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DOD Handbook 263 diode databook tote design technology

STP3010

Abstract: SUN HOLD ras 0910 comes in a 223-pin ceramic pin grid array (CPGA) package. FEATURES · 100 percent compatibility with , 223-Pin Ceramic Pin Grid Array (CPGA) Document Part Number: STP3010 20 July 1997 Sun , Preliminary TGX TurboGXTM Graphics Accelerator STP3010 PACKAGE INFORMATION 223-Pin Ceramic Pin Grid Array (CPGA) Pin Assignments Pin Pin Signal Pin Signal Pin A2 VCC Signal C12 , TGX TurboGXTM Graphics Accelerator STP3010 223-Lead CPGA Package Dimensions D N D2 J Q1
Sun Microelectronics
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STP3010PGA SUN HOLD ras 0910 ras 0910 MARK 4C7 display duplo 27C256 223-P

ARINC 629 sim

Abstract: m38510/55501 Pin Grid Arr ay LCC s Int. Tra nsc eiv Bus er Con trol Rem ler ote Ter Mo min , SM D# DIP Pin Grid Arr ay LCC Int. Tra nsc eiv Bus er Con trol Rem ler ote , Hole P10=1.86" x 1.86" 170 pin CPGA P11=1.86" x 1.86" 223 pin CPGA ADAPTER Cards-for migrating to , x .2") F3 ~ 36-pin CFP (.92" x .51" x .13") F4 ~ 36-pin CSOJ (.92 x .43" x .184") F6 ~ 32-lead , Series 56 pin plug-in 2.2" x 1.2"; terminal bit processor; +5V; also available in a 1.0" x 1.7" 60-lead
Aeroflex
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UT69151 ACT8600 ARINC 629 sim m38510/55501 AMP ARINC-629 SIM MT72038 CQFP 240 smd cmos 4435 UT1553B UT1553 UT1760A ARX5009 ARX5010

cpga weight

Abstract: Operations 32-Bit Barrel Shifter One 32-Bit Data Bus (24-Bit Address) Packaging ­ 132-Lead Ceramic Quad Flatpack With Nonconductive Tie-Bar (HFG Suffix) ­ 141-Pin Ceramic Staggered Pin Grid- Array Package (GFA Suffix) ­ 132-Lead TAB Frame ­ 132-Lead Plastic Quad Flatpack (PQ Suffix) description The SMJ320C31 , , SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS SGUS026F ­ APRIL 1998 ­ REVISED OCTOBER 2001 141-PIN GFA STAGGERED GRID ARRAY PACKAGE ( BOTTOM VIEW ) TA PACKAGE ( TOP VIEW ) 1 3 5 7 9 11 13 15 17 19 2 4 6 8
Texas Instruments
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cpga weight MIL-PRF-38535 SMJ320C31-60 SMJ320C31-50 SMJ320C31-40 SMJ320LC31-40 SMQ320LC31-40

CXD 4191

Abstract: H9925 full built-in scan testing capability 132-pin CPGA (Ceramic Pin Grid Array) package ©1986, 1987 , °C to 70°C) M ­ Military (-55°C to + 125°C) Package Code G ­ 132-Lead Ceramic Pin Grid Array Device Type , CPGA (Ceramic Pin Grid Array). The L64134 is functionally equivalent and pin compatible with the L64133 , Information 132-Pin Ceramic Pin Grid Array: See FH Package in Package Selector Guide L64032 G C -XX , Multiplier Array 64 CLKP CLKI TCX TCY SUB ADD SHFT XPLD FA RND PSEL OEXP 68-Bit Adder 68 Product Register
LSI Logic
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CXD 4191 H9925 jd 1803 b 107 jd 1803 data jd 1803 19 B L6421 H14000 DB05-000019-00

intel packaging

Abstract: CERAMIC PIN GRID ARRAY CPGA lead frame date) x x x 2 INTRODUCTION Table 1-3. Ceramic Pin Grid Array Lead Count 68 68 , 132 168 A A Cavity Down Cavity Down 208 240-280 272-320 387 Ceramic Pin Grid Array , Carrier Package (TCP), the Plastic Pin Grid Array (PPGA) and the Plastic Ball Grid Array (PBGA) packages , Introduces the new Plastic Pin Grid Array Package technology. Chapter 14 Provides a profile of the Intel , Grid Array 208 272 324 352 FW FW FW GC Sq Plastic Pin Grid Array 296 FV Sq
Intel
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intel packaging PLCC 68 intel package dimensions 68 CERAMIC LEADLESS CHIP CARRIER LCC QFP Shipping Trays tsop Shipping Trays INTEL CDIP 40 PIN CH01WIP

Ablebond 71-1

Abstract: Nitto (MM-PQFP) Ceramic quad flatpack (CQFP) Ceramic pin grid array (CPGA) Plastic pin grid array (PPGA , PACKAGES Table 4-1 Summary of CPGA Electrical Data Lead Count Electrical Parameter 68 CPGA 88 , 0 005 0 006 0 004 0 005 0 006 Lead Count Electrical Parameter 168 CPGA 208 , 0 006 Lead Count Electrical Parameter 280 CPGA 296 CPGA 320 CPGA 360 CPGA Min , cross-sectional dimensions (width and thickness) material and length of the lead Ceramic packages have relatively
Intel
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Ablebond 71-1 Nitto bimetal ABLEBONd 84-1 FR4 epoxy dielectric constant 4.4 thermal analysis on pcb 93-WA-EEP-6 91-WA-EEP-27 91-WA-EEP-31

C3150

Abstract: MO-069 , and Logical Operations 32-Bit Barrel Shifter One 32-Bit Data Bus (24-Bit Address) Packaging - 132-Lead Ceramic Quad Flatpack With Nonconductive Tie-Bar (HFG Suffix) - 141-Pin Ceramic Staggered Pin Grid- Array Package (GFA Suffix) - 132-Lead TAB Frame - 132-Lead Plastic Quad Flatpack (PQ Suffix , SGUS026G - APRIL 1998 - REVISED SEPTEMBER 2006 141-PIN GFA STAGGERED GRID ARRAY PACKAGE ( BOTTOM VIEW , L N R U W 34 TB PACKAGE ( TOP VIEW ) 132-PIN HFG QUAD FLATPACK ( TOP VIEW ) ÉÉ ÉÉ
Texas Instruments
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C3150 MO-069 SMJ320C31GFAM40 c3140
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