CDCM7005 SCAS793C P0022-01 P0023-01 B0057-01 T0058-01 T0060-01 S0079-01 - Datasheet Archive

 

www.ti.com SCAS793C ­ JUNE 2005 ­ REVISED DECEMBER 2007 3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER

 

CDCM7005 CDCM7005 www.ti.com SCAS793C SCAS793C ­ JUNE 2005 ­ REVISED DECEMBER 2007 3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER FEATURES 1 · GND GND GND GND GND C VBB GND AVCC AVCC AVCC AVCC AVCC GND STATUS_ REF or PRI_SEC_ CLK STATUS_ D VCXO_IN GND GND GND GND GND VCXO or VCC I_REF_CP E VCXO_IN GND VCC VCC VCC VCC VCC VCC F Y0A GND GND GND GND GND VCC Y4B G Y0B VCC VCC VCC VCC VCC VCC Y4A H PD Y1A Y1B Y2A Y2B Y3A Y3B RESET or HOLD SEC_REF CTRL_DATA PLL_LOCK CTRL_CLK AVCC AVCC CTRL_LE AVCC CP_OUT P0022-01 P0022-01 36 35 34 33 32 31 30 29 28 27 26 25 37 24 GND AVCC 38 23 AVCC 39 22 STATUS_REF or PRI_SEC_CLK STATUS_VCXO or I_REF_CP VBB 40 21 VCC VCC 41 20 VCC VCXO_IN 42 19 VCC VCXO_IN 43 18 VCC VCC 44 17 Y4B VCC 45 16 Y4A Y0A 46 15 VCC Y0B 47 14 VCC 48 1 2 3 4 5 6 7 8 9 13 10 11 12 RESET or HOLD VCC Y3A Thermal Pad must be soldered to GND Y3B · · · GND VCC · SEC_REF VCC · B Y2A · · CTRL_ DATA PLL_LOCK Y2B · 8 VCC · 7 VCC · 6 PRI_REF REF_SEL VCC_CP CP_OUT CTRL_LE CTRL_CLK NC · · 5 A VCC_CP · 4 Y1A · 3 Y1B · · 2 PRI_REF · 1 REF_SEL · PIN ASSIGNMENTS (TOP VIEW) PD · High Performance LVPECL and LVCMOS PLL Clock Synchronizer Two Reference Clock Inputs (Primary and Secondary Clock) for Redundancy Support With Manual or Automatic Selection Accepts LVCMOS Input Frequencies Up to 200 MHz VCXO_IN Clock is Synchronized to One of the Two Reference Clocks VCXO_IN Frequencies Up to 2.2 GHz (LVPECL) Outputs Can Be a Combination of LVPECL and LVCMOS (Up to Five Differential LVPECL Outputs or Up to 10 LVCMOS Outputs) Output Frequency is Selectable by x1, /2, /3, /4, /6, /8, /16 on Each Output Individually Efficient Jitter Cleaning From Low PLL Loop Bandwidth Low Phase Noise PLL Core Programmable Phase Offset (PRI_REF and SEC_REF to Outputs) Wide Charge Pump Current Range From 200 µA to 3 mA Dedicated Charge Pump Supply (VCC_CP) for Wide Tuning Voltage Range VCOs Presets Charge Pump to VCC_CP/2 for Fast Center-Frequency Setting of VC(X)O Analog and Digital PLL Lock Indication Provides VBB Bias Voltage Output for Single-Ended Input Signals (VCXO_IN) Frequency Hold-Over Mode Improves Fail-Safe Operation Power-Up Control Forces LVPECL Outputs to 3-State at VCC < 1.5 V SPI Controllable Device Setting 3.3-V Power Supply Packaged in 64-Pin BGA (0,8 mm Pitch ­ ZVA) or 48-Pin QFN (RGZ) Industrial Temperature Range ­40°C to 85°C VCC · P0023-01 P0023-01 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005­2007, Texas Instruments Incorporated CDCM7005 CDCM7005 www.ti.com SCAS793C SCAS793C ­ JUNE 2005 ­ REVISED DECEMBER 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION The CDCM7005 CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O: · VC(X)O_IN / PRI_REF = (N x P) / M or · VC(X)O_IN / SEC_REF = (N x P) / M VC(X)O_IN clock operates up to 2.2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements. The CDCM7005 CDCM7005 can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005 CDCM7005 are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The LVCMOS outputs are arranged in pairs (Y0A:Y0B, Y1A:Y1B, .), so that each pair has the same frequency. But each output can be separately inverted and disabled. The built in synchronization latches ensure that all outputs are synchronized for low output skew. All device settings, like outputs signaling, divider value, input selection, and many more, are programmable by SPI (3-wire serial peripheral interface). SPI allows individually control of the device settings. The device operates in 3.3-V environment and is characterized for operation from ­40°C to 85°C. 2 Submit Documentation Feedback Copyright © 2005­2007, Texas Instruments Incorporated Product Folder Link(s) :CDCM7005 CDCM7005 CDCM7005 CDCM7005 www.ti.com SCAS793C SCAS793C ­ JUNE 2005 ­ REVISED DECEMBER 2007 FUNCTIONAL BLOCK DIAGRAM VCC AVCC VCC_CP Selected REF Signal REF_SEL Manual & Automatic CLK Select STATUS_REF/ PRI_SEC_CLK STATUS_VCXO/ I_REF_CP freq. Detect > 2 Mhz PLL_LOCK freq. Detect > 2 Mhz LOCK LVCMOS SEC_REF R EF_M UX PRI_REF Progr. Delay M Reference Clock Feedback Clock Progr. Delay N Progr. Divider HOLD PFD Charge Pump Progr. Divider 10 M 2 N 2 Current Reference SPI LOGIC CTRL_LE CP_OUT 12 CTRL_DATA CTRL_CLK PECL to LVCMOS LV CMOS RESET or HOLD FB_MUX Y0_MUX Y0A PD LV PECL Y0B LV CMOS LV CMOS Y1_MUX Y1A ÷1 LV PECL Y1B ÷2 LV CMOS ÷3 LV CMOS ÷4 VCXO_IN PECL INPUT Y2A Y2_MUX VCXO_IN ÷6 LV PECL Y2B /8 ÷8 LV CMOS ÷ 16 LV CMOS 90o 90o Y3A Y3_MUX ÷4 ÷8 P16-Div LV PECL P Divider Y3B LV CMOS LV CMOS Bias Generator VCC ­ 1.3V Y4A Y4_MUX VBB LV PECL Y4B LV CMOS GND B0057-01 B0057-01 Submit Documentation Feedback Copyright © 2005­2007, Texas Instruments Incorporated Product Folder Link(s) :CDCM7005 CDCM7005 3 CDCM7005 CDCM7005 www.ti.com SCAS793C SCAS793C ­ JUNE 2005 ­ REVISED DECEMBER 2007 Table 1. PIN ASSINGMENT TERMINAL NAME I/O DESCRIPTION BGA QFN VCC D7, E3, E4, E5, E6, E7, E8, F7, G2, G3, G4, G5, G6, G7 2, 5, 6, 9, 10, 13, 15, 18, 19, 20, 21, 41, 44, 45; 48 Power 3.3-V supply. There is no internal connection between VCC and AVCC. It is recommended that AVCC use its own supply filter. GND B2, B3, B4, B5, B6, B7, B8, C2, D2, D3, D4, D5, D6, E2, F2, F3, F4, F5, F6 Thermal pad and pin 24 Ground Ground AVCC C3, C4, C5, C6, C7 27, 30, 32, 38, 39 Analog Power 3.3-V analog power supply. There is no internal connection between AVCC and VCC. It is recommended that AVCC use its own supply filter. VCC_CP A3 33 Power This is the charge pump power supply pin used to have the same supply as the external VCO. It can be set from 2.3 V to 3.6 V. CTRL_LE A5 29 I LVCMOS input, control latch enable for serial programmable Interface (SPI), with hysteresis CTRL_CLK A6 28 I LVCMOS input, serial control clock input for SPI, with hysteresis CTRL_DATA A7 26 I LVCMOS input, serial control data input for SPI, with hysteresis I LVCMOS input, asynchronous power down (PD) signal. This pin is low active and can be activated external or by the corresponding bit in the SPI register (in case of logic high, the SPI setting is valid). Switches the device into power-down mode. Resets M- and N-Divider, 3-states charge pump, STATUS_REF, or PRI_SEC_CLK pin, STATUS_VCXO or I_REF_CP pin, PLL_LOCK pin, VBB pin and all Yx outputs. Sets the SPI register to default value; has internal 150-k pullup resistor. PD H1 1 This LVCMOS input can be programmed (SPI) to act as HOLD or RESET. RESET is the default function. This pin is low active and can be activated external or via the corresponding bit in the SPI register. In case of RESET, the charge pump (CP) is switched to 3-state and all counters (N, M, P) are reset to zero (the initial divider settings are maintained in SPI registers). The LVPECL outputs are static low and high respectively and the LVCMOS outputs are all low or high if inverted. RESET is not edge triggered and should have a pulse duration of at least 5 ns. RESET or HOLD H8 VCXO_IN E1 43 I VCXO LVPECL input VCXO_IN D1 42 I Complementary VCXO LVPECL input PRI_REF A1 36 I LVCMOS input for the primary reference clock, with an internal 150-k pullup resistor and input hysteresis. SEC_REF B1 37 I LVCMOS input for the secondary reference clock, with an internal 150-k pullup resistor and input hysteresis. 14 I In case of HOLD, the CP is switched in to 3-state mode only. After HOLD is released and with the next valid reference clock cycle the charge pump is switched back in to normal operation (CP stays in 3-state as long as no reference clock is valid). During HOLD, the P divider and all outputs Yx are at normal operation. This mode allows an external control of the frequency hold-over mode. The input has an internal 150-k pullup resistor. REF_SEL A2 35 I LVCMOS reference clock selection input. In the manual mode the REF_SEL signal selects one of the two input clocks: REF_SEL [1]: PRI_REF is selected; REF_SEL [0]: SEC_REF is selected; The input has an internal 150-k pullup resistor. CP_OUT A4 31 O Charge pump output 4 Submit Documentation Feedback Copyright © 2005­2007, Texas Instruments Incorporated Product Folder Link(s) :CDCM7005 CDCM7005 CDCM7005 CDCM7005 www.ti.com SCAS793C SCAS793C ­ JUNE 2005 ­ REVISED DECEMBER 2007 Table 1. PIN ASSINGMENT (continued) TERMINAL NAME VBB BGA QFN C1 40 I/O DESCRIPTION Bias voltage output to be used to bias unused complementary input VCXO_IN for single ended signals. The output of VBB is VCC ­ 1.3 V. The output current is limited to about 1.5 mA. O This output can be programmed (SPI) to provide either the STATUS_REF or PRI_SEC_CLK information. This pin is set high if one of the STATUS conditions is valid. STATUS_REF is the default setting. STATUS_REF or PRI_SEC_CLK C8 23 In case of STATUS_REF, the LVCMOS output provides the Status of the Reference Clock. If a reference clock with a frequency above 2 MHz is provided to PRI_REF or SEC_REF STATUS_REF will be set high. O In case of PRI_SEC_CLK, the LVCMOS output indicates whether the primary clock [high] or the secondary clock [low] is selected. This LVCMOS output can be programmed (SPI) to provide either the STATUS_VCXO information or serve as current path for the charge pump (CP). STATUS_VCXO is the default setting. STATUS_VCXO or I_REF_CP D8 22 In case of STATUS_VCXO, the LVCMOS output provides the status of the VCXO input (frequencies above 2 MHz are interpreted as valid clock; active high). O In case of I_REF_CP, it provides the current path for the external reference resistor (12 k ±1%) to support an accurate charge pump current, optional. Do not use any capacitor across this resistor to prevent noise coupling via this node. If the internal 12 k is selected (default setting), this pin can be left open. LVCMOS output for PLL_LOCK information. This pin is set high if the PLL is in lock (see feature description). This output can be programmed to be digital lock detect or analog lock detect (see feature description). PLL_LOCK A8 25 The PLL is locked (set high), if the rising edge either of PRI_REF or SEC_REF clock and VCXO_IN clock at the phase frequency detector (PFD) are inside the lock detect window for a predetermined number of successive clock cycles. I/O The PLL is out-of-lock (set low), if the rising edge of either the PRI_REF or SEC_REF) clock and VCXO_IN clock at the PFD are outside the lock detect window or if a cycle-slip occurs. Both, the lock detect window and the number of successive clock cycles are user definable (via SPI). Y0A:Y0B Y1A:Y1B Y2A:Y2B Y3A:Y3B Y4A:Y4B F1, G1, H2, H3, H4, H5, H6, H7, G8, F8 46, 47, 3, 4, 7, 8, 11,12, 16, 17 The outputs of the CDCM7005 CDCM7005 are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The outputs are selectable via SPI (Word 1, Bit 2-6). The power-up setting is all outputs are LVPECL. O ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE / UNIT (2) VCC, AVCC, VCC_CP Supply voltage range VI Input voltage range VO Output voltage range (3) ­0.5 V to VCC + 0.5 V IOUT Output current for LVPECL/LVCMOS outputs (0 < VO < VCC) ±50 mA IIN Input current (VI < 0, VI > VCC) Tstg Storage temperature range TJ Maximum junction temperature (1) (2) (3) (3) ­0.5 V to 4.6 V ­0.5 V to VCC + 0.5 V ±20 mA ­65°C to 150°C 125°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute­maximum­rated conditions for extended periods may affect device reliability. All supply voltages have to be supplied at the same time. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. Submit Documentation Feedback Copyright © 2005­2007, Texas Instruments Incorporated Product Folder Link(s) :CDCM7005 CDCM7005 5 CDCM7005 CDCM7005 www.ti.com SCAS793C SCAS793C ­ JUNE 2005 ­ REVISED DECEMBER 2007 Package Thermal Resistance for RGZ (QFN) Package (1) Airflow (lfm) JA (°C/W) (2) JC (°C/W) JP (°C/W) 22.4 JT (°C/W) (3) 0 24.7 0.2 250 23.2 0.2 500 (1) (2) (3) 29.9 150 1.5 0.2 21.5 0.3 The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board). Connected to GND with nine thermal vias (0,3 mm diameter). JP (junction pad) is used for the QFN package, because the main heat flow is from the junction to the GND pad of the QFN. Package Thermal Resistance for ZVA (BGA) Package (1) Airflow (m/s) JC (°C/W) 0 m/s 53.9 28.3 1 m/s 49.8 0.7 2 m/s (1) (2) JA (°C/W) JB (°C/W) JT (°C/W) 48.5 0.8 (2) 38.6 0.7 The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board). JB (junction board) is used for the BGA package, because the main heat flow is from junction to the board. RECOMMENDED OPERATING CONDITIONS MIN VCC, AVCC VCC_CP Supply voltage NOM MAX 3 3.3 3.6 2.3 VIL Low-level input voltage LVCMOS, see High-level input voltage LVCMOS, see (1) IOH High-level output current LVCMOS (includes all status pins) IOL Low-level output current LVCMOS (includes all status pins) VI Input voltage range LVCMOS VINPP Input amplitude LVPECL (VVCXO_IN ­ VVCXO_IN) (2) VIC Common-mode input voltage LVPECL TA Operating free-air temperature (1) (2) V VCC (1) VIH UNIT 0.3 VCC V 0.7 VCC V ­8 mA 8 mA 0 3.6 V 0.5 1.3 V 1 VCC­0.3 V ­40 85 °C VIL and VIH are required to maintain ac specifications; the actual device function tolerates a smaller input level of 1V, if an ac-coupling to VCC/2 is provided. VINPP minimum and maximum is required to maintain ac specifications; the actual device function tolerates at a minimum VINPP of 150 mV. TIMING REQUIREMENTS over recommended ranges of supply voltage, load and operating free air temperature PARAMETER MIN TYP MAX UNIT 0 200 MHz 40% 60% 0 2200 PRI_REF/SEC_REF_IN REQUIREMENTS fREF_IN LVCMOS primary or secondary reference clock frequency (1) (2) tr/ tf Rise and fall time of PRI_REF or SEC_REF signals from 20% to 80% of VCC dutyREF Duty cycle of PRI_REF or SEC_REF at VCC/2 4 ns VCXO_IN, VCXO_IN REQUIREMENTS fVCXO_IN VCXO clock frequency (3) tr/ tf Rise and fall time 20% to 80% of VINPP at 80 MHz to 800 MHz (4) (1) (2) (3) (4) 6 MHz 3 ns At Reference Clock less than 2 MHz, the device stays in normal operation mode but the frequency detection circuitry resets the STATUS_REF signal to low. In this case, the status of the STATUS_REF is no longer relevant. fREF_IN can be up to 250 MHz in typical operating mode (25°C / 3.3-V VCC). If the Feedback Clock (derives from VCXO input) is less than 2 MHz, the device stays in normal operation mode but the frequency detection circuitry resets the STATUS_VCXO signal and PLL_LOCK signal to low. Both status signals are no longer relevant. This effects the HOLD-over function as well, as the PLL_LOCK signal is no longer valid! Use a square wave for lower frequencies (< 80 MHz). Submit Documentation Feedback Copyright © 2005­2007, Texas Instruments Incorporated Product Folder Link(s) :CDCM7005 CDCM7005 CDCM7005 CDCM7005 www.ti.com SCAS793C SCAS793C ­ JUNE 2005 ­ REVISED DECEMBER 2007 TIMING REQUIREMENTS (continued) over recommended ranges of supply voltage, load and operating free air temperature PARAMETER dutyVCXO MIN Duty cycle of VCXO clock TYP 40% MAX UNIT 60% SPI/CONTROL REQUIREMENTS (see Figure 14) fCTRL_CLK CTRL_CLK frequency 20 MHz tsu1 CTRL_DATA to CTRL_CLK setup time 10 ns th2 CTRL_DATA to CTRL_CLK hold time 10 ns t3 CTRL_CLK high duration 25 ns t4 CTRL_CLK low duration 25 ns tsu5 CTRL_LE to CTRL_CLK setup time 10 ns tsu6 CTRL_CLK to CTRL_LE setup time 10 ns t7 CTRL_LE pulse width 20 tr/ tf Rise and fall time of CTRL_DATA CTRL_CLK, CTRL_LE from 20% to 80% of VCC ns 4 ns 4 ns PD, RESET, HOLD, REF_SEL REQUIREMENTS tr / tf Rise and fall time of the PD, RESET, HOLD, REF_SEL signal from 20% to 80% of VCC DEVICE CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) TYP (1) MAX UNIT fVCXO = 245.76 MHz, fREF_IN = 30.72 MHz, PFD = 240 kHz, ICP = 2 mA, all outputs are LVPECL and Div-by-8 (load, see Figure 13) 210 260 mA fVCXO = 245.76 MHz, fREF_IN = 30.72 MHz, PFD = 240 kHz, ICP = 2 mA, All outputs are LVCMOS and Div-by-8 (load, 10 pF) 120 150 mA fIN = 0 MHz, VCC = 3.6 V, AVCC = 3.6 V, VCC_CP = 3.6 V, VI = 0 V or VCC PARAMETER 100 300 µA ±40 µA ±100 µA TEST CONDITIONS MIN OVERALL ICC_LVPECL Supply current (ICC over frequency see Figure 1 through Figure 4) ICC_LVCMOS ICCPD Power-down current IOZ High-impedance state output current for Yx outputs VO = 0 V or VCC ­ 0.8 V VI_REF_CP Voltage on I_REF_CP (external current path for accurate charge pump current) 12 k to GND at pin D8 (BGA), pin 22 (QFN) VBB Output reference voltage VCC = 3 V ­ 3.6 V; IBB = ­0.2 mA CO Output capacitance for Yx VCC = 3.3 V, VO = 0 V or VCC Input capacitance at PRI_REF and SEC_REF VI = 0 V or VCC, VI = 0 V or VCC Input capacitance at CTRL_LE, CTRL_CLOCK, CTRL_DATA VI = 0 V or VCC CI VO = 0 V or VCC 1.21 V VCC­1.3 V 2 pF 2.7 pF 2 LVCMOS fclk Output frequency, see and Figure 7 VIK (2) (3) Load = 5 pF to GND, 1 k to VCC, 1 k to GND 250 MHz LVCMOS input clamp voltage VCC = 3 V, II = ­18 mA ­1.2 V II LVCMOS input current for CTRL_LE, CTRL_CLK, CTRL_DATA VI = 0 V or VCC, VCC = 3.6 V ±5 µA IIH LVCMOS input current for PD, RESET, HOLD, REF_SEL, PRI_REF, SEC_REF, (see (4) VI = VCC, VCC = 3.6 V 5 µA (1) (2) (3) (4) , , Figure 6, All typical values are at VCC = 3.3 V, temperature = 25°C. fclk can be up to 400 MHz in the typical operating mode (25°C / 3.3-V VCC). The total power consumption limit of 700 mW for the BGA package can be violated if several LVCMOS outputs switch at high frequency (see Figure 3 and Figure 4). Operating the LVCMOS or LVPECL output above the maximum frequency will not cause a malfunction to the device, but the output signal swing may no longer meet the output specification. These inputs have an internal 150-k pullup resistor. Submit Documentation Feedback Copyright © 2005­2007, Texas Instruments Incorporated Product Folder Link(s) :CDCM7005 CDCM7005 7 CDCM7005 CDCM7005 www.ti.com SCAS793C SCAS793C ­ JUNE 2005 ­ REVISED DECEMBER 2007 DEVICE CHARACTERISTICS (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IIL LVCMOS input current for PD, RESET, HOLD, REF_SEL, PRI_REF, SEC_REF, (see (4) VOH High-level output voltage for LVCMOS outputs VI = 0 V, VCC = 3.6 V VCC = min to max, IOH = ­100 µA VCC = 3 V, IOH = ­6 mA VCC = 3 V, IOH = ­12 mA MIN TYP (1) UNIT ­35 ­15 MAX µA VCC­0.1 V 2.4 2 VCC = min to max, IOL = 100 µA 0.1 VCC = 3 V, IOL = 6 mA 0.5 VOL Low-level output voltage for LVCMOS outputs IOH High-level output current VCC = 3.3 V, VO = 1.65 V ­30 mA IOL Low-level output current VCC = 3.3 V, VO = 1.65 V 33 mA VREF_IN = VCC/2, Y = VCC/2, see Figure 11, Load = 10 pF 1.8 ns VCC = 3 V, IOL = 12 mA (5) 0.8 tpho Phase offset (REF_IN to Y output) tsk(p) LVCMOS pulse skew, see Figure 10 Crosspoint to VCC/2 load, see Figure 12 tpd(HL) Propagation delay from VCXO_IN to Yx, see Figure 10 Crosspoint to VCC/2, Load = 10 pF, see Figure 12 (PLL bypass mode) tsk(o) LVCMOS single-ended output skew, see (6) and Figure 10 All outputs have the same divider ratio 55 Outputs have different divider ratios 70 Duty cycle LVCMOS VCC/2 to VCC/2 Output rise/fall slew rate 20% to 80% of swing (load see Figure 12) tpd(LH) tslew-rate V 150 2 2.5 49% 2.4 ps 3 ns ps 51% 3.5 V/ns LVPECL (7) fclk Output frequency, see II LVPECL input current and Figure 5 VI = 0 V or VCC VOH LVPECL high-level output voltage Load, See Figure 13 VOL LVPECL low-level output voltage Load, See Figure 13 |VOD| Differential output voltage See Figure 9 and load, see Figure 13 500 tpho Phase offset (REF_IN to Y output) (8) VREF_IN = VCC/2 to cross point of Y, see Figure 11 ­200 tpd(LH) tpd(HL) Propagation delay time, VCXO_IN to Yx, see Figure 10 Cross point-to-cross point, load see Figure 13 tsk(p) LVPECL pulse skew, see Figure 10 tsk(o) LVPECL output skew (8) tr / tf Rise and fall time CI Load, see Figure 13 0 1500 MHz ±20 µA VCC­1.18 VCC­0.81 V VCC­2 VCC­1.55 V mV 100 ps 640 ps Cross point-to-cross point, load see Figure 13 10 ps Load see Figure 13, all outputs have the same divider ratio 20 Load see Figure 13, outputs have different divider ratios 50 20% to 80% of VOUTPP, see Figure 9 340 490 ps Input capacitance at VCXO_IN, VCXO_IN 120 170 220 1.5 ps pF LVCMOS-TO-LVPECL tsk(P_C) Output skew between LVCMOS and LVPECL outputs, see (9) and Figure 10 Cross point to VCC/2; load, see Figure 12 and Figure 13 1.7 2 2.4 ns PLL ANALOG LOCK IOH High-level output current VCC = 3.6 V, VO = 1.8 V ­110 µA IOL Low-level output current VCC = 3.6 V, VO = 1.8 V 110 µA (5) (6) (7) (8) (9) 8 This is valid only for the same frequency of REF_IN clock and Y output clock. It can be adjusted by the SPI controller (reference delay M and VCXO delay N). The tsk(o) specification is only valid for equal loading of all outputs. Operating the LVCMOS or LVPECL output above the maximum frequency will not cause a malfunction to the device, but the output signal swing may no longer meet the output specification. The tsk(o) specification is only valid for equal loading of all outputs. The phase of LVCMOS is lagging in reference to the phase of LVPECL. Submit Documentation Feedback Copyright © 2005­2007, Texas Instruments Incorporated Product Folder Link(s) :CDCM7005 CDCM7005 CDCM7005 CDCM7005 www.ti.com SCAS793C SCAS793C ­ JUNE 2005 ­ REVISED DECEMBER 2007 DEVICE CHARACTERISTICS (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TYP (1) 65 µA ±5 MIN MAX 45 TEST CONDITIONS µA UNIT IOZH LOCK High-impedance state output current for PLL LOCK output (10) IOZL LOCK High-impedance state output current for PLL LOCK output (10) VO = 0 V (PD is set low) VIT+ Positive input threshold voltage VCC = min to max VCC×0.55 V VIT­ Negative input threshold voltage VCC = min to max VCC×0.35 V VO = 3.6 V (PD is set low) PHASE DETECTOR fCPmax Maximum charge pump frequency Default PFD pulse width delay ICP Charge pump sink/source current range (11) VCP = 0.5 VCC_CP ICP3St Charge pump 3-state current 100 0.5 V < VCP < VCC_CP ­ 0.5 V MHz ±3 mA 10 nA CHARGE PUMP ±0.2 VCP = 0.5 VCC_CP, internal reference resistor, SPI default settings ICPA ICP absolute accuracy 10% VCP = 0.5 VCC_CP, external reference resistor 12 k (1%) at I_REF_CP, SPI default settings ICPM Sink/source current matching 0.5 V < VCP < VCC_CP ­ 0.5 V, SPI default settings IVCPM ICP vs VCP matching 5% 0.5 V < VCP < VCC_CP ­ 0.5 V 2.5% 5% (10) Lock output has an 80-k pulldown resistor. (11) Defined by SPI settings. TYPICAL CHARACTERISTICS LVPECL SUPPLY CURRENT vs NUMBER OF ACTIVE OUTPUTS 250 All Output Pairs Active (4 div-by-8 / 1 div-by-3) 230 For div-by-3/6 ICC - Supply Current - mA 210 190 All Output Pairs Active (div-by-8) 170 All Output Pairs Active (div-by-1) 150 VCC = 3.3 V TA = 25°C for div-by-2/4/8/16 130 One Output Pair Active (div-by-8) 110 90 For 1 Output Pair No Output Active 70 50 50 250 450 650 850 1050 1250 1450 1650 1850 2050 VCXO_IN Input Frequency - MHz G001 A. If div-by-2/4/8/16 is activated for one or more outputs, ' for div-by-2/4/8/16' has to be added to ICC of div-by-1. If div-by-3 or div-by-6 is activated, ' for div-by-2/4/8/16' and ' for div-by3/6' has to be added to ICC of div-by-1. Figure 1. Submit Documentation Feedback Copyright © 2005­2007, Texas Instruments Incorporated Product Folder Link(s) :CDCM7005 CDCM7005 9 CDCM7005 CDCM7005 www.ti.com SCAS793C SCAS793C ­ JUNE 2005 ­ REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) LVPECL DEVICE POWER CONSUMPTION vs NUMBER OF ACTIVE OUTPUTS PDEV - Device Power Consumption - mW 750 VCC = 3.3 V TA = 25°C 650 All Output Pairs Active (4 div-by-8 / 1 div-by-3) 550 All Output Pairs Active (div-by-8) 450 All Output Pairs Active (div-by-1) One Output Pair Active (div-by-8) 350 250 150 No Output Active 50 50 250 450 650 850 1050 1250 1450 1650 1850 2050 VCXO_IN Input Frequency - MHz G002 Figure 2. LVCMOS SUPPLY CURRENT / DEVICE POWER CONSUMPTION vs NUMBER OF ACTIVE OUTPUTS (Load = 5 pF) Icc - Supply Current - mA 200 all outputs active div-by-3 700 600 D for div-by-3/6 150 all outputs active div-by-1 one output pair active div-by-1 100 500 400 300 D for 1 output 50 D for 1 output pair 200 100 one output active div-by-1 PDEV - Power Device Consumption - mW 800 Vcc = 3.3V TA = 255C load = 5 pF no output active 0 50 100 150 200 250 0 300 Output Frequency - MHz A. To estimate ICC with different P-divider settings use ' for div-by-2/4/8/16' and ' for div-by-3/6' of Figure 1. B. It is not recommended to exceed power dissipation of 700 mW for the BGA package at TA 85°C. Figure 3. 10 Submit Documentation Feedback Copyright © 2005­2007, Texas Instruments Incorporated Product Folder Link(s) :CDCM7005 CDCM7005 CDCM7005 CDCM7005 www.ti.com SCAS793C SCAS793C ­ JUNE 2005 ­ REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) LVCMOS SUPPLY CURRENT / DEVICE POWER CONSUMPTION vs NUMBER OF ACTIVE OUTPUTS (Load = 10 pF) 900 VCC = 3.3 V TA = 255C Load = 10 pF all outputs active div-by-3 800 700 200 600 D for div-by-3/6 500 150 all outputs active div-by-1 400 one output pair active div-by-1 100 300 D for 1 output 50 D for 1 output pair PDEV - Device Power Consumption - mW Icc - Supply Current - mA 250 200 100 one output active div-by-1 no output active 0 40 60 80 100 120 140 160 180 200 220 240 260 280 0 300 Output Frequency - MHz A. To estimate ICC with different P-divider settings use ' for div-by-2/4/8/16' and ' for div-by-3/6' of Figure 1. B. It is not recommended to exceed power dissipation of 700 mW for the BGA package at TA 85°C. Figure 4. DIFFERENTIAL LVPECL OUTPUT VOLTAGE vs OUTPUT FREQUENCY VOD - Differential Output Voltage - V 0.90 VCC = 3.3 V TA = 25°C Termination = 50 W to VCC - 2 V 0.85 0.80 0.75 0.70 0.65 0.60 0.55 0.50 50 250 450 650 850 1050 1250 fOut - Output Frequency - MHz 1450 1650 1850 G005 Figure 5. Submit Documentation Feedback Copyright © 2005­2007, Texas Instruments Incorporated Product Folder Link(s) :CDCM7005 CDCM7005 11 CDCM7005 CDCM7005 www.ti.com SCAS793C SCAS793C ­ JUNE 2005 ­ REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) LVCMOS OUTPUT SWING vs FREQUENCY 3.6 VCC = 3.6 V 3.4 LVCMOS Output Swing - V 3.2 3.0 2.8 2.6 VCC = 3.3 V 2.4 VCC = 3 V 2.2 2.0 1.8 TA = 25°C Load = 5 pF (See Figure 12) 1.6 1.4 50 100 150 200 250 300 350 400 450 500 f - Frequency - MHz G006 Figure 6. LVCMOS OUTPUT SWING vs FREQUENCY 3.6 3.4 VCC = 3.6 V LVCMOS Output Swing - V 3.2 3.0 2.8 2.6 2.4 VCC = 3.3 V 2.2 VCC = 3 V 2.0 1.8 TA = 25°C Load = 10 pF (See Figure 12) 1.6 1.4 50 100 150 200 250 300 350 400 450 500 f - Frequency - MHz G007 Figure 7. 12 Submit Documentation Feedback Copyright © 2005­2007, Texas Instruments Incorporated Product Folder Link(s) :CDCM7005 CDCM7005 CDCM7005 CDCM7005 www.ti.com SCAS793C SCAS793C ­ JUNE 2005 ­ REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) OUTPUT REFERENCE VOLTAGE (VBB) vs LOAD 4.0 VCC = 3.3 V TA = 25°C VBB - Output Reference Voltage - V 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -5 0 5 10 15 20 25 30 35 I - Load - mA G008 Figure 8. PARAMETER MEASUREMENT INFORMATION Yx VOH VOD Yx VOL 80% 20% 0V tr VOUTpp tf T0058-01 T0058-01 Figure 9. LVPECL Differential Output Voltage and Rise/Fall Time Submit Documentation Feedback Copyright © 2005­2007, Texas Instruments Incorporated Product Folder Link(s) :CDCM7005 CDCM7005 13 CDCM7005 CDCM7005 www.ti.com SCAS793C SCAS793C ­ JUNE 2005 ­ REVISED DECEMBER 2007 PARAMETER MEASUREMENT INFORMATION (continued) LVPECL VCXO_IN /VCXO_IN tpd(LH) / tpd(HL); tsk(p) = | tpd(HL) - tpd(LH) | YxA LVPECL YxB YxA LVPECL YxB tsk(o)LVPECL YxA LVPECL YxB YxA LVCMOS tsk p_c LVCMOS VCXO_IN /VCXO_IN tpd(LH); tsk(p) = | tpd(HL) - tpd(LH) | YxA/B LVCMOS tsk(o)LVCMOS YxA/B LVCMOS A. Output skew, tsk(o), is calculated as the greater of: The difference between the fastest and the slowest tpd(LH)n (n = 0.4) The difference between the fastest and the slowest tpd(HL)n (n = 0.4) B. Pluse skew, tsk(p), is calculated as the magnitude of the absolute time difference between the high-to-low (tpd(HL) and the low-to-high (tpd(LH) propagation delays when a single switching input causes one or more outputs to switch, tsk(p) = |tpd(HL) ­ tpd(LH) |. Pulse skew is sometimes refered to as pulse width distortion or duty cycle skew. Figure 10. Output Skew 14 Submit Documentation Feedback Copyright © 2005­2007, Texas Instruments Incorporated Product Folder Link(s) :CDCM7005 CDCM7005 CDCM7005 CDCM7005 www.ti.com SCAS793C SCAS793C ­ JUNE 2005 ­ REVISED DECEMBER 2007 PARAMETER MEASUREMENT INFORMATION (continued) VIH 50% VCC VIL REF_IN tpho LVPECL VOH YxB LVPECL VOL YxA tpho LVCMOS VOH LVCMOS VOL T0060-01 T0060-01 Figure 11. Phase Offset CDCM7005 CDCM7005 1kW Y3 LVCMOS 1kW 10pF S0079-01 S0079-01 Figure 12. LVCMOS Output Loading During Device Test VCC ZO = 50W Yx CDCM7005 CDCM7005 Driver LVPECL Receiver ZO = 50W Yx 50W 50W VEE VT = VCC ­ 2V S0078-01 S0078-01 Figure 13. LVPECL Output Loading During Device Test Submit Documentation Feedback Copyright © 2005­2007, Texas Instruments Incorporated Product Folder Link(s) :CDCM7005 CDCM7005 15 CDCM7005 CDCM7005 www.ti.com SCAS793C SCAS793C ­ JUNE 2005 ­ REVISED DECEMBER 2007 PARAMETER MEASUREMENT INFORMATION (continued) SPI CONTROL INTERFACE The serial interface of the CDCM7005 CDCM7005 is a simple SPI-compatible interface for writing to the registers of the device and consists of three control lines: CTRL_CLK, CTRL_DATA, and CTRL_LE. There are four 32-bit wide registers, which can be addressed by the two LSBs of a transferred word (bit 0 and bit 1). Every transmitted word must have 32 bits, starting with MSB first. Each word can be written separately. Bit 7, 8, 10, and Bit 12 to 31 of Word 3 are reserved for factory test purposes and must be filled with zeros. The transfer is initiated with the falling edge of CTRL_LE; as long as CTRL_LE is high, no data can be transferred. During CTRL_LE, low data can be written. The data has to be applied at CTRL_DATA and has to be stable before the rising edge of CTRL_CLK. The transmission is finished by a rising edge of CTRL_LE. With the rising edge of CTRL_LE, the new word is asynchronously transferred to the internal register (e.g., N, M, P, .). Each word has to be separately transmitted by this procedure. t4 t3 CTRL_CLK th2 tsu1 CTRL_DATA Bit31 (MSB) Bit30 Bit2 Bit1 Bit0 t7 CTRL_LE tsu5 tsu6 T0061-01 T0061-01 Figure 14. Timing Diagram SPI Control Interface The SPI serial protocol accepts word Write operation only. There is neither a read, acknowledge, nor a handshake operation. The following four words include the register settings of the programmable functions of the CDCM7005 CDCM7005. It can be modified to the customer application by changing one or more bits. It comes up with a default register setting after power up or if the power down (PD) control signal is applied. The default setting is shown in column five of the following words. A low active function is shown as [0] and a high active function is shown as [1]. 16 Submit Documentation Feedback Copyright © 2005­2007, Texas Instruments Incorporated Product Folder Link(s) :CDCM7005 CDCM7005 CDCM7005 CDCM7005 www.ti.com SCAS793C SCAS793C ­ JUNE 2005 ­ REVISED DECEMBER 2007 PARAMETER MEASUREMENT INFORMATION (continued) Word 0 BIT BIT NAME POWER UP CONDITION DESCRIPTION/FUNCTION 0 C0 Register Selection C1 Register Selection M0 Reference Divider M Bit 0 1 3 M1 Reference Divider M Bit 1 1 4 M2 Reference Divider M Bit 2 1 5 M3 Reference Divider M Bit 3 1 6 M4 Reference Divider M Bit 4 1 7 M5 Reference Divider M Bit 5 1 8 M6 Reference Divider M Bit 6 QFN 0 2 BGA 0 1 PIN AFFECTED 1 Reference Divider M 9 M7 Reference Divider M Bit 7 0 10 M8 Reference Divider M Bit 8 0 11 M9 Reference Divider M Bit 9 0 12 VCXO Divider N Bit 0 1 N1 VCXO Divider N Bit 1 1 14 N2 VCXO Divider N Bit 2 1 15 N3 VCXO Divider N Bit 3 1 16 N4 VCXO Divider N Bit 4 1 17 N5 VCXO Divider N Bit 5 1 18 N6 VCXO Divider N Bit 6 1 19 N7 VCXO Divider N Bit 7 0 20 N8 VCXO Divider N Bit 8 0 21 N9 VCXO Divider N Bit 9 0 22 N10 VCXO Divider N Bit 10 0 23 N11 VCXO Divider N Bit 11 0 24 DLYM0 Reference Phase Delay M Bit 0 0 25 DLYM1 Reference Phase Delay M Bit 1 0 26 DLYM2 Reference Phase Delay M Bit 2 0 27 DLYN0 Feedback Phase Delay N Bit 0 0 28 DLYN1 Feedback Phase Delay N Bit 1 0 29 DLYN2 Feedback Phase Delay N Bit 2 0 30 MANAUT Manual or Auto Ref. Manual Reference Clock Selection [0] Automatic Reference Clock Selection [1] 0 A1, B1 36, 37 31 (2) N0 13 (1) VC(X)O Divider N (1) REFDEC Freq. Detect Reference Frequency Detection on [0], off [1] 0 C8 23 Progr. Delay M Progr. Delay N (2) The frequency applied to the Divider N must be smaller than 300 MHz. A sufficient P Divider must be selected with the FB_MUX to maintain this criteria. If set to low, STATUS_REF will be in normal operation. If set to high, STATUS_REF will be high, even if no valid clock is detected ( primary clock is selected REF_SEL [0] -> secondary clock is selected In the automatic mode, the primary clock is selected by default even if both clocks are available. In case the primary clock is not available or fails, then the input switches to the secondary clock as long until the primary clock is back. Figure 15 shows the automatic clock selection. 1 PRI_REF SEC_REF 1 2 3 4 2 Internal Reference Clock STATUS_REF PRI_SEC_CLK Primary Clock Secondary Clock Primary Clock T0062-01 T0062-01 NOTE: PRI_REF is the preferred clock input. Figure 15. Behavior of STATUS_REF and PRI_SEC_CLK In the automatic mode, the frequencies of both clock signals have to be similar, but may differ by up to 20%. The phase of the clock signal can be any. The clock input circuitry is design to suppress glitches during switching between the primary and secondary clock in the manual and automatic mode. This avoids an undefined switching of the following circuitries. The phase of the output clock slowly follows the new input phase. There will be no phase-jump at the output. How quick the phase adjustment is done depends on the selected loop parameter, i.e., at a loop bandwidth of