SCAA100 CDCM61001 CDCM61002 CDCM61004 E5052A - Datasheet Archive

 

SCAA100 ­ February 2009 Ethernet Clock Generation Using the CDCM6100x Firoj Kabir and Johnny Lau . ICP - Clock

 

Application Report SCAA100 SCAA100 ­ February 2009 Ethernet Clock Generation Using the CDCM6100x Firoj Kabir and Johnny Lau . ICP - Clock Distribution Circuits ABSTRACT This application report is a guide for using Texas Instruments CDCM6100x in an Ethernet LAN and WAN application as a clock distributor and clock synthesizer along with measured jitter performance results. Background Today's networking boxes require clock generation and buffering. Traditional methods involved a clock oscillator and a clock buffer. For LAN applications, a typical 156.25-MHz clock is needed, and for WAN applications a 155.52-MHz clock is used. Due to the low jitter and accuracy needed for these clock oscillators, their cost are high. So how does a designer lower cost but maintain low jitter, high accuracy, and clock buffering in a single solution? The CDCM6100x answers this question. Functional Description The CDCM6100x is a highly versatile, low-jitter frequency synthesizer which can generate low-jitter clock outputs, selectable among LVPECL, LVDS, or LVCMOS, from a low- frequency crystal or LVCMOS input for a variety of wireline and data communication applications. The CDCM6100x features an on-chip PLL that can be easily configured solely through control pins. The overall output jitter performance is less than 1 ps, rms or 35 ps, pk-pk, thus making the device a perfect choice for use in demanding applications like SONET, Ethernet, Fibre Channel, and SAN. The CDCM6100x is packaged in a small 32-pin, 5-mm × 5-mm QFN package. The CDCM6100x is available in one-, two-, and four- output versions. Output Divider CDCM61001 CDCM61001 Osc/ PLL Prescaler XTAL/ LVCMOS CDCM61002 CDCM61002 CDCM61004 CDCM61004 PR[1,0] OD[2,0] LVPECL/ LVDS/ LVCMOS Figure 1. CDCM6100x Functional Block Diagram SCAA100 SCAA100 ­ February 2009 Submit Documentation Feedback Ethernet Clock Generation Using the CDCM6100x 1 Application www.ti.com Application Today's networking LAN and WAN clocking require low jitter (typ < 1ps rms or lower). Typical clock speeds for LAN applications are 625 MHz, 312.5 MHz, 156.25 MHz, and 125 MHz. For WAN applications, 622.08 MHz, 311.04 MHz, 155.52 MHz, and 77.76 MHz are commonly used. For both LAN and WAN systems, the output signal type needed can be differential (LVPECL or LVDS) or single-ended 3.3-V LVCMOS. This application report demonstrates solutions that can meet these needs while also offering a lower cost solution to today's high priced oscillators and clock buffers. Test Equipment and Setup All the measurements discussed in this application report were taken under normal operating conditions using a 3.3-V power supply and at room temperature. Equipment used: · Agilent E5052A E5052A Signal Source Analyzer · Power supply · CDCM6100x EVM Block Diagram and Jitter Test Results of LAN Solutions The following four solutions show how to generate networking LAN clocks from the CDCM6100x devices and a low-cost, standard 25-MHz crystal. The 25 MHz is fed into the CDCM6100x VCO core to generate a 625-MHz, 312.5-MHz, 156.25-MHz, or a 125-MHz frequency available to the output buffer. The output signal type can be native LVPECL, LVDS, or LVCMOS. These examples select LVPECL for the output buffers, but also included are some LVDS and LVCMOS measurements at the end of this applications report. LAN Solution 1 Block Diagram: This solution uses the one-output version CDCM61001 CDCM61001 to generate 625 MHz. If more outputs are needed, the CDCM61002 CDCM61002 and CDCM61004 CDCM61004 can supply two or four outputs, respectively. CDCM61001 CDCM61001 25 MHz Low Jitter Clock Synthesizer 625 MHz Figure 2. LAN Block Diagram 1 2 Ethernet Clock Generation Using the CDCM6100x SCAA100 SCAA100 ­ February 2009 Submit Documentation Feedback LAN Solution 1 Jitter Test Results: www.ti.com LAN Solution 1 Jitter Test Results: OUT_0 = 625-MHz LVPEL ­ RMS Jitter is 494 sec (10 kHz­20 MHz) LAN Solution 2 Block Diagram This solution uses the one output version CDCM61001 CDCM61001 to generate 312.5 MHz. If more outputs are needed, the CDCM61002 CDCM61002 and CDCM61004 CDCM61004 can supply two or four outputs, respectively CDCM 61001 25 MHz 312.5 MHz Low Jitter Clock Synthesizer Figure 3. LAN Block Diagram 2 SCAA100 SCAA100 ­ February 2009 Submit Documentation Feedback Ethernet Clock Generation Using the CDCM6100x 3 LAN Solution 2 Jitter Test Results: www.ti.com LAN Solution 2 Jitter Test Results: OUT_0 = 312.5-MHz LVPEL ­ RMS Jitter is 470 sec (10 kHz­20 MHz) LAN Solution 3 Block Diagram: This solution uses the two-output version CDCM61002 CDCM61002 to generate two copies of 156.25 MHz. If more or less outputs are needed, the CDCM61001 CDCM61001 and CDCM61004 CDCM61004 can supply one or four outputs, respectively. CDCM 61002 25 MHz 156.25 MHz Low Jitter Clock Synthesizer 156.25 MHz Figure 4. LAN Block Diagram 3 4 Ethernet Clock Generation Using the CDCM6100x SCAA100 SCAA100 ­ February 2009 Submit Documentation Feedback LAN Solution 3 Jitter Test Results: www.ti.com LAN Solution 3 Jitter Test Results: OUT_0 = 156.25-MHz LVPEL ­ RMS Jitter is 477 sec (10 kHz­20 MHz) SCAA100 SCAA100 ­ February 2009 Submit Documentation Feedback Ethernet Clock Generation Using the CDCM6100x 5 OUT_1 = 156.25-MHz LVPEL ­ RMS Jitter is 476 sec (10 kHz­20 MHz) www.ti.com OUT_1 = 156.25-MHz LVPEL ­ RMS Jitter is 476 sec (10 kHz­20 MHz) LAN Solution 4 Block Diagram: This solution uses the four-output version CDCM61004 CDCM61004 to generate four copies of 125 MHz. If less outputs are needed, the CDCM61001 CDCM61001 and CDCM61002 CDCM61002 can supply one or two outputs, respectively. 125 MHz 25 MHz CDCM61004 CDCM61004 125 MHz Low Jitter Clock Synthesizer 125 MHz 125 MHz Figure 5. LAN Block Diagram 4 6 Ethernet Clock Generation Using the CDCM6100x SCAA100 SCAA100 ­ February 2009 Submit Documentation Feedback LAN Solution 4 Jitter Test Results: www.ti.com LAN Solution 4 Jitter Test Results: OUT_0 = 125-MHz LVPECL ­ RMS Jitter is 551 sec (10 kHz­20 MHz) SCAA100 SCAA100 ­ February 2009 Submit Documentation Feedback Ethernet Clock Generation Using the CDCM6100x 7 OUT_1 = 125-MHz LVPECL ­ RMS Jitter is 551 sec (10 kHz­20MHz) www.ti.com OUT_1 = 125-MHz LVPECL ­ RMS Jitter is 551 sec (10 kHz­20MHz) 8 Ethernet Clock Generation Using the CDCM6100x SCAA100 SCAA100 ­ February 2009 Submit Documentation Feedback www.ti.com OUT_2 = 125-MHz LVPECL ­ RMS Jitter is 551 sec (10 kHz­20 MHz) OUT_2 = 125-MHz LVPECL ­ RMS Jitter is 551 sec (10 kHz­20 MHz) SCAA100 SCAA100 ­ February 2009 Submit Documentation Feedback Ethernet Clock Generation Using the CDCM6100x 9 OUT_3 = 125-MHz LVPECL ­ RMS Jitter is 553 sec (10 kHz­20 MHz) www.ti.com OUT_3 = 125-MHz LVPECL ­ RMS Jitter is 553 sec (10 kHz­20 MHz) Block Diagram and Jitter Test Results of WAN Solutions The following four solutions show how to generate networking WAN clocks from the CDCM6100x devices and a low-cost, standard 24.8832-MHz crystal. The 24.8832 MHz is fed into the CDCM6100x VCO core to generate a 622.08-MHz, 311-04 MHz, 155-52 MHz, or 77.76-MHz frequency available to the output buffer. The output signal type can be native LVPECL, LVDS, or LVCMOS. These examples select LVPECL for the output buffers. WAN Solution 1 Block Diagram: This solution uses the one output version CDCM61001 CDCM61001 to generate 622.08 MHz. If more outputs are needed, the CDCM61002 CDCM61002 and CDCM61004 CDCM61004 can supply two or four outputs, respectively. CDCM61001 CDCM61001 24.8832 MHz Low Jitter Clock Synthesizer 622.08 MHz Figure 6. WAN Block Diagram 1 10 Ethernet Clock Generation Using the CDCM6100x SCAA100 SCAA100 ­ February 2009 Submit Documentation Feedback WAN Solution 1 Jitter Test Results: www.ti.com WAN Solution 1 Jitter Test Results: OUT_0 = 622.08-MHz LVPECL ­ RMS Jitter is 504 sec (10 kHz­20 MHz) WAN Solution 2 Block Diagram: This solution uses the one-output version CDCM61001 CDCM61001 to generate 311.04 MHz. If more outputs are needed, the CDCM61002 CDCM61002 and CDCM61004 CDCM61004 can supply two or four outputs, respectively. CDCM 61001 24.8832 MHz 311.04 MHz Low Jitter Clock Synthesizer Figure 7. WAN Block Diagram 2 SCAA100 SCAA100 ­ February 2009 Submit Documentation Feedback Ethernet Clock Generation Using the CDCM6100x 11 WAN Solution 2 Jitter Test Results: www.ti.com WAN Solution 2 Jitter Test Results: OUT_0 = 311.04-MHz LVPECL ­ RMS Jitter is 486 sec (10 kHz­20 MHz) WAN Solution 3 Block Diagram: This solution uses the two-output version CDCM61002 CDCM61002 to generate two copies of 155.22 MHz. If more or less outputs are needed, the CDCM61001 CDCM61001 and CDCM61004 CDCM61004 can supply one or four outputs, respectively. CDCM 61002 24.8832 MHz 155.52 MHz Low Jitter Clock Synthesizer 155.52 MHz Figure 8. WAN Block Diagram 3 12 Ethernet Clock Generation Using the CDCM6100x SCAA100 SCAA100 ­ February 2009 Submit Documentation Feedback www.ti.com WAN Solution 3 Jitter Test Results: WAN Solution 3 Jitter Test Results: OUT_0 = 155.52-MHz LVPECL ­ RMS Jitter is 489 sec (10 kHz­20 MHz) SCAA100 SCAA100 ­ February 2009 Submit Documentation Feedback Ethernet Clock Generation Using the CDCM6100x 13 OUT_1 = 155.52-MHz LVPECL ­ RMS Jitter is 488 sec (10 kHz­20 MHz) www.ti.com OUT_1 = 155.52-MHz LVPECL ­ RMS Jitter is 488 sec (10 kHz­20 MHz) WAN Solution 4 Block Diagram: This solution uses the four-output version CDCM61004 CDCM61004 to generate four copies of 77.76 MHz. If less outputs are needed, the CDCM61001 CDCM61001 and CDCM61002 CDCM61002 can supply one or two outputs, respectively. 77.76 MHz 24.8832 MHz CDCM61004 CDCM61004 77.76 MHz Low Jitter Clock Synthesizer 77.76 MHz 77.76 MHz Figure 9. WAN Block Diagram 4 14 Ethernet Clock Generation Using the CDCM6100x SCAA100 SCAA100 ­ February 2009 Submit Documentation Feedback www.ti.com WAN Solution 4 Jitter Test Results: WAN Solution 4 Jitter Test Results: OUT_0 = 77.76-MHz LVPECL ­ RMS Jitter is 535 sec (10 kHz­20 MHz) SCAA100 SCAA100 ­ February 2009 Submit Documentation Feedback Ethernet Clock Generation Using the CDCM6100x 15 OUT_1 = 77.76-MHz LVPECL ­ RMS Jitter is 533 fsec (10 kHz­20 MHz) www.ti.com OUT_1 = 77.76-MHz LVPECL ­ RMS Jitter is 533 fsec (10 kHz­20 MHz) 16 Ethernet Clock Generation Using the CDCM6100x SCAA100 SCAA100 ­ February 2009 Submit Documentation Feedback www.ti.com OUT_2 = 77.76-MHz LVPECL ­ RMS Jitter is 537 sec (10 kHz­20 MHz) OUT_2 = 77.76-MHz LVPECL ­ RMS Jitter is 537 sec (10 kHz­20 MHz) SCAA100 SCAA100 ­ February 2009 Submit Documentation Feedback Ethernet Clock Generation Using the CDCM6100x 17 OUT_3 = 77.76-MHz LVPECL ­ RMS Jitter is 533 sec (10 kHz­20 MHz) www.ti.com OUT_3 = 77.76-MHz LVPECL ­ RMS Jitter is 533 sec (10 kHz­20 MHz) Performance Summary LAN Configurations Performance results of this LAN configuration are: 1. CDCM61001 CDCM61001 = 625 MHz OUT_0 = 625-MHz LVPEL ­ RMS Jitter is 494 sec (10 kHz­0 MHz) 2. CDCM61001 CDCM61001 = 312.5 MHz OUT_0 = 312.5-MHz LVPEL ­ RMS Jitter is 470 sec (10 kHz­20 MHz) 3. CDCM61002 CDCM61002 = 2 × 156.25 MHz OUT_0 = 156.25-MHz LVPEL ­ RMS Jitter is 477 sec (10 kHz­20 MHz) OUT_1 = 156.25-MHz LVPEL ­ RMS Jitter is 476 sec (10 kHz­20 MHz) 4. CDCM61004 CDCM61004 = 4 × 125 MHz OUT_0 = 125-MHz LVPECL ­ RMS Jitter is 551 sec (10 kHz­20 MHz) OUT_1 = 125-MHz LVPECL ­ RMS Jitter is 551sec (10 kHz­20MHz) OUT_2 = 125-MHz LVPECL ­ RMS Jitter is 551 sec (10 kHz­20 MHz) OUT_3 = 125-MHz LVPECL ­ RMS Jitter is 553 sec (10 kHz­20 MHz) WAN Configurations Performance results of this WAN configuration are: 1. CDCM61001 CDCM61001 = 622.08 MHz OUT_0 = 622.08-MHz LVPECL ­ RMS Jitter is 504 sec (10 kHz­20 MHz) 2. CDCM61001 CDCM61001 = 311.04 MHz OUT_0 = 311.04-MHz LVPECL ­ RMS Jitter is 486 sec (10 kHz­20 MHz) 3. CDCM61002 CDCM61002 = 2 × 155.52 MHz 18 Ethernet Clock Generation Using the CDCM6100x SCAA100 SCAA100 ­ February 2009 Submit Documentation Feedback Additional Data www.ti.com OUT_0 = 155.52-MHz LVPECL ­ RMS Jitter is 489 sec (10 kHz­20 MHz) OUT_1 = 155.52-MHz LVPECL ­ RMS Jitter is 488 sec (10 kHz­20 MHz) 4. CDCM61004 CDCM61004 = 4 × 77.76 MHz OUT_0 = 77.76-MHz LVPECL ­ RMS Jitter is 535 sec (10 kHz­20 MHz) OUT_1 = 77.76-MHz LVPECL ­ RMS Jitter is 533 sec (10 kHz­20 MHz) OUT_2 = 77.76-MHz LVPECL ­ RMS Jitter is 537 sec (10 kHz­20 MHz) OUT_3 = 77.76-MHz LVPECL ­ RMS Jitter is 533 sec (10 kHz­20 MHz) Additional Data As previously mentioned, the CDCM6100x output type can be configured to LVPECL, LVDS, or LVCMOS. The following are some additional jitter measurements with LVDS and LVCMOS outputs. 125-MHz LVDS ­ RMS Jitter is 555 sec (10 kHz­20 MHz) SCAA100 SCAA100 ­ February 2009 Submit Documentation Feedback Ethernet Clock Generation Using the CDCM6100x 19 125-MHz LVCMOS ­ RMS Jitter is 539 sec (10 kHz­20 MHz) www.ti.com 125-MHz LVCMOS ­ RMS Jitter is 539 sec (10 kHz­20 MHz) Crystal Bypassed Output The CDCM6100x also has a unique feature that is worth noting. The device includes a bypassed output of the crystal frequency that is LVCMOS. OSC_OUT is an LVCMOS output that can be used in test mode to monitor proper loading of the input crystal to achieve the necessary crystal frequency with least error. This bypassed output is only available when the main outputs are selected on the LVPECL level. The output buffer is disabled during VCO calibration and is enabled only after calibration is complete. A 25-MHz input crystal was used in these examples. RSTN PR[1.0] 2 OD[2.0] 3 CDCM61001 CDCM61001 Feedback Divider Prescaler VCO Output Divider PFD Charge Pump Loop Filter Crystal/ LVCMOS Output Driver LVPECL/ LVCMOS/ LVDS 3.3 V LVCMOS CE 20 Ethernet Clock Generation Using the CDCM6100x 2 OS[1.0] SCAA100 SCAA100 ­ February 2009 Submit Documentation Feedback www.ti.com 25-MHz LVCMOS ­ RMS Jitter is 249 sec (10 kHz­5 MHz) 25-MHz LVCMOS ­ RMS Jitter is 249 sec (10 kHz­5 MHz) Conclusion The CDCM6100x performance meets today's networking frequencies and low-jitter requirements