CDB4353 CS4353 CS8416 DS803DB2

Evaluation Board for the CS4353 Features Description Demonstrates Recommended Layout and Grounding Arrangements The CDB4353

CDB4353 CDB4353 Evaluation Board for the CS4353 CS4353 Features Description Demonstrates Recommended Layout and Grounding Arrangements The CDB4353 CDB4353 evaluation board is an excellent means for quickly evaluating the CS4353 CS4353 24-bit, high-performance stereo D/A converter. Evaluation requires an analog signal analyzer, a digital signal source, and a +3.3 V power supply. Analog line-level outputs are provided via RCA phono jacks. CS8416 CS8416 Receives S/PDIF, & EIAJ-340Compatible Digital Audio Headers for External PCM Audio Single-ended Stereo Analog Outputs Requires Only a Digital Signal Source and a +3.3 V Power Supply for a Complete Digital-toAnalog Converter System Configured by On-board Hardware Controls The CS8416 CS8416 digital audio receiver IC provides the system timing necessary to operate the Digital-to-Analog converter and will accept S/PDIF and EIAJ-340-compatible audio data. The evaluation board may also be configured to accept external timing and data signals for operation in a user application during system development. Power, Digital Source Select, and S/PDIF Error Indicator LEDs The CDB4353 CDB4353 is controlled by switches to select the digital signal source and configuration options for the CS4353 CS4353. Current sense resistors allow for easy power calculations during system development. Current Sense Resistors for CS4353 CS4353 Supplies (VA, VL, and VCP) ORDERING INFORMATION CDB4353 CDB4353 Evaluation Board Indicator LEDs +3.3V Power (Optional separate VL) PCM Input Optical S/PDIF Input PCM Clocks/Data PCM Clocks/Data PCM Mux and Level Shifter PCM Clocks/Data External System Connector AOUTA PCM Clocks/Data CS4353 CS4353 Analog Outputs AOUTB CS4353 CS4353 Settings CS8416 CS8416 S/PDIF Receiver CS8416 CS8416 serial port format Hardware Control Switches http://www.cirrus.com CS4353 CS4353 Reset CS8416 CS8416 Reset PCM source select Coaxial S/PDIF Input PCM Header S/PDIF Error S/PDIF or PCM Input Selected +3.3V power VL power Reset Circuit Copyright © Cirrus Logic, Inc. 2008 (All Rights Reserved) AUG '08 DS803DB2 DS803DB2 CDB4353 CDB4353 TABLE OF CONTENTS 1. CDB4353 CDB4353 SYSTEM OVERVIEW . 4 2. CS4353 CS4353 DIGITAL-TO-ANALOG CONVERTER . 4 3. CS8416 CS8416 DIGITAL AUDIO RECEIVER . 4 4. INPUT FOR CLOCKS AND DATA . 4 5. POWER SUPPLY CIRCUITRY . 5 6. GROUNDING AND POWER SUPPLY DECOUPLING . 5 7. HARDWARE CONTROL . 5 8. CS8416 CS8416 AND CS4353 CS4353 RESET . 5 9. ANALOG OUTPUT FILTERING . 5 10. BOARD CONNECTIONS AND SETTINGS . 6 11. PERFORMANCE PLOTS . 7 12. SCHEMATICS AND LAYOUT . 12 13. REVISION HISTORY . 18 LIST OF FIGURES Figure 1. FFT (48 kHz, 0 dB) . 7 Figure 2. FFT (48 kHz, -60 dB) . 7 Figure 3. FFT (48 kHz, No Input) . 7 Figure 4. FFT (48 kHz Out-of-Band, No Input) . 7 Figure 5. 48 kHz, THD+N vs. Input Freq . 7 Figure 6. 48 kHz, THD+N vs. Level . 7 Figure 7. 48 kHz, Fade-to-Noise Linearity . 8 Figure 8. 48 kHz, Frequency Response . 8 Figure 9. 48 kHz, Crosstalk . 8 Figure 10. 48 kHz, Impulse Response . 8 Figure 11. FFT (96 kHz, 0 dB) . 8 Figure 12. FFT (96 kHz, -60 dB) . 8 Figure 13. FFT (96 kHz, No Input) . 9 Figure 14. FFT (96 kHz Out-of-Band, No Input) . 9 Figure 15. 96 kHz, THD+N vs. Input Freq . 9 Figure 16. 96 kHz, THD+N vs. Level . 9 Figure 17. 96 kHz, Fade-to-Noise Linearity . 9 Figure 18. 96 kHz, Frequency Response . 9 Figure 19. 96 kHz, Crosstalk . 10 Figure 20. 96 kHz, Impulse Response . 10 Figure 21. FFT (192 kHz, 0 dB) . 10 Figure 22. FFT (192 kHz, -60 dB) . 10 Figure 23. FFT (192 kHz, No Input) . 10 Figure 24. FFT (192 kHz Out-of-Band, No Input) . 10 Figure 25. 192 kHz, THD+N vs. Input Freq . 11 Figure 26. 192 kHz, THD+N vs. Level . 11 Figure 27. 192 kHz, Fade-to-Noise Linearity . 11 Figure 28. 192 kHz, Frequency Response . 11 Figure 29. 192 kHz, Crosstalk . 11 Figure 30. 192 kHz, Impulse Response . 11 Figure 31. System Block Diagram and Signal Flow . 12 Figure 32. CS8416 CS8416 and CS4353 CS4353 . 13 Figure 33. HW Configuration, PCM Header, and Power . 14 Figure 34. Silkscreen Top . 15 Figure 35. Top Side . 16 Figure 36. Bottom Side . 17 2 DS803DB2 DS803DB2 CDB4353 CDB4353 LIST OF TABLES Table 1. Switch S1 Quick Setup . 5 Table 2. System Connections . 6 Table 3. CDB4353 CDB4353 Jumper Settings . 6 Table 4. CDB4353 CDB4353 Switch Settings . 6 DS803DB2 DS803DB2 3 CDB4353 CDB4353 1. CDB4353 CDB4353 SYSTEM OVERVIEW The CDB4353 CDB4353 evaluation board is an excellent means of quickly evaluating the CS4353 CS4353. The CS8416 CS8416 digital audio interface receiver provides an easy interface to digital audio signal sources, including the majority of digital audio test equipment. The evaluation board also allows the user to supply external PCM clocks and data through two separate header options for system development. Configuration of the CDB4353 CDB4353 can be modified through piano switch S1, see Table 4. The CDB4353 CDB4353 system block diagram and signal flow is shown in Figure 31, and the CDB4353 CDB4353 schematics are shown in Figures 32 and 33. 2. CS4353 CS4353 DIGITAL-to-ANALOG CONVERTER A description of the CS4353 CS4353 is included in the CS4353 CS4353 datasheet. 3. CS8416 CS8416 DIGITAL AUDIO RECEIVER The system receives and decodes the standard S/PDIF data format using a CS8416 CS8416 Digital Audio Receiver, Figure 32. The outputs of the CS8416 CS8416 include a serial bit clock, serial data, left-right clock, and a 128/256 Fs master clock. The operation of the CS8416 CS8416 and a discussion of the digital audio interface is included in the CS8416 CS8416 datasheet. The evaluation board has been designed such that the input can be either optical or coaxial, see Figure 32. However, both inputs cannot be driven simultaneously. Position 3 of piano switch S1 sets the CS8416 CS8416 output data format to either I²S (down) or LJ (up). Position 2 of S1 sets the output MCLK to LRCK ratio of the CS8416 CS8416. This switch should be set to 256 (down) for input Fs48 kHz. The CS8416 CS8416 must be manually reset via S2 after either switch has been toggled for the change to take effect. 4. INPUT FOR CLOCKS AND DATA The evaluation board has been designed to allow interfacing to external systems via headers J13 and J4. Header J13 allows the evaluation board to accept externally generated PCM clocks and data at a nominal voltage of 3.3 V. The PCM clocks and data are buffered, level-shifted to the VL supply, and then input to the CS4353 CS4353. The schematic for the clock/data input is shown in Figure 33. Position 1 of S1 selects the CS4353 CS4353 PCM source as either the CS8416 CS8416 (up) or header J13 (down). Note: If the VL supply is set to a low voltage level (VL