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Part Manufacturer Description Datasheet BUY
CD4050AFB Texas Instruments CMOS Hex Non-Inverting Buffer/Converter 16-CDIP -55 to 125 visit Texas Instruments
CD4050BDTG4 Texas Instruments 4000/14000/40000 SERIES, HEX 1-INPUT NON-INVERT GATE, PDSO16, GREEN, PLASTIC, MS-012AC, SOIC-16 visit Texas Instruments
CD4050BNSR Texas Instruments CMOS Hex Non-Inverting Buffer/Converter 16-SO -55 to 125 visit Texas Instruments Buy
CD4050BF3A Texas Instruments CMOS Hex Non-Inverting Buffer/Converter 16-CDIP -55 to 125 visit Texas Instruments
CD4050BD Texas Instruments CMOS Hex Non-Inverting Buffer/Converter 16-SOIC -55 to 125 visit Texas Instruments Buy
CD4050BDWE4 Texas Instruments 4000/14000/40000 SERIES, HEX 1-INPUT NON-INVERT GATE, PDSO16, GREEN, PLASTIC, SOIC-16 visit Texas Instruments

CD4050 pin diagram

Catalog Datasheet MFG & Type PDF Document Tags

CD4049 equivalent

Abstract: CD4049 ic 16 pin diagram CONTROL OUTPUT LOW DRIVE RTN FIGURE 1A. PW-83075P6 BLOCK DIAGRAM · Trapizodal or Sinusoidal , LO FIGURE 1B. PW-84075P6 BLOCK DIAGRAM REGEN STATUS OV AMP REGEN LOW REGEN TRIP ADJ , LOW DRIVE RTN FIGURE 1C. PW-85075P6 BLOCK DIAGRAM ADVANCED TABLE 1. PW-8X075P6 ABSOLUTE , . FUNCTIONAL AND PIN DESCRIPTIONS: (FOR PW-83075P6, PW-84075P6 AND PW-85075P6 UNLESS NOTED) SC FAULT The SC , drain to low within 6 µs. REGEN STATUS (APPLIES TO PW-85075P6 ONLY) The REGEN STATUS pin is
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PW-83075 PW-85075 CD4049 equivalent CD4049 ic 16 pin diagram cd4049 IRML2402 cd4050 cd4049 pin out PW-84075 1-800-DDC-5757 A5976

74HC597

Abstract: ADS1210 discusses the system block diagram and the circuit diagram. The software design discusses the data , program can be implemented to do the data acquisition using the ADS1210 demo board. PC PORT PIN NO , . The Pin Connection and the Function of the Connector J1. the PC is connected to the demo board by the connector J1. Table I shows the pin connection and the pin function of the connector J1. The PC , 32Kx24 Memory Figure 3 shows the circuit diagram of the memory management section. The PC sends the
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8XC51 74HC597 SEC100 74LS157 74LS240 AB-113 ADS1210/11 SBAA011

CD4050

Abstract: CD4050 pin diagram similar monolithic multiplying DAC's while retaining the industry 7500-Series pin compatibility. Tightly , -, 18-, or 20-pin ceramic packages for the 10-, 12-, and 14-bit versions respectively. Applications , binary models 16 kfl for bcd models INPUT/OUTPUT CONNECTIONS dac-ha12b, 1sd PIN FUNCTION 1 OUTPUT 1 , 10 BIT 7 in ii bits in 12 BIT 9 IN 13 BIT 10 (n (LSB) 14 + VDD 15 REFERENCE IN 16 FEEDBACK PIN FUNCTION PIN FUNCTION 1 output 1 1 output 1 2 output 2 2 output 2 3 ground 3 ground 4 bit 1 in (msb
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DAC-HA10BM DAC-HA12BC DAC-HA12DC DAC-HA14BC DAC-HA14BM DAC-HA12BC-1 CD4050 pin diagram CD4050 equivalent DAC with BCD inputs binary bcd conversion logic diagram 0D0021S 7500-S DAC-HA10BC DAC-HA10BR

cd4049a

Abstract: RE200 CD4050A are pin compatible with the CD4009A and CD4010A respectively, and can be substituted for these , and CD4050 have hlgh·to·low·level voltage conversion capability but not STATIC ELECTRICAL , . 21 ~uiescent device current test circuit. Fig. 22 - (a)Schematic diagram of C04049A, 1 6 identical units. (b) Schematic diagram of C04050A, 1 6 identical units. 0_ I 556
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cd4049a RE200 CD4050 pin function CD4049 PIN DIAGRAM Circuit CD4050 i C04049 CD4049A CD4049A- CD4050A-N CD4069 92CI-IO

CD4049 ic 16 pin diagram

Abstract: KA590 , or logic-level conversion applications. In these applications the CD4049A and CD4050A are pin , CD4049 and CD4050 have high-toiow level voltage conversion capability but no! low-to-high-leve I , )Schematic diagram of CD4Q49A, \ 6 identical units. (b) Schematic diagram of CD4050A, 6identical units. Fig
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KA590 CD4049 PIN DIAGRAM CD4069 CMOS hex inverter CD4050 ic 16 pin diagram CD4069 PIN DIAGRAM AND CD4049 HEX INVERTER CD4049A-CD4050A- ICS-204 CD40S0A 92CS-27400

cd4050

Abstract: 16 pin CD4050 pin configuration discusses the system block diagram and the circuit diagram. The software design discusses the data , program can be implemented to do the data acquisition using the ADS1210 demo board. PC PORT PIN NO , device U5 The data input from the ADS1210 demo board Not connected Ground TABLE I. The Pin , . Table I shows the pin connection and the pin function of the connector J1. The PC sends two kinds of , Figure 3 shows the circuit diagram of the memory management section. The PC sends the signal AUTOFEED to
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16 pin CD4050 pin configuration G2119 TCSS257 JP13 JP15 74LS240 PC AP10PC A37594

CD4049 PIN DIAGRAM

Abstract: CD4049 amplifier -83075P6 BLOCK DIAGRAM · Trapezoidal or Sinusoidal Compatible · DSP/Microprocessor Compatible · PW-83075P6 - , RPV's. 1 June 13, 2000 Data Device Corporation RSENSE- FIGURE 1B. PW-84075P6 BLOCK DIAGRAM , -85075P6 BLOCK DIAGRAM TABLE 1. PW-8X075P6 ABSOLUTE MAXIMUM RATINGS (TC = +25°C UNLESS OTHERWISE SPECIFIED , overvoltage condition has occurred. FUNCTIONAL AND PIN DESCRIPTIONS: (FOR PW-83075P6, PW-84075P6 AND PW , to the VREF pin to set the output voltage scale for I_VOUT. 50% LOWER 0.6 µs Min. 50% RSENSE
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CD4049 amplifier HA 131 50A 12 Vdc brush motor driver UC1625 application CD4049 application EM339

CD4049UB

Abstract: cd4050b CD4049UB and CD4050B are pin compatible with the CD4009UB and CD4010B respectively, and can be substituted , "sink" or "source" driver · COS/MOS high-to-Iow logic-level converter CD4049UB FUNCTIONAL DIAGRAM , VCC 18 18 "The CD4049 and CD4050 have h.gh·to-Iow-Ievel voltage convers.on c.opahol.ly hili I1ul , -4-_ _~_"" = Vss I b) vss 10) CD4050B FUNCTIONAL DIAGRAM Fig. 7-a) SchematiC diagram of CD4049UB, 7 of 6 Identical Units; b) Schematic dIagram of CD4050B, 7 of 6 Identical units. 194
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CD4049U kee2 CD4049UB- CD4050B-N RCA-CD4049UB 24480RI 24481RI

jd 1803

Abstract: CD4050 ic 16 pin diagram CD4049UB and CD4050B are pin compatible with the CD4009UB and CD4010B respectively, and can be substituted , VCC _'- VSS J- NC = I 5 NC - 16 CD4050B FUNCTIONAL DIAGRAM Features: â  High sink current , FUNCTIONAL DIAGRAM -0.5 to +20 V 0.5 to +20.5 V ±10 mA MAXIMUM RATINGS, Absolute-Maximum Values: DC , Voltage Range (V|fy|) vcc' 18 V The CD4049 and CD4050 have high-to-low-level vol tage conversion i.ip.iln , â'"at Schematic diagram of CD4049UB. 1 of 6 identical units; bj Schematic diagram of CD4050B, 1 of 6
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CD401 CD4069UB jd 1803 CD4049 ic 8 pin diagram pin diagram of CD4050B IC CD4049 CD40S0B CD4049UB-I CS-20M 92CM-33556 372-L574

M917

Abstract: cd4050 -917 Receiver Figure 2 Block Diagram Teltone Corporation/10801.120th Avenue NE.WrMand.WA 98033 Phone , connect L C to G R D (Pin 18 to Pin 15). Disconnect D T M F inputs if rotary dial counting only is desired , analogous device to convey information. Installation Data Mounting pin assignments and dimensions for , ALL OUTPUTS CD4050 CD4049 (CMOS) o TTL/CMOS +5V Relative humidity limits 0 to 85% Meets
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M917 Teltone m-917 rotary decoder CS 213 M-917 D0D151S

CD4049 ic 16 pin diagram

Abstract: CD4050 ic 16 pin diagram , or logic-level conversion applications. In these applications the CD4049A and CD4050A are pin , Voltage Range (V|) vCc" 12 V The CD4049 and CD4050 have high-toiow level voltage conversion capability , . 20â'"Input leakage current test circuit. Fig. 22 - (a)Schematic diagram of CD4049A, 1 6 identical units. (b) Schematic diagram of CD4050A, 6 identical units. Fig. 21â'"Quiescent device current test
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schematic diagram inverter 72 volt input TEA1043 cmos ic cd4049 IC CD4050 pin diagram of ic cd4069 MCS-20S24 92CS-204 92CS-2092

CD4050 equivalent

Abstract: resolver sensor DRIVE VBUS- FIGURE 1A. PW-83075P6 BLOCK DIAGRAM · Trapezoidal or Sinusoidal Compatible · DSP , 's. © 2001 Data Device Corporation RSENSE- FIGURE 1B. PW-84075P6 BLOCK DIAGRAM REGEN STATUS VBUS+ OV , DIAGRAM TABLE 1. PW-8X075P6 ABSOLUTE MAXIMUM RATINGS PARAMETER Drive Supply Voltage Logic Power-In , applied to the output pin. When a short circuit condition is detected, the output transistor is shut down , (L) indicating an overvoltage condition is occurring. FUNCTIONAL AND PIN DESCRIPTIONS: (FOR PW
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resolver sensor amplifier using lm741 LS132

CD4049 PIN DIAGRAM

Abstract: CD4049 equivalent OUTPUT LOW DRIVE VBUS- FIGURE 1A. PW-83075P6 BLOCK DIAGRAM · Trapezoidal or Sinusoidal , RSENSE- FIGURE 1B. PW-84075P6 BLOCK DIAGRAM REGEN STATUS VBUS+ OV ADJ REGEN BUSSLEEP MODE POWER , OUTPUT LOW DRIVE VBUS- FIGURE 1C. PW-85075P6 BLOCK DIAGRAM PRELIMINARY TABLE 1. PW , overvoltage condition has occurred. FUNCTIONAL AND PIN DESCRIPTIONS: (FOR PW-83075P6, PW-84075P6 AND PW , -85075P6 ONLY) The REGEN STATUS pin is referenced to REGEN BUS-. It indicates the state of the regen clamp
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3 phase induction motor fpga 60v 50a dc motor controller circuit HC 148 TRANSISTOR radar position control servo motor EL2009

CD4049 ic 8 pin diagram

Abstract: CD4049 ic 16 pin diagram . Connect the converter as shown in the Connection Diagram. Use the Input Pin Connections table for the , (Pin 23) and Digital Ground (Pin 22) are not connected internally and must be tied together externally , MODE (Pin 17) to V dd (Pin 18). In this continuous power mode, an A/D conversion will take place when a 5 microseconds or greater positive go ing pulse is applied to START CONVERT (Pin 21). For single supply operation (interrupt power mode), tie Power Mode (Pin 17) to E.O.C. (Pin 16). When EOC goes low
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intersil im6100 IM6100 ADC-HC12BMC ADC-HC12BMM ADC-HC12BMM-QL 02048-1194/TEL 339-3000/TLX

CD4049 ic 16 pin diagram

Abstract: CD4050 ic 16 pin diagram the Connection Diagram. Use the Input Pin Connections table for the desired input voltage range. Apply , . Analog Common (Pin 23) and Digital Ground (Pin 22) are not connected internally and must be tied together , POWER MODE (Pin 17) to Vdd (Pin 18). In this continuous power mode, an AID conversion will take place when a 5 microseconds or greater positive going pulse is applied to START CONVERT (Pin 21). For single supply operation (interrupt power mode), tie Power Mode (Pin 17) to E.O.C. (Pin 16). When EOC goes low
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ADC-HC12B specifications of CD4050 ic 16 pin diagram CD4049 ic not gate 16 pin diagram TRIMMING POTENTIOMETER 10k ttl to cmos converter 339-3000ATLX 174388/FAX

CD4049 PIN DIAGRAM

Abstract: CD4049 ic not gate 16 pin diagram signal noise. Analog Common (Pin 23) and Digital Ground (Pin 22) are not connected internally and must be , dual supplies, tie POWER MODE (Pin 17) to Vdd (Pin 18). In this continuous power mode, an AID , (Pin 21). For single supply operation (interrupt power mode), tie Power Mode (Pin 17) to E.O.C. (Pin 16 , receipt of a 50 microseconds minimum, 500 microseconds maximum pulse on START CONVERT (Pin 21), the , transferred into latches during a logic "1" to logic "0" transition of the EOC line. Serial data out (Pin 14
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RCA 1802 DATEL INTERSIL 00012 4292 A15V DS-0161A

CD4049 PIN DIAGRAM

Abstract: CD4049 ic 16 pin diagram Figure 1 Pin Diagram VOLTAGE HYSTERESIS CIRCUIT INPUTS mru (TONE I INPUTS I F * CLOCK SQUARE WAVE , Van â  VS5(+) 'I 18 _15_ 7 a _10. 11 U-967 (28-PIN) RECEIVER 21 2 _13_ 4 , Figure 4 Block Diagram Table 1 Absolute Maximum Ratings (Note 1) 28 14 26 25 24 23 19 18 BD , Voltage on Any Pin .(V2 + 0.3 V) to (Vi - 0.3V , Respective Manufacturer M-967 Table 2 Pin Functions Pin Number Function Description 1 Vss Positive
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CD4049 pin configuration 16 pin CD4049 pin configuration 567 tone bd 426 transistor fp 1016 447KHZ 28-PIN

84256c

Abstract: DEM-ADS1210 ADS1212 are 18-pin devices and the ADS1211 and ADS1213 are 24-pin devices, care must be taken to orient the ADS1210 and ADS1212 devices correctly. Place pin 9 of the ADS1210 or ADS1212 in the lower left-hand corner or pin 12 (DGND) of the DUT socket. The only necessary hardware connections to the , IBM-PC is made with a 25-pin ribbon cable to an unused parallel port. If the computer does not have two , Positive Negative Positive Negative Positive Negative Positive Negative INPUT PIN JUMPER
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ADS1211P CSC10A01103G 1280B-1 84256c DEM-ADS1210 what is IC 74LS373 IC 74ls373 S87C51FA-4N40 DEM-ADS1210/11 ADS121X ADS1213P 84256C-10LP-SK CD4050BC

TCI 550 antenna

Abstract: 3 phase induction motor fpga DRIVE VBUS- FIGURE 1A. PW-83075P6 BLOCK DIAGRAM · Trapezoidal or Sinusoidal Compatible · DSP , Device Corporation RSENSE- FIGURE 1B. PW-84075P6 BLOCK DIAGRAM REGEN STATUS OV ADJ OV ADJ HIGH OV , -85075P6 BLOCK DIAGRAM TABLE 1. PW-8X075P6 ABSOLUTE MAXIMUM RATINGS PARAMETER Drive Supply Voltage Logic , from a short circuit applied to the output pin. When a short circuit condition is detected, the output , . VIRSENSE (OUTPUT) (APPLIES TO PW-84075P6 ONLY) The voltage on the VIRsense pin represents current passing
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TCI 550 antenna

IC CD4050

Abstract: PW-82351 FIGURE 1. PW-82351P6 BLOCK DIAGRAM © 1998, 1999 Data Device Corporation 1 TABLE 1. PW , . BRAKE The BRAKE input controls dynamic braking of the motor. A logic `1' at this pin will select the , required, the disable input and the UMC input can be used. INPUT SEL The input select pin (INPUT SEL , individual output transistor control. The input select pin is a logic high input. UNDER VOLTAGE FLAG (UV , OUT FIGURE 5. PW-82351 INPUT TIMING DIAGRAM 8 POWER ON SEQUENCE When power is applied, the
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1 Phase PWM Motor drive ic 3-Phase PWM Motor drive ic IC lm741 82351 J31 transistor B-06/99-500
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