NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
CD4015BC CD4015BCM MS-012 CD4015BCN MS-001 DS005948 - Datasheet Archive
CD4015BC Dual 4-Bit Static Shift Register General Description Features The CD4015BC contains two identical, 4-stage,
Revised January 1999 CD4015BC CD4015BC Dual 4-Bit Static Shift Register General Description Features The CD4015BC CD4015BC contains two identical, 4-stage, serialinput/parallel-output registers with independent "Data", "Clock," and "Reset" inputs. The logic level present at the input of each stage is transferred to the output of that stage at each positive-going clock transition. A logic high on the "Reset" input resets all four stages covered by that input. All inputs are protected from static discharge by a series resistor and diode clamps to VDD and VSS. s Wide supply voltage range: s High noise immunity: 3.0V to 18V 0.45 VDD (typ.) s Low power TTL: Fan out of 2 driving 74L compatibility: or 1 driving 74LS s Medium speed operation: 8 MHz (typ.) clock rate s Fully static design: @VDD - VSS = 10V Applications · Serial-input/parallel-output data queueing · Serial to parallel data conversion · General purpose register Ordering Code: Order Number Package Number Package Description CD4015BCM CD4015BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012 MS-012, 0.150" Narrow CD4015BCN CD4015BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001 MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Connection Diagram Truth Table Pin Assignments for DIP and SOIC CL (Note 1) X D R Q1 Qn 0 0 0 Qn-1 1 0 1 Qn-1 X 0 Q1 Qn X 1 0 0 (No change) X = Don't Care Case Note 1: Level Change © 1999 Fairchild Semiconductor Corporation DS005948 DS005948.prf www.fairchildsemi.com CD4015BC CD4015BC Dual 4-Bit Static Shift Register October 1987 CD4015BC CD4015BC Logic Diagrams Terminal No. 16 = VDD Terminal No. 8 = GND www.fairchildsemi.com 2 Recommended Operating Conditions -0.5 to +18 VDC DC Supply Voltage (VDD) Storage Temperature Range (TS) Input Voltage (VIN) -65°C to +150°C 500 mW Lead Temperature (TL) (Soldering, 10 seconds) -40°C to +85°C Note 2: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The tables of "Recommended Operating Conditions" and "Electrical Characteristics" provide conditions for actual device operation. 700 mW Small Outline 0 to VDD VDC Operating Temperature Range (TA) Power Dissipation (PD) Dual-In-Line +3 to +15 VDC DC Supply Voltage (VDD) -0.5 to VDD +0.5 VDC Input Voltage (VIN) Note 3: VSS = 0V unless otherwise specified. 260°C DC Electrical Characteristics (Note 3) Symbol Parameter -40°C Conditions Min Max +25°C Min +85°C Typ Max Min Max Units Quiescent Device VDD = 5V, VIN = VDD or VSS 20 0.005 20 150 µA Current VDD = 10V, VIN = VDD or VSS 40 0.010 40 300 µA VDD = 15V, VIN = VDD or VSS IDD 80 0.015 80 600 µA LOW Level VDD = 5V 0.05 0 0.05 0.05 V Output Voltage VOL VDD = 10V 0.05 0 0.05 0.05 V 0 0.05 VDD = 15V VOH HIGH Level 0.05 VDD = 5V 4.95 4.95 5 0.05 4.95 V V VDD = 10V 9.95 9.95 10 9.95 V VDD = 15V Output Voltage 14.95 14.95 15 14.95 V LOW Level VDD = 5V, VO = 0.5V or 4.5V 1.5 2.25 1.5 1.5 V Input Voltage VIL VDD = 10V, VO = 1.0V or 9.0V 3.0 4.50 3.0 3.0 V 6.75 4.0 VDD = 15V, VO = 1.5V or 13.5V 4.0 4.0 V VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1.0V or 9.0V 7.0 7.0 5.50 7.0 V VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 8.25 11.0 V LOW Level Output VDD = 5V, VO = 0.4V 0.52 0.44 0.88 0.36 mA Current (Note 4) IOL HIGH Level Input Voltage VIH VDD = 10V, VO = 0.5V 1.3 1.1 2.25 0.9 mA mA 3.5 3.5 2.75 3.5 V VDD = 15V, VO = 1.5V 3.0 8.8 2.4 VDD = 5V, VO = 4.6V -0.52 -0.44 -0.88 -0.36 mA VDD = 10V, VO = 9.5V -1.3 -1.1 -2.25 -0.9 mA VDD = 15V, VO = 13.5V -3.6 Input Current VDD = 15V, VIN = 0V -0.3 -10-5 -0.3 -1.0 µA VDD = 15V, VIN = 15V IIN 3.6 HIGH Level Output Current (Note 4) IOH 0.3 10-5 0.3 1.0 µA -3.0 -8.8 -2.4 mA Note 4: IOH and IOL are tested one output at a time. 3 www.fairchildsemi.com CD4015BC CD4015BC Absolute Maximum Ratings(Note 2) (Note 3) CD4015BC CD4015BC AC Electrical Characteristics (Note 5) TA= 25°C, CL= 50 pF, RL= 200k, tr = tf = 20 ns, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units CLOCK OPERATION 350 ns 80 160 ns 60 120 ns VDD = 5V 100 200 ns VDD = 10V 50 100 ns VDD = 15V 40 80 ns Minimum Clock VDD = 5V 160 250 ns Pulse-Width VDD = 10V 60 110 ns VDD = 15V tWL, tWM 230 VDD = 15V tTHL, tTLH VDD = 5V VDD = 10V tPHL, tPLH 50 85 ns Propagation Delay Time Transition Time Clock Rise and VDD = 5V 15 µs Fall Time VDD = 10V 15 µs VDD = 15V trCL, tfCL 15 µs Minimum Data VDD = 5V 50 100 µs Set-Up Time VDD = 10V 20 40 µs VDD = 15V tSU 15 30 VDD = 5V 2 VDD = 10V VDD = 15V CIN Maximum Clock Frequency fCL Input Capacitance µs 3.5 MHz 4.5 8 MHz 6 11 MHz Clock Input 7.5 10 pF Other Inputs 5 7.5 pF ns RESET OPERATION 200 400 100 200 ns VDD = 15V 80 160 ns Minimum Reset VDD = 5V 135 250 ns Pulse Width VDD = 10V 40 80 ns VDD = 15V tWH(R) VDD = 5V VDD = 10V tPHL(R) 30 60 ns Propagation Delay Time Note 5: AC Parameters are guaranteed by DC correlated testing. www.fairchildsemi.com 4 CD4015BC CD4015BC Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012 MS-012, 0.150" Narrow Package Number M16A 5 www.fairchildsemi.com CD4015BC CD4015BC Dual 4-Bit Static Shift Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001 MS-001, 0.300" Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.