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DC392A-A Linear Technology LTC1628 or LTC3728 Evaluation Kit visit Linear Technology - Now Part of Analog Devices
DC392A-C Linear Technology LTC1628 or LTC3728 Evaluation Kit visit Linear Technology - Now Part of Analog Devices
DC392A-B Linear Technology LTC1628 or LTC3728 Evaluation Kit visit Linear Technology - Now Part of Analog Devices
LF198AJ8 Linear Technology IC SAMPLE AND HOLD AMPLIFIER, CDIP8, Sample and Hold Circuit visit Linear Technology - Now Part of Analog Devices
LF198S Linear Technology IC SAMPLE AND HOLD AMPLIFIER, PDSO, Sample and Hold Circuit visit Linear Technology - Now Part of Analog Devices
LF198AS Linear Technology IC SAMPLE AND HOLD AMPLIFIER, PDSO, Sample and Hold Circuit visit Linear Technology - Now Part of Analog Devices

CD4013 gate diagram

Catalog Datasheet MFG & Type PDF Document Tags

fsk modulation and demodulation using Xr2206

Abstract: lm 2206 for frequency modulation gate inputs, the maximum voltage rating at any pin may be reached before the absolute maximum current , level, the frequency at the two outputs is y2 what is normally seen there. The block diagram shows the , -2123 PSK Mod/Demod 1200 BPS H CD-4049 Hex Inverter I CD-4016 Quad B1 - Lateral Switch J CD-4013 Dual D Flip-Flop K CD-4013 Dual D Flip-Flop L XR-1488 Quad Line Driver M XFI-1489 Quad Line Receiver N XR 4194 , CD4011 Quad 2 Input Island Gate R 8048/8748 Microprocessor CI C2 C3 C4 C5 C6 C7 C8 C9 C10 C11
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fsk modulation and demodulation using Xr2206 lm 2206 for frequency modulation Cd4013 XR-4741 F-7404 TDA 4608 XR-2123A XR-2123 T1-T2220 Q1-2N4403 Q3-2N4401 2N4401

CD4013

Abstract: cd4017 . 5 - Functional diagram o f dual D flip-flop type CD4013. T o ta l P o w e r S.S x 10'^ JiW = 5.5 , e C D 4 5 1 8 , a B C D u p - 9 2 C S -2 9 2 4 4 R I Fig. 2 · Detailed diagram o f , characteristics curve » for type CD4013. F o r a J o h n s o n c o u n te r, w h ich o p e ra te s by fe e d in , 8 9 Fig. 9 - External gate required b y Johnson counter; counting sequence requiring only one , c o n tro ls , a n d freq u e n c y sy n th esis. .* 1 ` 'o »2 *
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ICAN-6552 cd4017 IC CD4013 CD4024 johnson decade counter IC CD4017 ic cd4017 CD4013 gate diagram

timer ic cd4020

Abstract: CD4026 ic pin diagram 25 cd4011 2.5 cd4049 7.5 cd4095 7.5 cd40104 25 cd4012 2.5 cd4050 7.5 cd4096 7.5 cd40105 25 cd4013 , ® RADS (SI) ON CD4000-SERIES INTEGRATED CIRCUITS (ALUMINUM GATE CMOS ON BULK SILICON) Latchup Latchup , Functional Diagrams â'""DO St h=atb+c M 92CS - 2475 7 Dual 3-lnpul NOR Gate Plus Inverter CD4000B (File No. 985) 92CS - 2 4 762 Quad 2-lnput NOR Gate CD4001B (File No. 985) (File No. 945) Dual 4-lnput NOR Gate CD4002B (File No. 985) 18-Stage Static Shift Register CD4006B (File No. 1033) Jrti . Â
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timer ic cd4020 CD4026 ic pin diagram CD4020 timer ic ASTABLE MULTIVIBRATOR CD4060 cd4010g IC Cd4020 CD4000-S CD4000B-S CD4000B-

diagram of LED matrix using 4017

Abstract: 4017-DECADE COUNTER form a AND gate so the clock pulse will be passed to the right side counter when the sequence starts. When the right counter reaches the 10th count, pin 11 will move high enabling the AND gate on the right , drawing below the schematic diagram and note the solderless breadboard is arranged in rows labeled A-J , with all parts. Refer to the schematic diagram, and install the various other components so they , AM line of the CD4013. The stop time is programmed in the same manner. Two additional push buttons
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diagram of LED matrix using 4017 4017-DECADE COUNTER ic 4017 decade counter datasheet ic 4017 IRFZ44 mosfet IRFZ44 mosfet for square wave inverter CD4516 74HC138 74HCT138 74HC14 74HCT14 2N3053

4017 COUNTER IC

Abstract: ic 4017 decade counter diodes (1n914) and 15 resistor form a AND gate so the clock pulse will be passed to the right side , enabling the AND gate on the right to pass the clock pulse to the left side counter. As the left side , below the schematic diagram and note the solderless breadboard is arranged in rows labeled A-J, and , parts. Refer to the schematic diagram, and install the various other components so they connect to the , AM line of the CD4013. The stop time is programmed in the same manner. Two additional push buttons
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4017 COUNTER IC ic 4017 decade counter ic 4017 PIN DIAGRAM power inverter schematic diagram irfz44 4017 decade counter with 10 decoded outputs IC 4017 decoder ic 1N4001 2N2219A

design of the IC CD4013

Abstract: CD4013 DATA SHEET On-Board Gating of Chip-Enable Signals Memory Write-Cycle Completion 6ns CE Gate Propagation Delay s , WDPO CE IN Figure 1. Block Diagram SP791DS/08 SP791 Low Power Microprocessor Supervisory with , Input. This input can be tied to an external momentary pushbutton switch, or to a logic gate output , . Manual-Reset Timing Diagram Figure 3. Diode "OR" connections allow multiple reset sources to connect to MR , 70ns Figure 5. WDI, WDO and WDPO Timing Diagram (VCC mode). Figure 4. Adding an external
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MAX791 design of the IC CD4013 CD4013 DATA SHEET CD4013 internal diagram CD4013 PIN DIAGRAM 1N4148 74HC04 SP791EP SP791EN SP6660EU/TR SP6660EU-L/TR

SP791

Abstract: design of the IC CD4013 On-Board Gating of Chip-Enable Signals Memory Write-Cycle Completion 6ns CE Gate Propagation Delay s , Figure 1. Block Diagram SP791DS/08 SP791 Low Power Microprocessor Supervisory with Battery , Input. This input can be tied to an external momentary pushbutton switch, or to a logic gate output , . Manual-Reset Timing Diagram Figure 3. Diode "OR" connections allow multiple reset sources to connect to MR , 70ns Figure 5. WDI, WDO and WDPO Timing Diagram (VCC mode). Figure 4. Adding an external
Sipex
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CD4013 equivalent CD4013 alternative SP791CN

IC 7447 bcd to 7 segment decoder

Abstract: circuit of bcd to 7 segment decoder using ic 7447 integration Reference voltage integration Integrator output zero Internal analog gate status for each phase , tRI tsi 1-104 PERSONAL COMPUTER DATA ACQUISITION ADC TC835 Table I. Internal Analog Gate Status , signal. 1 SW, S W r, Internal Analog Gate Status SW ri SW z SW r Closed Closed SW i , ^ 6.8V ZENER 1 Figure 6 Digital Section Functional Diagram GROUND Figure 5 Using an , INPUT r ANALOG COMMON B2 B1 XÍ ~ !h 1/2 0 CD4013 R STROBE OR n r> 1/4 CD4030
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IC 7447 bcd to 7 segment decoder circuit of bcd to 7 segment decoder using ic 7447 LS 7447 specification ic 7447 BCD to 7-segment application of cd4081 AM 770 DENSITY ZERO CALIBRATION TC7135 ICL7135 MAX7135 SI7135 TC7660 WI8888

CD4013 equivalent

Abstract: 4 digit MULTIPLEXED 7 segment display 7 ~ ~ S /- / 7 FUNCTIONAL BLOCK DIAGRAM D4 SEGMENT OUTPUTS TC7211A D2 SEGMENT OUTPUTS , FUNCTIONAL BLOCK DIAGRAM D4 SEGMENT OUTPUTS TC7212A v *â'" »» _ m m * 7 WIDE , brightness control input is transferred 1othe output transistor gate for "ON" segments. The brightness , ir CD4071 B8 D1 1/4 CD4030 1/2 a CD4013 CLK S R £ Hgure 6.4-1/2 Digit ADC
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SY6522 4 digit MULTIPLEXED 7 segment display binary to led display decoder TC7212 CD4061 4-digit 7 segment display driver ICM7211A DF411 CD4054A ICL8052I 00077D

cd4090

Abstract: CD 4090 . 3 shows an exam ple o f a CD4001 N O R gate functional test. V p j) is selected to cover the desired , fully tested, as shown by the timing diagram. OS Q7 Q8 V d o - 16 ©©©©©©©© © Output Enable S 3 , waveforms shown in the timing diagram o f Fig. 5 to th e device under test, in this case th e CD 4094B o f , interm ediate levels depending on the device type. The timing diagram, Fig. 5, shows 0-level d ata being , are at logic 0. The following clock pulses, those @ © ' Fig. 4 - Functional diagram o f the
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ICAN-6525 cd4090 CD 4090 datesheet CD4001N CMOS 4000B series rca CD 4013 ICAN-6532 S157CM MD154 CD4013A/B CD4029A/B

CD4513

Abstract: CD4513 bcd IN SW1 SWITCH OPEN SWITCH CLOSED ­ IN Figure 3A. Analog Circuit Function Diagram , output zero Internal analog gate status for each phase is shown in Table 1. ANALOG INPUT SIGNAL , . Internal Analog Gate Status Conversion Cycle Phase + SWRI Internal Analog Gate Status ­ SWRI , UNDER­ RANGE 26 21 STROBE BUSY Figure 6. Digital Section Functional Diagram TC04 20 , 2 6.8 k D 1/4 CD4081 +5V 1/4 CD4030 1/2 Q CD4013 CLK S R Negative Supply Voltage
TelCom Semiconductor
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CD4513 CD4513 bcd CD4513 internal diagram cd4013 pin configuration 2-DIGIT 7-SEGMENT LED DISPLAY 4v CD4013 application

ICM72171

Abstract: ICM7109 Functional Block Diagram ZERO 4 T.G. 4 D1 10 ZERO UP/DN COUNT U/D CL CARRY 1 4 T.G. 4 D2 10 ZERO U/D CL , . Figure 2 shows control outputs timing diagram. Display Outputs and Control The Digit and SEGment drivers , how to cascade counters and retain correct leading zero blanking. The NAND gate detects whether a , : CD4011B COUNT INPUT 20 GATE 8 ICM7217 COUNT LED DISPLAY FIGURE 19A. 300µs GATE 50µs STORE 1s , 23 8 9 10 14 LOW ORDER 15 - 19 21, 22 V+ 1/ D CD4013 Q CL 2 50k 3k 50k NPN
Harris Semiconductor
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ICM7109 ICM72171 ICM7027A 4 digit object counter circuit lCM7217A lN914 ICM7217A ICM7217B ICM7217C ICM7207A 24288MH

ICM7217A

Abstract: icm7109 15 D4 Functional Block Diagram 4 ZERO 4 T.G. T.G. 1 4 D1 10 VDD T.G , /BORROW output when it is being used for cascading. Figure 2 shows control outputs timing diagram , 22) shows how to cascade counters and retain correct leading zero blanking. The NAND gate detects , 0.47µF C 8 GATE TR CV 1 14 5 RESET VSS 20 GND INVERTERS: CD40106B NANDS: CD4011B COUNT INPUT FIGURE 19A. 300µs 1s GATE 50µs STORE RESET FIGURE 19B. FIGURE 19
Harris Semiconductor
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ICM7217AIPI IC 7217 Unit COUNTER CD4069 equivalent CD4069 PIN DIAGRAM AND IC CD4011 cd4069 on off switch

CD4513

Abstract: si7135 OPEN SWITCH CLOSED Figure 3A. Analog Circuit Function Diagram 4 Figure 3D. Reference Voltage , (t) dt = VR tRI , RC RC 0 Internal analog gate status for each phase is shown in Table 1. ANALOG , PERSONAL COMPUTER DATA ACQUISITION A/D CONVERTER TC835 Table 1. Internal Analog Gate Status Conversion , Closed Closed* Closed Closed ­ SWI SW RI + Internal Analog Gate Status ­ SW RI SWZ SW R , UNDER­ RANGE 26 STROBE 21 BUSY Figure 6. Digital Section Functional Diagram REF IN TC04
TelCom Semiconductor
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LITRONIX LM3113 3 digit common cathode 7 segment display 12 pin

CD4513

Abstract: max7135 Circuit Function Diagram 3-68 Figure 3D. Reference Voltage Integration Cycle TELCOM SEMICONDUCTOR , Reference voltage integration Integrator output zero 3 4 Internal analog gate status for each phase , PERSONAL COMPUTER DATA ACQUISITION A/D CONVERTER TC835 Table 1. Internal Analog Gate Status Conversion Cycle Phase + SWRI Internal Analog Gate Status ­ SWRI SWZ SWR SW1 Closed SWI , Section Functional Diagram TC04 20 k 22 DIGITAL GND V+ 2 SIGNAL INTE SYSTEM 10,000
TelCom Semiconductor
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12 pin common anode 7-segment display 368 bcd CD4513 internal diagram 7447 7-segment display Understanding Ratiometric Conversions pin diagram of CD4081 LM311

4 digit object counter circuit

Abstract: CD4069 equivalent RESET 14 15 SEG c RESET 14 15 D4 Functional Block Diagram 4 ZERO 4 T.G. T.G , shows control outputs timing diagram. The CARRY/BORROW output is a positive going pulse occurring , zero blanking. The NAND gate detects whether a digit is active since one of the two segments a or b , 2 6 ICM7217 8 GATE TR COUNT TH VSS 0.47µF C CV 14 5 1 RESET VSS 20 GND COUNT INPUT INVERTERS: CD40106B NANDS: CD4011B FIGURE 19A. 300µs 1s GATE
Intersil
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4 Digit counter 7217 CD4069 internal diagram 555 TIMER APPLICATIONS tachometer CD4069 Application 7-segment common anode cd4069 on off 888-IN

7 segment common anode

Abstract: IC CD4013 pin diagram for 7 segment RESET 14 15 D4 Functional Block Diagram 4 ZERO 4 T.G. T.G. 1 4 D1 10 T.G , control outputs timing diagram. The CARRY/BORROW output is a positive going pulse occurring typically , zero blanking. The NAND gate detects whether a digit is active since one of the two segments a or b , 9 3 VDD STORE 24 0.047µF 1K LED DISPLAY RB 2 6 ICM7217 8 GATE TR , : CD4011B COUNT INPUT FIGURE 19A. 300µs 1s GATE 50µs STORE RESET FIGURE 19B. FIGURE 19
Intersil
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7 segment common anode IC CD4013 pin diagram for 7 segment CD4069 PIN DIAGRAM AND DATA SHEET information comes from thumbwheel switches, the d CD4011 oscillator ICM7213 ISO9000

CD4513

Abstract: Circuit Function Diagram TC835-8 11/5/96 Figure 3D. Reference Voltage Integration Cycle 4 © 2001 , signal integration Reference voltage integration Integrator output zero Internal analog gate status , Converter TC835 Table 1. Internal Analog Gate Status Conversion Cycle Phase SWI + SWRI Internal Analog Gate Status â'" SWRI Input Signal Integration SWR SW1 Closed System , Microchip Technology Inc. 25 Figure 6. Digital Section Functional Diagram 6.8 kâ"¦ V+ 22
Microchip Technology
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DS21478A

4 digit object counter circuit

Abstract: two digit common anode multiplexed 7-segment disp 14 15 D4 Functional Block Diagram 4 ZERO 4 T.G. T.G. 1 4 D1 10 VDD , shows control outputs timing diagram. The CARRY/BORROW output is a positive going pulse occurring , zero blanking. The NAND gate detects whether a digit is active since one of the two segments a or b , DISPLAY RB 2 6 ICM7217 8 GATE TR COUNT TH VSS 0.47µF C CV 1 14 5 , GATE 50µs STORE RESET FIGURE 19B. FIGURE 19. INEXPENSIVE FREQUENCY COUNTER STOP LOGIC TO
Intersil
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two digit common anode multiplexed 7-segment disp CD4013 UP DOWN COUNTER IC CD4069 not gate intersil icm7217 4-Digit, LCD Display tachometer counter display driver

CD4069 equivalent

Abstract: icm7217 Diagram ZERO 4 T.G. 4 D1 10 VDD ZERO UP/DN COUNT U/D CL CARRY 1 4 T.G. 4 D2 10 ZERO U/D CL CARRY 2 4 T.G , diagram. Display Outputs and Control The Digit and SEGment drivers provide a decoded 7-segment display , zero blanking. The NAND gate detects whether a digit is active since one of the two segments a or b is , GND 20 GATE 8 ICM7217 COUNT LED DISPLAY INVERTERS: CD40106B NANDS: CD4011B COUNT INPUT FIGURE 19A. 300µs GATE 50 µs STORE 1s RESET FIGURE 19B. FIGURE 19. INEXPENSIVE FREQUENCY COUNTER
Intersil
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three digit common anode multiplexed 7-segment display intersil frequency counter cd4000 logic devices 88-INTERSIL
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